clock gating

clock mesh
multi-voltage domains
multi-vt
power-gating to blocks to shut them off.

Need for Isolation Cells

Isolation cells are used in designs where power gating is implemented. Signals t
raversing from a relatively OFF block to a relatively ON block (i.e. signal sour
ce power can be ON/OFF when destination is ON whereas source will always be OFF
when destination power is OFF) needs insertion of isolation logic at the interfa
ce. Two reasons why isolation of the signal is required are:
To prevent short-circuit current
To prevent data corruption
Leakage
Gate-leakage
A decap cells is basically a large NMOS or PMOS transistor. In the case of NMOS,
the gate tied to VDD and the source and drain tied to VSS, and the vice versa f
or PMOS. That is, the gate capacitance is used as the decoupling capacitance. In
this case, there is an active high inversion channel and the structure is simil
ar to a parallel plate capacitance
1
with the dielectric being the gate oxide. The conduction mechanism is primarily
quantum-mechanical tunneling.
Current from gate oxide leakage
For a constant oxide thickness equation 1 becomes,
VoxideeVI/12-? (3)
That is, as tox increases, the leakage current increases exponentially and incre
ases with Voltage

Sub-threshold conduction:
Sub-threshold conduction occurs when the transistor is in the off state, as in the
case of the NMOS in the inverter above. In this condition, there is a weak inver
sion in the channel and a small current still flows from source to drain. This su
b-threshold conduction current is given by:
Reverse biased Diode current:
In the NMOS transistor in the inverter, the substrate (p) is tied to VSS and the
node Vout (nwell) is tied to VDD. This forms a reverse-biased pn junction.
In summary, the following can be concluded:
1. As Voltage increases, leakage current increases from sub-threshold conduction
.
2. As temperature increases, leakage current increases from reverse-bias current
.

Variation
There are two source classes of variation that must be considered in design, glo
bal and local. Global chip-to-chip variations cause performance differences amon
g dies and are modeled as operating corners. Local on-chip variations cause perf
ormance differences among transistors within the same die and are modeled as an
added derating factor to skew calculations. What are the specific causes of thes
e local variations?
Transistors located in close proximity on the same chip exhibit variation in the
ir characteristics due to random manufacturing variations in:
the number and location of doping atoms
the length and width of the transistor channel
the thickness of oxide layers across the die
Timing derating is the universally accepted method to model the maximum OCV that
the design is expected to incur. Newer technology nodes feature increased gate
speeds as well as increased susceptibility to variation. Because of this, the de
rating factor has also
increased, and today it is common to see derating between 5 percent and 10 perce
nt. Thus, it becomes necessary to design circuit structures that are inherently
variation tolerant to reduce the adverse impact of OCV derating.
Clock mesh is a clocking scheme employed by high-performance design teams to ach
ieve low skew and high OCV tolerance. The large impact of OCV derating on conven
tional clock trees motivates mainstream design groups to also consider clock mes
h. An examination of clocking structures explains why.
Routing is a classic problem in VLSI design and its basic version appears fairly
straightforward. Divide the cell layout into equal-sized tiles (or gcells) where
each tile has capacity
constraints that represent the number of wires that can physically cross each of
the boundaries of the
tile. A solution to the global routing problem consists of a routing of the term
inals of each net through
adjacent (contiguous) gcells, such that each gcell s capacity constraints are sati
sfied. The threedimensional generalization breaks each tile into a separate tile
for each metal layer and then permits
via connections between adjacent tiles that have the same (x,y) coordinates. Of
course, this is an
abstraction of the real routing problem [1] which has grown much more complex wi
th the advent of
subwavelength lithography and CMP effects, and more generally, with the steady p
PTSI
transfer voltage from multiple aggressors to victim during transition.
clock reconvergence pessimissim - (max delay of element - min delay of element)
for setup - different edges of clocks and so crpr should not be removed.