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Experiment No 1
Realization of Boolean Expression using Logic gates.
Aim: Simplification and realization of given Boolean expression using logic gates and
universal gates.
Components Required:
Particulars
Sl
No
01 IC 7404, 7408, 7410,7427
02 IC 7400, 7402
Range
Quantity
-----
01 each
02 each
Design :
Example Y = ( A + B C ) ( B + C A )
a) Simplification for Basic gates.
Y=(A+BC)(B+CA)
= AB + AA C + BBC + ABC C
= AB + A C + B C
( A.A = A, B.B = B & C C = 0 )
b) Simplification for NAND gate.
Y=(A+BC)(B+CA)
Y=(A+BC)(B+CA)
= (AB) (BC) (AC)
c) Simplification for NOR gate.
Y=(A+BC)(B+CA)
Y = ( A + B ) ( A + C ) (B + C ) (B + A)
(Distributive Law)
Y = ( A + B ) ( A + C ) (B + C )
Y = ( A + B ) ( A + C ) (B + C )
Y=(A+B)+(A+C)+(B+C)
Dept. of E&C
K.I.T - Tiptur
Logic Diagram:
Using Basic gate.
Dept. of E&C
K.I.T - Tiptur
Truth Table:
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Y
0
0
0
1
1
0
1
1
Procedure:
01. The IC is fixed on the IC trainer and Vcc & GND connections are given from 5V
Supply.
02. Connections are made as shown in Logic diagram.
03. All the inputs are given to toggle switches and outputs to LEDs.
04. Truth table is verified for different combinations of input.
Result:
Dept. of E&C
Staff Signature
Remarks
K.I.T - Tiptur
Experiment No 2
Realization of Half/Full adder and Half/Full Subtractors using logic gates.
Aim : 1. To realize using basic gates: a) Half adder. b) Half substractor c) Full adder
d) Full substractor.
2. To realize universal(NAND) gate: a) Half adder. b) Half substractor c) Full adder
d) Full substractor.
Components Required:
Particulars
Sl
No
01 IC 7408, 7432, 7486
02 IC 7400
Range
Quantity
-----
01 each
02 each
Outputs
Sum(S) Carry(C)
0
0
1
0
1
0
0
1
Realization for carry
0
0
1
1
0
0
1
0
0
1
1
S = AB + AB
=AB
C = AB
Logic Diagram:
Half adder using basic gates:
A
B
7486
3
7408
3
Dept. of E&C
Sum
Carry
K.I.T - Tiptur
7400
6
7400
12
3
7400
10
Sum
11
13
7400
8
B
1
7400
3
Carry
Outputs
Difference Borrow
(D)
(Bo)
0
0
1
1
1
0
0
0
0
1
0
1
0
0
1
0
1
1
Bo = AB
0
0
1
1
D = AB+AB
= AB
Logic Diagram:
Half Subtractor using basic gates:
1
A
B
7486
3
1
7404
2
1
2
Dept. of E&C
7408
3
Bo
K.I.T - Tiptur
A
0
0
0
0
1
1
1
1
Inputs
B
Ci
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Outputs
Sum (S) Carry Out (Co)
0
0
1
0
1
0
0
1
1
0
0
1
0
1
1
1
Realization for sum
BCi
00
0
01
1
11
0
10
1
BCi
A
S = ABC+ABC+ABC+ABC
= C (AB)
Dept. of E&C
00
0
01
0
11
1
10
0
K.I.T - Tiptur
Logic Diagram:
Full adder using basic gates:
A
0
0
0
0
1
1
1
1
Inputs
B
0
0
1
1
0
0
1
1
Dept. of E&C
C
0
1
0
1
0
1
0
1
Outputs
Diff (D) Borrow(Bo)
0
0
1
1
1
1
0
1
1
0
0
0
0
0
1
1
K.I.T - Tiptur
BCi
00
0
01
1
11
1
10
1
00
0
01
1
11
0
10
1
Bo = AB+ABC+ABC
= AB+C(AB)
D = ABC+ABC+ABC+ABC
= ABC
A
B
7486
7404
1
4
7404
7408
4
5
7408
1
2
Half subtractor
7432
1
2
Bo
Half subtractor
Dept. of E&C
K.I.T - Tiptur
Procedure:
1. The IC is fixed on the IC trainer and Vcc & GND connections are given from 5V
Supply.
2. Connections are made as shown in the Logic diagram.
3. All the inputs are connected to the switches & output to the LEDs.
4. The truth table is verified for different combinations of input.
Result:
Dept. of E&C
Staff Signature
Remarks
K.I.T - Tiptur
Experiment No.3
Parallel adder
Aim: (i) Realization of parallel adder/Subtractors using 7483 chip
(ii) BCD to Excess-3 code conversion and vice versa.
Component required:
Sl.No
01
Particulars
IC 7483, 7486
Range
-------
Quantity
1 each
S4
Co
Ci
GND
B1
A1
S1
S2
B2
A2
7483
A4
S3
A3
B3
Vcc
B3
1
3
8
10
A4
A3
A2
A1
B2
16
4
B1
11
7483
7486
B4
Vcc
+5V
15
2
6
S4
S3
S2
9
14
S1
Co
Ci
13
12
Gnd
Ci
Dept. of E&C
10
K.I.T - Tiptur
Decimal
No
A
B
9
5
12 8
Carry
in
Ci
0
0
Inputs
Binary Digit 1
Outputs
Binary Digit - 2 Carry
Sum
out
A4 A3 A2 A1 B4 B3 B2 B1
Co
S4 S3 S2 S1
1
0
0
1
0
1
0
1
0
1 1 1 0
1
1
0
0
1
0
0
0
1
0 1 0 0
Outputs
Binary Digit - 2 Borrow
Difference
Decimal Borrow
No
in
out
A B
Ci
A4 A3 A2 A1 B4 B3 B2 B1
Co
S4 S3 S2 S1
9
5
1
1
0
0
1
0
1
0
1
1
0 1 0 0
8 12
1
1
0
0
0
1
1
0
0
0
1 1 0 0
Note : If Co = 1 answer is +ve, if Co=0 answer is ve, take 2s complement of the result
to get the magnitude.
(ii) BCD to Excess-3 Code Conversion
Truth Table for BCD to Excess-3 conversion:
BCD Number
Excess 3 Code
A4 A3 A2 A1
S4 S3 S2 S1
0
0
0
0
0
0
1
1
0
0
0
1
0
1
0
0
0
0
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
0
0
1
1
1
0
1
0
1
1
0
0
0
0
1
1
0
1
0
0
1
0
1
1
1
1
0
1
0
1
0
0
0
1
0
1
1
1
0
0
1
1
1
0
0
Add 3 to BCD number to get Excess-3 code
Realization using 7483:
Decimal
No
A
B
3
0
3
Dept. of E&C
Carry
in
Ci
0
0
Inputs
Binary Digit 1
Outputs
Binary Digit 2 Carry Excess-3 Code
(BCD Number)
out
A4 A3 A2 A1 B4 B3 B2 B1
Co
S4 S3 S2 S1
0
0
1
1
0
0
0
0
0
0 0 1 1
0
11
K.I.T - Tiptur
Decimal
No
A
B
3
3
3
7
Carry
in
Ci
1
1
Inputs
Binary Digit 1
Outputs
Binary Digit 2 Carry
BCD
(Excess 3 Code)
out
A4 A3 A2 A1 B4 B3 B2 B1
Co
S4 S3 S2 S1
0
0
1
1
0
0
1
1
1
0 0 0 0
0
0
1
1
0
1
1
1
0
1 1 0 0
Procedure:
01. The IC is fixed on the IC base board and Vcc & Gnd connections are given from
5V supply.
02. Connections are made as shown in the Logic diagram.
03. All the inputs are connected to the switches & output to the LEDs.
04. The truth table is verified for different combinations of input.
Note: Keep the B inputs i.e B4B3B2B1 = 0011 as constant and vary the A inputs i.e
A4A3A2A1 for both BCD to Excess-3 and Excess-3 to BCD conversions.
Result:
Date of Completion of Exp.
Dept. of E&C
Staff Signature
12
Remarks
K.I.T - Tiptur
Experiment No: 4
Code Conversion
Aim: To realizes a code converter: (i) Binary to Gray code conversion (ii) Gray to
Binary code conversion.
Component Required:
Sl.No
01
Particulars
IC 7486
Range
------
Quantity
1 No
Gray Outputs
G3
G2
G1
G0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
0
0
1
1
0
0
0
G2
B1 B0
00
B3 B2
01
11
10
00
01
G3 = B3
B1 B0
00
01
01
01
11
11
10
B3 B2
00
1
11
10
G0
B1 B0
G2 = B3 B2 + B3 B2
G2 = B3 B2
Dept. of E&C
10
11
1
G1 = B2 B1 + B1 B2
G1 = B1 B2
13
10
1
B3 B2
00 01 11 10
00
1
1
G0 = B1B0 + B1 B0
G0 = B1 B0
K.I.T - Tiptur
G3
7486
1
2
B2
G2
G1
G0
7486
4
5
B1
7486
10
B0
Gray Code to Binary conversion:
Truth Table:
G3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Gray Inputs
G2 G1
0
0
0
0
0
1
0
1
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
0
1
0
1
0
0
0
0
Dept. of E&C
G0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
Binary Outputs
B3 B2 B1 B0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
14
K.I.T - Tiptur
B2
G1 G0
G3 G2
B0
G1 G0
00
01 11 10
00 01 11 10
00
1 1
G3 G2
00
01
01
11
10
B3 = G3
G1 G0
11
1
10
B2 = G3 G2 + G3 G2
B2 = G2 G3
G3 G2
01
1
00 01 11 10
00
1
1
11
10
1
1
G2
1
2
G1
4
5
G0
9
10
B2
B1
7486
7486
B0
Procedure:
1. The IC is fixed on the IC zip socket and Vcc & Gnd connections are given from
5V Supply.
2. Connections are made as shown in the Logic diagram.
3. All the inputs are connected to the switches & output to the LEDs.
4. Truth table is verified for different combinations of input.
Result:
Date of Completion of Exp.
Dept. of E&C
Staff Signature
15
B0 = G3 G2 G1 G0
B1 = G1 G2 G3
G3
Remarks
K.I.T - Tiptur
Experiments No. 5
Multiplexer / Demultiplexer
Aim : i) To realize and verify the truth table of:
Component Required:
Sl.No
01
02
Particulars
IC 7410
IC 7420 , 74153
Range
-----------
Quantity
2 No
1 each
Truth Table:
Select Lines
S1
S0
0
0
0
1
1
0
1
1
Dept. of E&C
Output
Y
Y=D0
Y=D1
Y=D2
Y=D3
16
K.I.T - Tiptur
S1
S0
13
2
1
5
4
3
12
74LS10
74LS10
74LS10
9
10
11
D0
74LS10
1
2
13
D1
12
74LS10
3
4
5
D2
74LS20
1
2
4
5
74LS10
9
10
11
D3
Truth Table
D0
0
1
X
X
X
X
X
X
Inputs
D1 D2
X
X
X
X
0
X
1
X
X
0
X
1
X
X
X
X
Dept. of E&C
D3
X
X
X
X
X
X
0
1
Select lines
S1
S0
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Output
Y
0
1
0
1
0
1
0
1
17
K.I.T - Tiptur
16
Vcc
Select S1
15
Enable Eb
D3(a)
14
Select S0
D2(a)
13
D3(b)
D1(a)
12
D2(b)
D0(a)
11
D1(b)
Ya (O/P)
10
D0(b)
Gnd
IC 74153
Enable Ea
Yb (O/P)
Function table:
Inputs
Data Inputs
Data Select
S1
X
0
0
0
0
1
1
1
1
S0
X
0
0
1
1
0
0
1
1
Dept. of E&C
D0
X
0
1
X
X
X
X
X
X
D1
X
X
X
0
1
X
X
X
X
D2
X
X
X
X
X
0
1
X
X
D3
X
X
X
X
X
X
X
0
1
18
Enable
Output
Data Output
E
1
0
0
0
0
0
0
0
0
Y
0
0
1
0
1
0
1
0
1
Remarks
Y=0
Y=D0
Y=D1
Y=D2
Y=D3
K.I.T - Tiptur
S0
S1
7400
7400
10
9
7400
Y0
7400
11
Y1
7400
Y2
7400
Y3
12
13
1
2
4
5
Truth Table:
Select Lines
S1
S0
0
0
0
1
1
0
1
1
Dept. of E&C
Y0
0
1
1
1
Outputs
Y1 Y2
1
1
0
1
1
0
1
1
Y3
1
1
1
0
19
K.I.T - Tiptur
Decoder / Demultiplexer:
16
1 S0
15
1 S1
14
2 S0
1 (Y0)
13
2 S1
1 (Y1)
12
2 (Y0)
1 (Y2)
11
2 (Y1)
1 (Y3)
10
2 (Y2)
Gnd
2 (Y3)
IC 74139
E1 Enable
Vcc
E2 Enable
Truth Table:
Enable
E
1
0
0
0
0
Select Lines
S1
X
0
0
1
1
S0
X
0
1
0
1
Outputs
Y0
1
0
1
1
1
Y1
1
1
0
1
1
Y2
1
1
1
0
1
Y3
1
1
1
1
0
Dept. of E&C
20
K.I.T - Tiptur
For Sum:
A=0, B=0
0
I0a=0
A=0, B=1
1
I1a=1
A=1, B=0
1
I2a=1
A=1, B=1
0
I3a=0
Remark
Required Output
Input to selected lines
A=0, B=1
0
I1b=0
A=1, B=0
0
I2b=0
A=1, B=1
1
I3b=1
Remark
Required Output
Input to selected lines
For Carry:
A=0, B=0
0
I0b=0
Logic 1
Vcc
16
B
A
Logic 0
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Sum
0
1
1
0
1
0
0
1
Ya
1
7
Sum
Carry
Yb 9
8
Eb
15
Gnd
Ea
74153
3 I3a
4 I2a
I1a
5
6 I0a
S0
14
S1
2
13 I3b
I2b
12
I1b
11
I0b
10
Carry
0
0
0
1
0
1
1
1
For Sum:
C
0
1
A=0, B=0
0
1
I0a=C
Dept. of E&C
A=0, B=1
1
0
I1a=C
A=1, B=0
1
0
I2a=C
A=1, B=1
0
1
I3a=C
21
Remark
Required Output
Input to selected lines
K.I.T - Tiptur
For Carry:
C
0
1
A=0, B=0
0
0
I0b=0
A=0, B=1
0
1
I1b=C
A=1, B=0
0
1
I2b=C
A=1, B=1
1
1
I3b=1
Remark
Required Output
Input to selected lines
1
7404
B
A
Logic 0
3 I3a
4 I2a
I1a
5
6 I0a
14 S0
2 S1
13 I3b
I2b
12
I1b
11
I0b
10
16
Ea
Ya
74153
Vcc
1
7
Sum
Yb 9
Eb
15
Carry
Gnd
Logic 1
B
0
1
0
1
Diff
0
1
1
0
Borrow
0
1
0
0
For Difference:
A=0, B=0
0
I0a=0
A=0, B=1
1
I1a=1
A=1, B=0
1
I2a=1
A=1, B=1
0
I3a=0
Remark
Required Output
Input to selected lines
A=0, B=1
1
I1b=1
A=1, B=0
0
I2b=0
A=1, B=1
0
I3b=0
Remark
Required Output
Input to selected lines
For Borrow:
A=0, B=0
0
I0b=0
Dept. of E&C
22
K.I.T - Tiptur
Logic 1
6 I0a
14 S0
2 S1
13 I3b
I2b
12 I1b
11
I0b
10
8
B
A
Ea
Ya
74153
I3a
I2a
4
5 I1a
1
7
Yb 9
Eb
Diff
Borrow
15
16
Gnd
Vcc
Logic 0
Full Subtractor using IC 74153
Truth Table:
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Diff
0
1
1
0
1
0
0
1
Borrow
0
1
1
1
0
0
0
1
For Difference:
C
0
1
A=0, B=0
0
1
I0a=C
A=0, B=1
1
0
I1a=C
A=1, B=0
1
0
I2a=C
A=1, B=1
0
1
I3a=C
A=0, B=1
1
1
I1b=1
A=1, B=0
0
0
I2b=0
A=1, B=1
0
1
I3b=C
Remark
Required Output
Input to selected lines
For Borrow:
C
0
1
A=0, B=0
0
1
I0b=C
Dept. of E&C
23
Remark
Required Output
Input to selected lines
K.I.T - Tiptur
3 I3a
4 I2a
I1a
5
6 I0a
14 S0
2 S1
13 I3b
I2b
12
I1b
11
I0b
10
B
A
Logic 0
Logic 1
16
Ea
74153
7404
2
Ya
Vcc
1
7
Diff
Yb 9
8
Eb
15
Borrow
Gnd
13
G0
15
G1
G2
Dept. of E&C
1
7404
1S0
1S1
E1
74139
14
12
1Y0
11
1Y1
1Y2 10
9
1Y3
3 2S1
1
E2
24
2
4
7420
7420
B0
5
9
2Y0
2Y1
2Y2
2Y3
2S0
4
5
6
7
10
12
B1
13
B3
K.I.T - Tiptur
14
13
B0
15
B1
B2
1
7404
G0 = m (1,2,5,6)
G1 = m (2,3,4,5)
G2 = m (4,5,6,7)
1Y0
1S0
1S1
E1
74139
Binary Input
B2 B1
B0
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
1
0
1
0
0
1
0
1
11
1Y1
1Y2 10
1Y3 9
3 2S1
1
E2
1
2
4
5
7420
7420
4
5
6
7
10
12
G3
1. The IC is fixed on the IC zip socket and Vcc & Gnd connections are given from
5V Supply.
2. Connections are made as shown in the Logic diagram.
3. All the inputs are connected to the switches & output to the LEDs.
4. Truth table is verified for different combinations of input.
Result:
Dept. of E&C
Staff Signature
25
G1
13
Procedure:
G0
2Y0
2Y1
2Y2
2Y3
2S0
12
Remarks
K.I.T - Tiptur
Experiment No 6
Magnitude Comparator.
Aim:- a) To realization of One bit comparator.
b) To realization of Two bit comparator.
c) To study of 7485 magnitude comparator.
Component required:
Sl.No
01
02
Particulars
IC 7400
IC7402 , 7404, 7408, 7432, 7486
Range
-----------
Quantity
2 No
1 each
A=B
B
0
1
A<B
B
0
0
1
1
0
0
A>B = A B
0
1
0
0
1
1
0
1
A=B = A B + A B
0
1
0
0
0
1
1
0
A<B = A B
Logic diagram:
Truth table:
Inputs
A B
0
0
0
1
1
0
1
1
Dept. of E&C
Outputs
A<B A=B A>B
0
1
0
1
0
0
0
0
1
0
1
0
26
K.I.T - Tiptur
A>B
B1 B0
A1A0
00
01
11
10
A<B
B1 B0
00
0
1
1
1
01
0
0
1
1
11
0
0
0
0
10
0
0
1
0
B1 B0
00
1
0
0
0
A1A0
00
01
11
10
01
0
1
0
0
11
0
0
1
0
10
0
0
0
1
A1A0
00
01
11
10
00 01 11 10
0 1 1 1
0 0 1 1
0 0 0 0
0 0 1 0
Logic diagram:
A1
B1
A0
1
74LS04
2
B0
3
74LS04
4
74LS86
74LS04
74LS08
12
74LS86
4
5
13
74LS04
6
11
A=B
74LS32
74LS08
10
1
2
74LS08
10
9
74LS32
1
2
A<B
74LS32
4
5
A>B
74LS08
4
5
Truth Table:
A1
0
0
0
0
Inputs
A0 B1
0
0
0
0
0
1
0
1
Dept. of E&C
B0
0
1
0
1
Outputs
A<B A=B A>B
0
1
0
1
0
0
1
0
0
1
0
0
27
K.I.T - Tiptur
0
0
0
`0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
1
0
0
1
1
1
0
16
Vcc
I(A<B)
15
A3
I(A=B)
14
B2
I(A>B)
13
A2
A>B
12
A1
A=B
11
B1
A<B
10
A0
B0
Gnd
IC 7485
B3
Input Digit A
Input Digit B
Dept. of E&C
15
A3
13
A2
12
A1
10
A0
1
B3
14 B2
11
B1
9
B0
16
3
I(A=B)
I(A<B) 2
I(A>B) 4
A<B
7
A=B 6
A>B
5
8
28
Vcc
Inputs (From previous stage)
Outputs
Gnd
K.I.T - Tiptur
Procedure:
1. The IC is fixed on the IC zip socket and Vcc & Gnd connections are given from
5V Supply.
2. Connections are made as shown in the Logic diagram.
3. All the inputs are connected to the switches & output to the LEDs.
4. Truth table is verified for different combinations of input.
Result:
Date of Completion of Exp.
Dept. of E&C
Staff Signature
29
Remarks
K.I.T - Tiptur
Experiment No 7
Decoder / Encoder
Aim: a) Use of decoder chip (7447/7446) to display the given digit on a 7-segment
LED display.
b) Study of encoder chip IC 74147.
Component required:
Sl.No
01
02
03
Particulars
IC7447, MAN72, IC 74147, IC 74148
Trainer Kit
Wires
Range
----------------
Quantity
1 No
01 No
------
Logic diagram: Use of decoder chip (7447/7446) to display the given BCD digit on a
7-segment LED display.
BCD Inputs
7447
6 Q3
2
Q2
1
Q1
7
Q0
4
Vcc
RBO
Test
RBI
7-Segment Display
g
f
e
d
c
b
16
8
14
15
9
10
11
12
13
3
2
4
5
8
9
10
220
220
220
220
220
220
220
g
f
e
d
c
b
a
1
Vcc
Vcc
GND
Truth table:
Inputs
Q3 Q2 Q1 Q0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
Dept. of E&C
Output
on display
0
1
2
3
4
5
6
7
8
9
30
K.I.T - Tiptur
Vcc
16
NC
D
O\P
I/P3
I/P2
I/P1
I/P9
A
O\P
15
14
13
12
11
10
IC 74147
1
I/P4
I/P5
I/P6
I/P7
I/P8
Inputs
C
O\P
B
O\P
Gnd
Truth Table:
I/P1
X
X
X
X
X
X
X
X
0
1
I/P2
X
X
X
X
X
X
X
0
1
1
Dept. of E&C
I/P3
X
X
X
X
X
X
0
1
1
1
Decimal Inputs
I/P4 I/P5 I/P6
X
X
X
X
X
X
X
X
X
X
X
0
X
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I/P7
X
X
0
1
1
1
1
1
1
1
31
I/P8
X
0
1
1
1
1
1
1
1
1
I/P9
0
1
1
1
1
1
1
1
1
1
D
0
0
1
1
1
1
1
1
1
1
BCD outputs
C
B
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
A
0
1
0
1
0
1
0
1
0
1
K.I.T - Tiptur
16
E0
15
I/P3
GS
14
13
Inputs
I/P2 I/P1
12
I/P0
A0
O\P
11
10
IC 74148
1
I/P4
I/P5
I/P6
I/P7
E1
A2
O\P
A1
O\P
Gnd
Inputs
Truth Table:
Enable
Octal inputs
Binary outputs
E1
I/P0 I/P1 I/P2 I/P3 I/P4 I/P5 I/P6 I/P7 A2 A1 A0
X
X
X
X
X
X
X
X
X
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
X
X
X
X
X
X
X
0
0
0
0
0
X
X
X
X
X
X
0
1
0
0
1
0
X
X
X
X
X
0
1
1
0
1
0
0
X
X
X
X
0
1
1
1
0
1
1
0
X
X
X
0
1
1
1
1
1
0
0
0
X
X
0
1
1
1
1
1
1
0
1
0
X
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
Note :
1. Both E0 & Gs are active high when the enable I/P is high.
2. GS : Group signal is active low when any I/P is low
3. E0 : active low when all I/Ps are high.
Procedure:
1. The IC is fixed on the IC zip socket and Vcc & Gnd connections are given from
5V Supply.
2. Connections are made as shown in the Logic diagram.
3. All the inputs are connected to the switches & output to the LEDs.
4. Truth table is verified for different combinations of input.
Result:
Date of Completion of Exp.
Dept. of E&C
Staff Signature
32
Remarks
K.I.T - Tiptur
GS
1
1
0
0
0
0
0
0
0
0
E0
1
0
1
1
1
1
1
1
1
1
Experiment No: 8
Flip-Flops
Aim : a) Realization of (i) JK Flipflop (ii) MSJK Flip flop (iii) T Flipflop and
(iv) D Flipflop using NAND gates.
b) Truth table verification of IC 7476 (JK Flipflop).
Component required:
Sl.No
01
02
Particulars
IC 7410
IC 7400,7476
Range
-----------
Quantity
2 No
01 each
Slave
7410
7410
1
2
13
9
10
11
12
7400
Qm
7400
10
9
Clock
7410
3
4
5
12
1
2
13
12
7410
Qm
13
Qs
11
Qs
7400
7400
3
4
5
7410
Cr
Circuit Diagram 1
Qm
1
0
Qm
Qm
0
1
Qm
Qs
1
0
Qs
Qs
0
1
Qs
Status
Set
Reset
No change
Reset
Set
Qm
Qm
Qs
Qs
Toggles
Dept. of E&C
33
K.I.T - Tiptur
Procedure:
1. Connection are made as shown in Logic diagram 1.
Case 1: Asynchronous:
2. in the absence of clock.
a) With preset = 0 and clear =1,the output is set.
b) With preset = 1 and clear = 0,the output is reset.
Case 2: Synchronous:
3. Both present and clear are made high.
4. All combination of inputs is applied at J & K.
5. During the raising edge of the clock of the clock pulse in each case master O/P
follows the JK logic.
6. During the falling edge of the clock pulse in each case slave o/p follows the
master o/p.
Logic Diagram of D Flip-Flop:
Master
74LS10
74LS10
1
2
13
1
7400
9
10
11
12
12
10
9
12
1
2
13
74LS10
3
4
5
7400
7400
Slave
Pr
13
3
4
5
Clock
11
7400
7400
74LS10
74LS10
Cr
Preset
Clear
Dept. of E&C
Clock
Status
Reset
Set
34
K.I.T - Tiptur
74LS10
74LS10
1
2
13
Slave
Pr
7400
9
10
11
12
12
10
9
12
1
2
13
74LS10
3
4
5
7400
13
3
4
5
Clock
11
7400
7400
74LS10
74LS10
Cr
Preset
Clear
Clock
Status
No Change
Toggles
Procedure:
1. Connection are made as shown in Logic diagram.
2. The Truth Table is verified.
Result:
Date of Completion of Exp.
Dept. of E&C
Staff Signature
35
Remarks
K.I.T - Tiptur
Experiments : 9
Asynchronous up / Down Counter using IC 7476
Aim: a) Rig up a 3-bit asynchronous up counter.
b) Rig up a 3-bit down counter.
c) Rig up a Mod N counter.
Component required:
Sl.No
01
02
Particulars
IC 7476
IC 7400
Range
-----------
Quantity
2 No
01 No
Q1
Q1
K2
GND
Q2
Q2
J1
7476
CLK1
PRE1 CLR1
J1
Vcc
CLR
H
L
L
H
J
X
X
X
L
K
X
X
X
L
Q
H
L
H
Q
Q
L
H
H
Q
Dept. of E&C
CLK
X
X
X
OUTPUTS
36
Toggle
K.I.T - Tiptur
MSB
Q1
Q0
Q2
Vcc
Vcc
JAPRE
7476
Clock
1
16
CLK
CLR
15
Q
14
_
6Q
J
7476
12
CLK
CLR
8
11
Q
10
_
Q
2
PRE
7476
16
15
Q
CLK
CLR
3
14
_
Q
3
Connect pin 5 to Vcc & pin 13 to GND for all 7476 IC
Vcc
Truth Table:
Clock
0
1
2
3
4
5
6
7
8
Q2
0
0
0
0
1
1
1
1
0
Q1
0
0
1
1
0
0
1
1
0
Q0
0
1
0
1
0
1
0
1
0
Wave Forms:
Dept. of E&C
37
K.I.T - Tiptur
Q0
MSB
Q1
Q2
Vcc
Vcc
J PRE
7476
Clock
1
16
CLK
CLR
3
15
Q
14
_
6Q
J
7476
12
CLK
CLR
8
11
Q
10
_
Q
2
PRE
7476
16
15
Q
CLK
CLR
3
14
_
Q
Vcc
Truth Table:
Clock
0
1
2
3
4
5
6
7
8
Q2
1
1
1
1
0
0
0
0
1
Q1
1
1
0
0
1
1
0
0
1
Q0
1
0
1
0
1
0
1
0
1
Wave Forms :
Dept. of E&C
38
K.I.T - Tiptur
Mod N Counters:
Logic Diagram for Mod 5up counter:
1
2
LSB
Q0
MSB
Q1
Q2
Vcc
Vcc
J PRE
7476
Clock
1
16
CLK
CLR
3
15
Q
14
_
6Q
J
7476
12
CLK
CLR
8
11
Q
10
_
Q
2
PRE
7476
16
15
Q
CLK
CLR
3
14
_
Q
Vcc
Truth Table:
Clock
0
1
2
3
4
5
Q2
0
0
0
0
1
0
Q1
0
0
1
1
0
0
Q0
0
1
0
1
0
0
Wave Forms:
Dept. of E&C
39
K.I.T - Tiptur
7400
J PRE
7476
CLK
16
CLR
3
MSB
Q1
Vcc
Clock
Q0
7
15
Q
14
_
6Q
J
7476
12
CLK
CLR
8
11
Q
10
_
Q
2
PRE
7476
16
Q2
15
Q
CLK
CLR
3
14
_
Q
Vcc
Truth Table:
Clock
0
1
2
3
4
Q2
1
1
1
1
0
Q1
1
1
0
0
1
Q0
1
0
1
0
1
1
1
1
When count becomes 3 preset the counter
Dept. of E&C
40
K.I.T - Tiptur
Procedure:
1. Connections are made as shown in the Logic diagram.
2. Clock pluses are applied one by one at the clock I/P and the O/P is observed at
Q0, Q1 & Q2.
3. Truth table is verified.
4. Continuous clock pluses are applied.
5. Waveforms at Q0, Q1 & Q2 are observed on CRO.
Result:
1)
2)
3)
4)
fclk = ___________
fQ0 = ___________
fQ1 = ___________
fQ2 = ___________
Dept. of E&C
Staff Signature
41
Remarks
K.I.T - Tiptur
Experiment No 10
3 Bit Synchronous Counter using IC 7476
Aim: To design and test a 3 bit Synchronous counter for the given sequence using IC
7476.
Component required:
Sl.No
01
02
03
04
Particulars
IC 7476
IC 7408
Trainer kit
Connecting wires
Range
---------------------
Quantity
2 No
01 No
1No
------
State Diagram:
00
11
00
11
01
10
01
10
State Table:
Clock
Q2
0
0
1
0
2
0
3
0
4
1
5
1
6
1
7
1
Dept. of E&C
Q0
0
1
0
1
0
1
0
1
State Change
Qn
Qn+1
0
0
0
1
1
0
1
1
42
J-K Input
J
K
0
X
1
X
X
1
X
0
K.I.T - Tiptur
Transition Table :
Present State
Q2
Q1
Q0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Next State
Q2
Q1
Q0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
FF-2
J2
K2
0
X
0
X
0
X
1
X
X
0
X
0
X
0
X
1
FF-1
J1
K1
0
X
1
X
X
0
X
1
0
X
1
X
X
0
X
1
FF-0
J0
K0
1
X
X
1
1
X
X
1
1
X
X
1
1
X
X
1
J0 = 1, K0 = 1
J1 = Q0, K1 = Q0
J2 = Q1.Q0, K2 = Q1.Q0
Logic Diagram for 3-bit Synchronous up counter:
LSB
Q0
MSB
Q1
Q2
Vcc
7408
Vcc
JAPRE
7
15
Q0
14
_
6Q0
7476
7476
Clock
1
16
CLK
FF-0
K0CLR
3
Vcc
JB
12
CLK
FF-1
K1CLR
8
11
Q1
10
_
Q1
2
PRE
JC
7476
1
16
15
Q2
CLK
FF-2
K2CLR
3
14
_
Q2
Dept. of E&C
43
K.I.T - Tiptur
Wave Forms:
clock
LSB QA
QB
MSB QC
Procedure:
1. Connections are made as shown in the Logic diagram.
2. Clock pulses are applied one by one at the clock I/P and the O/P is observed at Q0,
Q1, & Q2.
3. True table is verified.
4. Continuous clock pulses are applied.
5. Wave forms at Q0, Q1, & Q0 are observed on CRO.
Result:
1. fclk
= ___________
2. Fq0
= fclk / 2
= __________
3. fQ1
= fclk / 4
= ___________
4. fQ2
= fclk / 8
= ___________
Dept. of E&C
Staff Signature
44
Remarks
K.I.T - Tiptur
Experiment No 11
Counters using counter ICs
Decade Counter
Aim: Rig up a Mod N counter using IC 7490.
Component required:
Sl.No
01
Particulars
IC 7490
Range
------
Quantity
1 No
CP1
14
Clock I/P
Q0
Q1
Q2
Q3
12
11
Mod 5
Mod 2
CP2 1
Q3
0
0
1
Q2
Q1
0
0
0
0
0
0
Count
Count
Count
Count
Dept. of E&C
45
Q0
0
0
1
Remarks
Reset
Reset
Set to 9
K.I.T - Tiptur
CP1
14
Clock I/P
Q0
Q1
Q2
Q3
12
11
Mod 5
Mod 2
CP2 1
CP1
Clock I/P 14
Q0
Q1
Q2
Q3
12
11
Mod 5
Mod 2
CP2 1
Dept. of E&C
46
K.I.T - Tiptur
Q3
0
Q2
0
Q1
0
Q0
0
Clock
Q3
0
Q2
0
Q1
0
Q0
0
Wave Forms:
Mod 10 Counter (Decade Counter):
Mod 8 Counter:
fclk = ______ fQ0 = _______ fQ1 = _______ fQ2 = ______ fQ3 = ________
Dept. of E&C
47
K.I.T - Tiptur
Clock up
>5
Clock down
>4
Q0
Q1
Q2
Q3
10
Load
X
1
1
0
1
Clear
1
0
0
0
0
13
11
MSB
P0
Clk-up
X
1
X
1
12
LSB
Function Table:
Borrow
74192
14
15
Clear
Carry
Clk-down
X
1
X
1
P1
P2
P3
Load (L)
Mode
Reset to zero
Up-count
Down-count
Preset
Stop count
2
Clock I/N
>5
VCC
>4
Clear
14
12
7
74192
3
11
Load (L)
9 10 1 15
13
MSB
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LSB
Carry(NC) Borrow(NC) P3 P2 P1 P0
48
K.I.T - Tiptur
Q3 Q2 Q1 Q0
>5
Vcc
Clear
11
74192
>4
Clock I/N
14
12
Load(L)
9 10 1 15
13
MSB
LSB
Carry(NC) Borrow(NC) P3 P2 P1 P0
From 8 to 3 :
Q3
0
Q2
1
Q1
0
Q0
1
1
0
Clock
Q3
1
Q2
0
Q1
0
Q0
0
Waveforms:
Preset Value = 5, N = 4, (To count from 5 to 8) Up 74192:
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49
K.I.T - Tiptur
Procedure:
1.
2.
3.
4.
5.
6.
7.
Connections are made as shown in the Logic diagram with the load pin open.
The present value is made available at the data i/ps P3, P2, P1 and P0
The load pin is made low so that the present value appears at Q3, Q2, Q1 and Q0.
The output of the gate is then connected to the load input.
Clock pulses are applied one by one and the truth table is verified.
Continuous clock pulses are applied.
Waveforms at Q3, Q2, Q1 and Q0 are observed on CRO.
fclk = ______ fQ0 = ______ fQ1 = ______ fQ2 = ______ fQ3 = ______
Programmable 4-bit Synchronous up/down binary counter.
Logic Diagram of 74193 IC:
Clock up
>5
Clock down
>4
Clear
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Q0
Q1
Q2
Q3
Carry
12
Borrow
13
74193
50
K.I.T - Tiptur
14
15
10
11
MSB
Function Table:
Load Clear Clk-up Clk-down
Mode
X
1
X
X
Reset to zero
1
0
1
Up-count
1
0
1
Down-count
0
0
X
X
Preset
1
0
1
1
Stop count
Logic Diagram for Preset value =3, N = 6,(To count from 3 to 8 ):
Q3 Q2 Q1 Q0
1
2
Clock I/N
>5
Vcc
>4
Clear
3
11
74193
14
12
Load(L)
9 10 1 15
13
MSB
LSB
Carry(NC) Borrow(NC) P3 P2 P1 P0
Logic Diagram for Preset value =12, N = 8,(To count from 12 to 5 ):
Q3 Q2 Q1 Q0
Vcc
Clock I/N
Clear
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>5
74193
>4
14
12
3
11
Load(L)
9 10 1 15
13
51
K.I.T - Tiptur
MSB
LSB
from 12 to 5
Q3
0
Q2
0
Q1
1
Q0
1
Clock
Q3
1
Q2
1
Q1
0
Q0
0
Waveforms:
Present value = 3,
Dept. of E&C
52
Up 74193 :
Down 74193 :
K.I.T - Tiptur
Procedure:
1.
2.
3.
4.
5.
6.
7.
Connections are made as shown in the Logic diagram with the load pin open.
The present value is made available at the data i/ps P3, P2, P1 and P0.
The load pin is made low so that the present value appears at Q3, Q2, Q1 and Q0.
The output of the gate is then connected to the load input.
Clock pulses are applied one by one and the truth table is verified.
Continuous clock pulses are applied.
Waveforms at Q3, Q2, Q1 and Q0 are observed on CRO.
fclk = ______ fQ0 = ______ fQ1 = ______ fQ2 = ______ fQ3 = ______
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Staff Signature
53
Remarks
K.I.T - Tiptur
Experiment No 12
Shift Register
Aim: To conduct an experiment to perform the following operations on a given 4 bit data
using IC 7495.
i. Right shift, ii. SIPO, iii. SISO, iv. PIPO, v, PISO, vi, left shift, vii, Ring Counter,
viii. Johnson Counter.
Component required:
Sl.No
01
Particulars
IC 7495, 7404
Range
------
Quantity
1 No
Dept. of E&C
14
Vcc
D3
13
Q3
D2
12
Q2
D1
11
Q1
D0
10
Q0
CLK1
GND
CLK2
IC 7495
DS
54
K.I.T - Tiptur
Logic Diagram for i) Right shift and ii) Serial In Parallel Out (SIPO):
Vcc
Ds
14
7495
Clock 1
13
12
11
6
M=0
10
7
GND
Q3
Truth Table:
Clock
1
2
3
4
Serial Data
0
1
1
1
Q3
0
1
1
1
Q2
X
0
1
1
Q2
Q1
Q1
X
X
0
1
Q0
X
X
X
0
Q0
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55
K.I.T - Tiptur
Vcc
Ds
14
7495
Clock 1
13
12
11
6
M=0
10
7
GND
Q3
Truth Table:
Clock
1
2
3
4
5
6
7
Serial
D0= 0
D1 = 1
D2 = 1
D3 = 1
X
X
X
Q0
0
1
1
1
X
X
X
Q1
X
0
1
1
1
X
X
Q2
X
X
0
1
1
1
X
Q1
Q2
Q0
Q3
X
X
X
0 = D0
1 = D1
1 = D2
1 = D3
M=1
D3
D2
D1
D0
7495
Clock 2
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13
56
12
11
14
Vcc
10
K.I.T - Tiptur
7
GND
Q3
Q2
Truth Table:
Clock
1
D3
D2
D1
D0
Dept. of E&C
Vcc
7495
8
Clock
14
13
12
11
10
Q3
Q2
Q1
Q0
57
7
GND
K.I.T - Tiptur
Truth Table:
Mode
M
1
0
0
0
Clock
1
2
3
4
Ds
X
0
1
0
D3
1
X
X
X
Clock
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6
8
9
D1
D2
D3
7495
10
11
12
13
Q3
Q2
Q1
Q0
58
K.I.T - Tiptur
Truth Table:
Clock
1
2
3
4
Q0
X
X
X
1
Q1
X
X
1
0
Q2
X
1
0
1
Q3
1
0
1
1
D0
D1
D2
D3
Clock 1
Serial I/P
7495
10
11
12
13
Q3
Q2
Q1
Q0
Q2
0
Q3
0
Truth Table:
Mode
1
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Clock
1
Q0
1
Q1
0
59
K.I.T - Tiptur
0
0
0
0
0
2
3
4
5
6
0
0
0
1
1
0
0
1
0
0
0
0
Repeated
0
0
1
0
D3
D2
D1
D0
Clock 1
Serial I/P
7495
13
12
11
10
Q3
Q2
Q1
Q0
Q2
0
0
0
1
1
1
1
0
0
Q3
0
0
0
0
1
1
1
1
0
Truth Table:
Mode
1
0
0
0
0
0
0
0
0
Clock
1
2
3
4
5
6
7
8
9
Q0
0
1
1
1
1
0
0
0
0
Q1
0
0
1
1
1
1
0
0
0
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60
K.I.T - Tiptur
Staff Signature
Remarks
Experiment No 13
Sequence Generator
Aim: Design a sequence generator
Component required:
Sl.
No
01
Particulars
Range
Quantity
------
1 No
Block Diagram:
Next State Generator
Q0
Q1
10
1
Serial I/P
Q2
Q3
12
11
13
Shift Register
9
Clock I/P
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K.I.T - Tiptur
Clock
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Q0
1
0
0
0
1
0
0
1
1
0
1
0
1
1
1
Q1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
1
Q2
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
Q3
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
D O/P
0
0
0
1
1
0
1
1
0
1
0
1
1
1
1
00
0
0
0
0
Q0 Q1
00
01
11
10
01 11 10
1 0 1
1 0 1
1 0 1
1 0 1
D = Q2 Q3 + Q2 Q3
D = Q2 Q3
Note: During the generation of the complete sequence no state should repeat.
Logic Diagram:
1
D
3
Q0
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1
Q1
10
Q262
11
12
Q0
13
K.I.T - Tiptur
Clock1
Mode M
A
Procedure:
The give Sequence: 1000 1001 1010 1111.
1. Connections are made as shown in Logic diagram 1.
2. 5V supply is switched on. The shift register will now go to any random state. If
this state is one of these valid states in the truth table then step 4 is followed.
3. The connection from the output of the logic gate to the serial input pin is
removed. The shift register is brought to any one of the valid state in the truth
table by applying the required data at serial input. The connection from the logic
gate to the serial input is then made.
4. Clock pulses are applied one by one. The required sequence is obtained at Q0,
Q1, Q2, Q3 and output of the EX-OR gate.
Result: Truth table is verified.
Date of Completion of Exp.
Dept. of E&C
Staff Signature
63
Remarks
K.I.T - Tiptur
a
f
c
d
Dept. of E&C
64
Vcc = 3
a=1
b= 13
c =10
d=8
e=7
f=2
g = 11
K.I.T - Tiptur