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LAB SHEET
PROCESSING AND FABRICATION
TECHNOLOGY
EEN3106
TRIMESTER II 2010-2011
PFT1 NMOS Processing Simulation
PFT2 PMOS Processing Simulation
*Note: On-the-spot evaluation will be carried out during or at the end of the experiments.
Questions regarding metal oxide semiconductor (MOS) device processing and
fabrication, as well as device simulation will be asked during the evaluation.
Students are advised to read through this lab sheet before doing experiment. Your
individual performance during on-the-spot evaluation, participation in the lab simulation
work, teamwork effort, and learning attitude will count towards the lab marks, in addition
to the lab report.
Please bring along your USB stick for data files saving purpose.
INTRODUCTION:
Complementary metaloxidesemiconductor (CMOS) is a major class of integrated
circuits. CMOS technology is used in chips such as microprocessors, microcontrollers,
static RAM, and other digital logic circuits. CMOS technology is also used for a wide
variety of analog circuits such as image sensors, data converters, and highly integrated
transceivers for many types of communication. CMOS is also sometimes explained as
complementary-symmetry metaloxidesemiconductor. The words "complementarysymmetry" refer to the fact that the typical digital design style with CMOS uses
complementary and symmetrical pairs of p-type and n-type MOSFETs for logic
functions. Two important characteristics of CMOS devices are high noise immunity and
low static power supply drain. Significant power is only drawn when its transistors are
switching between on and off states; consequently, CMOS devices do not produce as
much heat as other forms of logic such as TTL (transistor-transistor logic). CMOS also
allows a high density of logic functions on a chip.
In this simulation, the fundamentals of MOS chip fabrication will be discussed and the
major steps of the process flow will be examined. The emphasis will be on the general
outline of the process flow and on the interaction of various processing steps, which
ultimately determine the device and the circuit performance characteristics. This
simulation shows that there are very strong links between the fabrication process and the
device performance. Hence, the circuit designer must have a working knowledge of chip
fabrication to create effective designs and to optimize the circuits with respect to various
manufacturing parameters.
The following discussion will concentrate on the well-established CMOS fabrication
technology, which requires that both the n-channel (nMOS) and p-channel (pMOS)
transistors be built on the same chip substrate. To accommodate both nMOS and pMOS
devices, special regions must be created in which the semiconductor type is opposite to
the substrate type. These regions are called wells or tubs. A p-well is created in an n-type
substrate or, alternatively, an n- well is created in a p-type substrate. In the simple n-well
CMOS fabrication technology presented, the nMOS transistor is created in the p-type
substrate, and the pMOS transistor is created in the n-well, which is built-in into the ptype substrate. In the twin-tub CMOS technology, additional tubs of the same type as the
substrate can also be created for device optimization.
The simplified process sequence for the fabrication of CMOS integrated circuits on a ptype silicon substrate is shown in Fig. 1. The process starts with the creation of the n-well
regions for pMOS transistors, by impurity implantation into the substrate. Then, a thick
oxide is grown in the regions surrounding the nMOS and pMOS active regions. The thin
gate oxide is subsequently grown on the surface through thermal oxidation. These steps
are followed by the creation of n+ and p+ regions (source, drain and channel-stop
implants) and by final metallization (creation of metal interconnects).
Figure-1: Simplified process sequence for fabrication of the n-well CMOS integrated
circuit with a single polysilicon layer, showing only major fabrication steps.
The process flow sequence pictured in Fig.1 may at first seem to be too abstract, since
detailed fabrication steps are not shown. To obtain a better understanding of the issues
involved in the semiconductor fabrication process, we first have to consider some of the
basic steps in more detail.
Fabrication Process Flow - Basic Steps
The integrated circuit may be viewed as a set of patterned layers of doped silicon,
polysilicon, metal and insulating silicon dioxide. In general, a layer must be patterned
before the next layer of material is applied on chip. The process used to transfer a pattern
to a layer on the chip is called lithography. Since each layer has its own distinct
patterning requirements, the lithographic sequence must be repeated for every layer,
using a different mask.
To illustrate the fabrication steps involved in patterning silicon dioxide through optical
lithography, let us first examine the process flow shown in Fig. 2. The sequence starts
with the thermal oxidation of the silicon surface, by which an oxide layer of about 1
micrometer thickness, for example, is created on the substrate (Fig. 2(b)). The entire
oxide surface is then covered with a layer of photoresist, which is essentially a lightsensitive, acid-resistant organic polymer, initially insoluble in the developing solution
(Fig. 2(c)). If the photoresist material is exposed to ultraviolet (UV) light, the exposed
areas become soluble so that they are no longer resistant to etching solvents. To
selectively expose the photoresist, we have to cover some of the areas on the surface with
a mask during exposure. Thus, when the structure with the mask on top is exposed to UV
light, areas which are covered by the opaque features on the mask are shielded. In the
areas where the UV light can pass through, on the other hand, the photoresist is exposed
and becomes soluble (Fig. 2(d)).
The sequence of process steps illustrated in detail in Fig. 2 actually accomplishes a single
pattern transfer onto the silicon dioxide surface, as shown in Fig. 3. The fabrication of
semiconductor devices requires several such pattern transfers to be performed on silicon
dioxide, polysilicon, and metal. The basic patterning process used in all fabrication steps,
however, is quite similar to the one shown in Fig. 2. Also note that for accurate
generation of high-density patterns required in sub-micron devices, electron beam (Ebeam) lithography is used instead of optical lithography. In the following section, the
main processing steps involved in the fabrication of an n-channel MOS transistor on ptype silicon substrate will be examined.
exposed areas on the silicon surface, ultimately creating two n-type regions (source and
drain junctions) in the p-type substrate. The impurity doping also penetrates the
polysilicon on the surface, reducing its resistivity. Note that the polysilicon gate, which is
patterned before doping actually defines the precise location of the channel region and,
hence, the location of the source and the drain regions. Since this procedure allows very
precise positioning of the two regions relative to the gate, it is also called the self-aligned
process.
Figure-4: Process flow for the fabrication of an n-type MOSFET on p-type silicon.
Once the source and drain regions are completed, the entire surface is again covered with
an insulating layer of silicon dioxide (Fig. 4(i)). The insulating oxide layer is then
patterned in order to provide contact windows for the drain and source junctions (Fig.
4(j)). The surface is covered with evaporated aluminum which will form the interconnects
(Fig. 2.4(k)). Finally, the metal layer is patterned and etched, completing the
interconnection of the MOS transistors on the surface (Fig. 4(l)). Usually, a second (and
third) layer of metallic interconnect can also be added on top of this structure by creating
another insulating oxide layer, cutting contact (via) holes, depositing, and patterning the
metal.
The schematic cross-section of a simple CMOS inverter circuit constituted by an nchannel MOS transistor and a p-channel MOS transistor is shown in Fig. 5 below. The
CMOS integrated circuit can be accomplished by fabricating the n-channel and p-channel
MOS devices on the same substrate, following the fabrication processes discussed in Fig.
1-4.
10. In your report, sketch the Id/Vgs curves. The raw data of Id/Vgs curve can be
obtained from the tcad8s Home folder, from a file with .log extension.
11. In your report, record the extraction values from the result.final file. (eg. gate oxide
thickness, Vt)
Part B: Effects of different influent factors on NMOS structure and Ids/Vgs curve
B1. Effects of Source/Drain Concentration
1.
In ANTHENA, change S/D concentration to 5e12cm-3
2.
3.
4.
5.
#S/D implant
implant arsenic dose=5.0e15 energy=50 pearson implant
boron dose=8e12 energy=100 pears
Click on run button to start simulation.
Save the simulated structure and graph generated
Repeat step 2 and 4 with S/D concentration of 8e17 cm-3
Compare and discuss the structure, Id-VgS curve simulated
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9. In your report, sketch the Id/Vgs curves. The raw data of Id/Vgs curve can be obtained
from the tcad8s Home folder, from a file with .log extension.
10. In your report, record the extraction value from the result.final file. (eg. gate oxide
thickness, Vt)
Part B: Effects of different influent factors on PMOS structure and Ids/Vgs curve
B1: Effect of the doping concentration of phosphorus in silicon
1. Scroll down the PMOS commands until you find the lines below:
# Start off by defining silicon with 1e14 phos doping...
# Decrease the following space.mult parameter for a denser
# mesh and more accuracy...
init orientation=100 c.phos=1e14 space.mult=2
2. In the last line of the above commands, change the value of c.phos to 1e15, for
example, c.phos=1e15.
3. Simulate the newly created PMOS commands and notify the changes on both PMOS
structure and Ids/Vgs curve.
4. Repeat step 2 and 3 for different doping.
B2: Effect of the BF2 dose in PLDD implant amorphous
1. Look for the commands below:
# PLDD implant amorphous
implant amorphous bf2 dose=2.0e14 energy=50 pearson
2. Change bf2dose=2.0e14 to 2.0e16, for example bf2 dose=2.0e16
3. Simulate the newly created PMOS commands and notify the changes on both PMOS
structure and Ids/Vgs curve.
4. Repeat step 2 and 3 for different bf2 dose.
Part C: Device design and evaluation of NMOS/PMOS with different dimensions
1.
2.
3.
4.
5.
You should carry out preparation work including literature reviews and trial
simulations prior to the PFT2 lab session, so that you can deliver a more efficient
device design of the metal oxide field effect transistor (MOSFET) within the lab
session of the PFT2.
You are required to design and simulate a 0.25 m n-type or p-type metal oxide
field effect transistor (MOSFET).
You are expected to evaluate the 0.25 m n-type or p-type MOSFET performance
in terms of device characteristics such as subthreshold slope, threshold voltage and
charge carrier mobility.
Based on your evaluations, compare the device performance of the 0.25 m n-type
or p-type metal oxide field effect transistor (MOSFET) with that of a 0.50 m
MOSFET.
Discuss your comparison results.
Marking Scheme
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Lab Assessment
(10%)
Components
Hands-On & Efforts
(2%)
On
the
Spot
Evaluation (2%)
Lab Report
(6%)
Details
The hands-on capability of the students and their efforts
during the lab sessions will be assessed.
The students will be evaluated on the spot based on the
lab experiments and the observations on the device
characteristics.
Each student will have to submit his/her lab final report
within 10 days of performing the lab experiment PFT2.
The report should cover the followings:
1. Introduction, which includes background
information on monolithic integrated MOSFETs
processing and device simulation.
2. Experimental section, which includes the general
summary of the lab experiment work in PFT1
and PFT2.
3. Results and Discussions, which include the
device simulation results, analysis, and
evaluations, with neat graphs/images of the
results and recorded data, as well as the
discussion on the device design of the 0.25 and
0.50 m MOSFETs.
4. Conclusion, which includes a conclusion on the
experimental and design work.
5. List of References, which includes all the
technical references cited throughout the entire
lab report.
The report must have references taken from online
scientific journals (e.g. www.sciencedirect.com,
http://ieeexplore.ieee.org/xpl/periodicals.jsp,
http://www.aip.org/pubs/) and/or conference proceedings
(e.g. http://ieeexplore.ieee.org/xpl/conferences.jsp).
Format of references: The references to scientific
journals and text books should follow the following
standard format:
Examples:
[1] William K, Bunte E, Stiebig H, Knipp D,
Influence of low temperature thermal annealing on
the performance of microcrystalline silicon thin-film
transistors, Journal of Applied Physics, 2007, 101, p.
074503.
[2] Hodges DA, Jackson HG, Analysis and design of
digital integrated circuits, New York, McGraw-Hill
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