ABSTRACT for SUBMICRON MOS VLSI PROCESS TECHNOLOGIES

This paper presents a technical perspective for submicron CMOS VLSI process
technology, emphasizing higher packing density and reliability. For megabit level dRAMs,
very small cell size below 20 pm2 with soft-error immunity has been successfully obtained
by adopting doped face trench capacitor technology as well as error checking and correcting
circuit. For logic LSIs, 0.1 pm thick high quality Si isolated layer onSi02 by FIPOS
technology, new surface planarization technology using ECR plasma deposition method for
trench isolation, gate electrode and multi-level interconnections have been developed.

INTRODUCTION
The major subjects required for the submicron MOS VLSI process are higher packing
density and higher reliability as well as lower power dissipation, and are interrelated.
Submicron channel MOS FETs should be operated below 3 V of supply voltage because of
insufficient tolerance for hot carrier injection (1). As well known, the CMOS circuit is
suitable to highly integrated VLSIs because of the largest circuit margin or ability operating
at lowest supply voltage as well as low power. In addition, the smallest device size in various
circuit forms is obtained by CMOS in an ideal case ( 2 ) . From these reasons, a CMOS
circuit operating below 3 V should be chosen for not only logic LSIs but also memory LSIs
using submicron device and process.
In this report, technologies based upon the above strategy, i.e., doped face trench
capacitor and reliable Mo gate technologies for megabit level CMOS dRAMs, and FIPOS
technology with very thin, high quality Si layer and new surface planarization technology
using ECR plasma deposition for trench isolation, gate electrode and multi-level
interconnections for several tens kilogate logic CMOS LSIs are presented. DOPED FACE
TRENCH CAPACITOR AND RELIABLE Mo GATE TECHNOLOGIES FOR MEGABIT
LEVEL DRAMS The cell size of dRAMs has been reduced to
about 1/3 for 4 times integration from 1 K to 256 K, as shown in Fig. 1. If this tendency is
maintained to megabit dRAMs, cell size should be reduced to 20-30 pm2 for 1 M and about
10 pm2 for 4 M. This situation is completely different from the 256 K era, where the guiding
principles of the 256 K development have been only pattern size reduction, word line delay
time reduction, and yield elevation by fault-tolerant technology ( 2 ) . When such small cell
size as below 30 pm2 is adopted for megabit dRAM, storage capacitor area becomes too
small, causing not only alpha-particle immunity degradation but also signal level at sense
amplifiers which is too small.
To overcome this problem, two methods in both process and circuit have been
approached; One is doped face trench capacitor (DFTC) as one of a three dimensional
structure (1,3,4,5) and the other is the on chip Error Checking and
-Co rrecting (ECC) circuit (6). The cell capacitor area and cell capacitance with 15 nm Si02
vs. cell area as a parameter of trench depth are shown in Fig.2. Here, the critical cell
capacitance to satisfy alpha-particle immunity is about 80 fF for 3 V and 50 fF for 5 V, if
circuit approach such as an ECC circuit is not employed to obtain immunity. On the other
hand, if the ECC circuit is adopted, the critical capacitance is determined by the sense
amplifier sensitivity (typically about 50 mV ) and a ratio of bit line to cell capacitances
(typically 1O:l) and the critical capacitance becomes about 20fF. From Fig. 2, it is found that
a cell capacitor with only 20 fF cannot be obtained for a 20 p 2 cell area and 15 nm Si02
unless trench capacitor or Si02 thinner than 10 nm, or higher dielectric materials are used.
Comparing reliability, process simplicity and its expansion to other processes such as
device isolation among these candidates, we have chosen trench capacitor technology for 1
Mb dRAM, where cell size, capacitance and trench depth/width are 20 pm2, 30 fF and 1.5
pm/0.5 pm, respectively, assuming 3 V operation and ECC circuit. The DFTC is
characterized by a trench surface doped with phosphorus, enabling cell plate grounding and
resulting in high breakdown immunity for very thin capacitor gate oxide. The SEM
photograph of DFTC cross section is shown in Fig.3. The capacitance, 30 fF is 3 times larger
than that by plane capacitor and the breakdown voltage is above 8 V, which is enough to 3 V
operation. Further, the capacitance will become more larger, using higher dielectric materials
or deeper trench, if necessary.Next, Mo gate process reliability for word line in dRAM is
discussed with respect to interface state density generation due to Mo atom penetration into
Si-Si02 interface during Mo deposition ( 7 ) . The penetration depth increases with increasing
substrate temperature during M deposition using EB evaporation or sputtering, and severer

problems arise with a gate oxide thickness decrease. From the attentive experiment, it was
found that the penetration occurs at just the initial stage of deposition, although a penetration
mechanism is not clear at present. To depress the penetration, the two step deposition method
has been developed, in which a very thin Mo layer below several nm is first deposited at
room temperature followed by deposition at a higher temperature. Using the method,
penetration depth has been reduced to below 3 nm and interface state density has been
lowered to the order ofl olo cm-2eV-1 even for 10 nm gate oxide, as shown in Fig. 4 , and, at
the same time, Mo interconnections step coverage has been improved due to second stage
high temperature deposition.
DEVICE ISOLATION AND SURFACE
PLANARIZATION TECHNOLOGIES
Packing density of CMOS logic LSIs depends
on
device isolation width and
multi-level interconnection's pitch and level number.For device isolation, we are developing
two
methods, one
is FIPOS as an effective SO1
structure and the other is trench
isolation using
lift-off technique due to ECR plasma deposition
method.The SO1 structure is the most desirable
because of latch-up free, which causes a great
advantage for isolation width reduction. For 16K
sKAM fabricated by FIPOS/CMOS with 2 p m rule and
0.5 pm Si layer thickness, chip size was reduced
to 80 % of that designed for bulk CMOS with the
same rule, i.e., isolation width could be reduced
to 3 pm for FIPOS/CMOS, compared to 10 p m for bulk CMOS.To advance the FIPOS to
submicron
process, 0.05-0.4 pm thick isolated Si layer
characteristics have been examined by the field
effect mobility and
drain leakage current
of
fabricated MOS FETs.Layer thickness can be
easily controlled by proton implantation energy
for n-type layer
formation before anodization.Yield
degradation caused by
leakage current was not
found for above 0.1 ym thickness. These results
show that crystalline quality of the isolated Si
layer above 0.1 pm is excellent as the substrate
for submicron CMOS LSI.Next,
surface planarization technology
using lift-off and ECR plasma deposition for full
levels involving trench isolation, gate electrode

and
multi-level
interconnections step is
presented.Surface planarization
is
inevitable to obtain higher packing density
in
future
LSIs.
Developed technology
for
full
levels planarization is named full
leveled
accumulation technology (FLAT). The ECR plasma
deposition method has such excellent features as
high directionality and high quality even at room
temperature deposition (12).
Fig. 6 shows the processing steps for trench
isolation of bulk CMOS, where Mo film usage as a
stencil for lift-off provides contamination free
process
for
succeeding
high
temperature
treatments, compared with conventional lift-off
process
using
photoresist as
a
stencil.
Interface state density of the trench surface
refilled by ECR plasma deposited Si02 is improved
by
O2
plasma
treatment
before
the
Si02
deposition. It becomes about 10l1 crn-'eV-'
after
total processing steps as shown in Fig. 7, which
is nearly equal to that of thermally grown Si02
interface.
Gate
multi-level
electrode

and
interconnections steps are also planarized by
FLAT. The cross-sectional view of full leveled
accumation chip is shown in Fig.8, where the step
height is within 0.2 pm in each level. Using this
A1
technology,
2 more
or
multi-leveled
interconnections with the same rule of 1.3 p m L&S
in all levels have been developed. This
planarized technology is expected to
be effective
to not only higher packing density but also
higher immunity to electromigration.