Disconnect detector for USB bus: When a disconnect occurs a pulse of 20 ns duration and 625

mv amplitude occurs on the D+ D- lines . The aim of the circuitry is to detect this pulse and trigger a D flipflop. Also it is required to reject pulses of amplitude less than or equal to 525 mv.
Techonlogy: For the amplificartion of the pulse National Semiconductor wide band op amp LMH
6715 is chosen with a gain bandwidth product of 480 Mhz and a slew rate of 1300 V per micro
second. A D flipflop of STTL is to be used since STTL allows a minimum pulse width of 6 ns.
Circuit diagram:
1K

D+

+
D-

1K

1K

3.3K
_

1K
+

1K
0.7K

3.3K

2K

1K
1K

_
+
+

Vdd

0.7K

5.25Z

0.7K

Vcc

1K
_
+
0.7K

2K

1K
D
Q
Disconnect
Detect

Circuit description :The circuit diagram consists of 5 stages of analog circuitry.The first stage
converts from differrential to single ended mode and has unity gain.The output of the first stage is
a 625 mv pulse of 20 ns duration.The second and third stages are inverting type and together gives
a gain of 10.The resistor connected to the + input minimises the effect of offset current.The output
of the third stage is 6.25 V pulse and a maximum rise and fall times of 5 ns are expected. The
fourth stage rejects input pulses of amplitude less than or equal to 525 mv by comparing with the
output of 5.25 V zener.When the input is zero +ve voltage output of 10.5 V is possible which is
limited to 0.7 V by means of the clamping diode at the output.Both the 4th and the fifth stages
provide a total gain of 4 so that for the input of 625 mv an output of 4V is achieved , positive
pulses upto 525 mv are rejected and the -ve voltage swing for the 0 input voltage is clamped by
the diode at the output of the 5th stage.At the output of the 5th stage a pulse of 20 ns duration rise
and falltimes of 5 ns is expected.This is sufficient to trigger a STTL D flipflop 74S74.
Fabrication : The circuit utilises 3 chips of LMH 6715 since each chip contains 2 op amps It is

found that the pusle response of the above IC is satisfactory from the diagram shown.The circuit
has to be fabricated and tested.It is hoped that the high input impedence op amp will not load the
transmission lines.The dual op amp is availavle in SOIC package so that the entire circuit can be
fabrcated in a small PCB. For PCB fabrication Ms Chellappa Graphics in Mambalam Chennai
who has got experience in designing PCBs for TV can be contacted.After the initial fabrication
and testing the circuit can be modified in case of any errors. Since the PCB fabrication cost is proportinal to the area the fabrication of the circuit may not be costly. The circuit operates with Vcc
supply of 5V and + or - Vdd supply of + or - 12V.The diagram below shows the IC pins.