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Victorian Rail Industry Operators Group Standards

VRIOGS 012.7.35
CSEE (UM71)
Jointless Track Circuit Application Manual
Revision:

Revision A

Issue Date:

2/8/2011

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i
VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual
Revision A
Issue Date: 2/8/2011
APPROVAL STATUS
APPROVER

STATUS

DATE

QUALIFICATIONS

Document Developer
VRIOG Steering
Committee

Accredited Rail Operator


Metropolitan Train
(Metro Trains
Melbourne)

Intrastate Train
(V/Line)

Interstate Train
(ARTC)

Tram
(Yarra Trams)

For any queries please contact vriogs@transport.vic.gov.au.

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

PURPOSE OF THE STANDARD


The Standard has been created through the collaboration of members of the
Victorian Rail Industry Operators Group (VRIOG) for the purpose of establishing
standards which, if implemented throughout the Victorian Rail Network, will facilitate
the interoperability of infrastructure.
The use of the Standard is not prescribed by law but, if adopted, conformity with the
provisions of the Standard is mandatory in order that the purpose of the Standard be
achieved.

DISCLAIMER
The Standard is published by the Director of Public Transport for information
purposes only and does not amount to any kind of advice.
Each person is responsible for making his or her own assessment of all such
information and for verifying such information. The content of this publication is not a
substitute for professional advice.
The Director of Public Transport and VRIOG accept no liability for any loss or
damage to any person, howsoever caused, for information contained in this
publication, or any purported reliance thereon.

COPYRIGHT STATEMENT
Director of Public Transport 2011.
This publication is copyright. No part may be reproduced by any process except in
accordance with the provisions of the Copyright Act.
Where information or material is so used, it should be used accurately and the
Standard should be acknowledged as the source of the information.

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

iii

TABLE OF CONTENTS
SECTION 1.0
Conventions......................................................................................1
SECTION 2.0
Definitions .........................................................................................2
SECTION 3.0
Scope ...............................................................................................4
3.1
Scope ...........................................................................................................4
3.2
Application....................................................................................................4
3.3
History ..........................................................................................................4
SECTION 4.0
Background.......................................................................................5
4.1
General.........................................................................................................5
4.2
Track Circuit Operation and Components ....................................................5
4.2.1
Principle of Operation ...........................................................................5
4.2.2
Transmitter (TX) ...................................................................................5
4.2.3
Receiver (RX) .......................................................................................6
4.2.4
Electrical Separation Joints (ESJs) ......................................................7
4.2.4.1
Air Core Inductors (ACIs)..................................................................9
4.2.4.2
Tuning Units (TUs)............................................................................9
4.2.4.3
Matching Units (MUs) .....................................................................10
4.2.4.4
Dual Matching Units........................................................................11
4.2.4.5
Tuning Matching Units (TMUs) .......................................................11
4.2.5
Track compensation capacitors..........................................................11
4.3
Intermediate Data Collectors (IDCs)...........................................................12
4.3.1
Pin Point Detectors (PPDs) ................................................................12
4.3.2
Data Collectors (DCRs) ......................................................................13
4.4
Track Circuit Specifications ........................................................................14
4.4.1
Drop shunt ..........................................................................................14
4.4.2
Traction return ....................................................................................14
4.4.3
Storage conditions..............................................................................14
SECTION 5.0
Design ............................................................................................15
5.1
Signal Arrangement Level Design ..............................................................15
5.1.1
General...............................................................................................15
5.1.2
Physical arrangement: End-fed track circuit .......................................15
5.1.3
Physical arrangement: Centre-fed track circuit...................................15
5.1.4
Physical arrangement: Track circuit over points .................................17
5.1.5
Track circuit separation and frequency selection ...............................18
5.1.5.1
Separation with ESJ .......................................................................18
5.1.5.2
Separation with IRJ.........................................................................19
5.1.5.3
ESJ leading into non-track circuited area .......................................19
5.1.5.4
ESJ co-located with TPWS unit ......................................................19
5.1.6
Track compensation ...........................................................................19
5.1.7
Traction requirements.........................................................................21
5.1.8
Use of Intermediate Data Collectors...................................................21
5.2
Detailed Level Design ................................................................................22
5.2.1
Cable and wire requirements..............................................................22
5.2.1.1
Extended length cabling from location to trackside ........................22
5.2.2
Cable frequency allocation .................................................................22
5.2.3
Track circuit adjustments....................................................................22
5.2.4
Universal adjustment ..........................................................................23
5.2.5
ESJ requirements ...............................................................................24
5.2.6
TU requirements.................................................................................24
5.2.7
ACI requirements................................................................................24
5.2.8
MU requirements ................................................................................24
5.2.9
PPD requirements ..............................................................................24
5.2.10
Delayed energisation..........................................................................25
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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

iv

Ventilation...........................................................................................25
5.2.11
5.2.12
Lightning protection ............................................................................26
SECTION 6.0
Installation.......................................................................................27
6.1
All cabling ...................................................................................................27
6.2
Trackside units ...........................................................................................27
6.2.1
Matching Unit (Single) ........................................................................27
6.2.2
Air Core Inductor ................................................................................27
6.3
On-track and cabling from track to trackside ..............................................27
6.3.1
ESJ arrangement................................................................................28
6.3.2
ACI track connection ..........................................................................28
6.3.3
TU track connection............................................................................28
6.3.4
Configuration: PPD.............................................................................28
6.3.5
Configuration: DCR ............................................................................28
6.3.6
Configuration: ESJ..............................................................................29
6.3.7
Configuration: Centre-fed TX..............................................................29
6.3.8
Configuration: IRJ...............................................................................29
6.4
Location equipment and cabling from location to trackside........................30
6.4.1
Equipment coding...............................................................................30
6.4.2
Ventilation...........................................................................................31
SECTION 7.0
Testing and Commissioning ...........................................................32
7.1
General.......................................................................................................32
7.2
Track circuit setup ......................................................................................32
7.3
IDC setup ...................................................................................................32
7.3.1
PPD setup ..........................................................................................32
7.3.2
DCR setup ..........................................................................................33
7.4
Checking ....................................................................................................33
7.4.1
Checking TX ....................................................................................33
7.4.2
Checking RX....................................................................................33
7.4.3
Checking PPD .................................................................................33
7.4.4
Checking DCR.................................................................................34
7.4.5
Specific adjustment ............................................................................35
SECTION 8.0
Appendix A .....................................................................................36
SECTION 9.0
Appendix B .....................................................................................61
9.1
Transmitter Adjustment Table KEM .........................................................61
9.2
Receiver Adjustment Tables KRV............................................................62
9.3
Electrical Separation Joint ESJ ...............................................................63
9.4
Insulated Rail Joint IRJ............................................................................67
9.5
Centre-fed Transmission ............................................................................71
9.6
Data Collector.............................................................................................73
9.7
Pin Point Detector ......................................................................................75
9.8
Transmitter Presentation and Coding.........................................................78
9.9
Receiver Presentation and Coding.............................................................83
9.10 Trackside Components ..............................................................................88
9.11 CSEE Trackside Box Support Post ............................................................92
SECTION 10.0
Specification for extended length TX/RX to MU cables ..............93
SECTION 11.0
Referenced Documents ..............................................................94

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual


SECTION 1.0
1)
2)
3)
4)
5)

6)
7)

Conventions

Words or phrases that appear capitalised out of context are defined within the
Definitions section of this VRIOG Standard.
The word Shall is to be understood as mandatory.
The word Should is to be understood as non-mandatory i.e. advisory or
recommended.
Uncontrolled Standards may not be referenced within the VRIOG Standards.
These include former PTC Standards, Franchisee Standards, Franchisee
Subcontractor Standards and Infrastructure Lessee Standards.
Controlled Standards, including Australian Standards and other VRIOG
Standards, may be referenced but only if:
The referenced item can not be adequately explained with an amount of
text that could not reasonably be inserted into the body of the Standard.
The reader is not referenced to another Controlled Standard necessary
for the item to be adequately explained i.e. one document link only.
The referenced document is a Figure or table and could not reasonably
be included in the appendices of the Standard.
The numbering system for the VRIOG Standards is chronologically sequential
from the point of introduction, and is not based on any form of interpretive
system.
VRIOG Standards will not contain any information that can be construed as a
work instruction, procedure, process or protocol. This information forms the
basis of each individual entitys Safety Accreditation Certification, and, as
such, is outside the scope of VRIOG Standards.

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual


SECTION 2.0

Definitions

Terminology used and/or applied in this Standard is defined as follows:


Term

ACI

Description
An Accredited Rail Operator is a Rail Infrastructure Manager
or a Rolling Stock Operator who is accredited under Part 5
of the Rail Safety Act 2006.
Air Core Inductor or Self Inductor

DCR

Data Collector

ESJ

Electrical Separation Joint

HP

High Power (Transmitter setting for maximum power output)

IDC

Intermediate Data Collector. This is the collective term used

Accredited Rail
Operator (ARO)

for both PPDs and DCRs.


IRJ

Insulated Rail Joint

IT

Intermediate Transmission. This arrangement is more


commonly known as a centre-fed track circuit.

KEM

Output turns ratio of transmitter output transformer

KMU

The turns ratio of the transformer in the matching unit

KRV

Input turns ratio of receiver input transformer

LP

Low Power (Transmitter setting for maximum power output)

MU

Matching Unit

PPD

Pin Point Detector

R1-R2

RX

The R1-R2 terminals on the receiver unit. The voltage across


these terminals is what is presented to the receivers
electronics, and is equal to the output voltage of the
receivers input transformer, if used.
Receiver Unit

RXMF

Alternate name for RXMU

RXMU

MU associated with a RX

RXTU

TU associated with a RX

SI

Air Core Inductor or Self Inductor

TU

Tuning Unit

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual


TMU

Combined Tuning and Matching Unit

TX

Transmitter Unit

TXMF

Alternate name for TXMU

TXMU

MU associated with a TX

TXTU

TU associated with a TX

V1-V2

The V1-V2 terminals on the receiver unit. The voltage across


these terminals is the input voltage to the receivers internal
multi-tapped input transformer.
The Victorian Rail Industry Operators Group comprising the
following members:
VicTrack
V/Line
Metro Trains Melbourne
Yarra Trams
Australian Rail Track Corporation (ARTC)
Public Transport Division of the Department of Transport
(PTD)

VRIOG

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual


SECTION 3.0
3.1

SCOPE

Scope

This manual sets out the application requirements of the CSEE UM71 jointless track
circuit within the Victorian broad gauge network.
3.2

Application

This manual is to be used for new installations and modifications of existing UM71
track circuits. References to track circuit refer to the CSEE UM71 jointless track
circuit, unless otherwise specified.
3.3

History

This manual combines the resources and information of the various documents as
well as unwritten industry knowledge relating to the use and installation of the UM71
track circuit within the Victorian railway industry.

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual


SECTION 4.0
4.1

BACKGROUND

General

The UM71 track circuit is a jointless track circuit suitable for vital train detection.
4.2
4.2.1

Track Circuit Operation and Components


Principle of Operation

The underlying working principle of jointless track circuits remains unchanged from
jointed track circuits. A power source energises receiver(s) through the track circuit
section; if any of the receiver(s) detects a loss of that power, the section is assumed
to be occupied and reported as such.
The primary difference is that jointless track circuits avoid the mechanical cutting of
the rails, the traditional insulated rail joints being replaced by tuned circuit elements.
Collectively, these tuned circuit elements are referred to as Electrical Separation
Joints (ESJs).
A number of components work in concert to provide the train detection capability.
The overall scheme of how the components work together is detailed below:
1) The transmitter outputs an electrical signal that is injected into the rails.
2) Nearby receiver(s) complete the circuit.
a. In the absence of a low resistance shunt 1 , the receiver(s) detect
sufficient transmitted power and indicate the track circuit section as
vacant.
b. In the presence of a low resistance shunt, the receiver(s) is unable to
detect sufficient transmitted power and indicate the track section as
occupied.
3) Adjacent track circuit sections are functionally isolated from each other, either
by the use of ESJs or insulated rail joints (IRJs).
The individual components are detailed in the following sections.
4.2.2

Transmitter (TX)

The transmitter generates a power-limited sinusoidal signal at one of four carrier


frequencies: 1700Hz, 2000Hz, 2300Hz or 2600Hz. The four transmitter variants are
also known as V1F1, V2F1, V1F2 and V2F2 respectively (see 4.2.4 for more
information on the naming scheme).
The transmitter is connected to the trackside interface (either a Matching Unit or a
combined Tuning Matching Unit) via a cable.
To provide additional protection against interference 2 , Binary Frequency Shift Keying
(BFSK) modulation is applied to the carrier frequency.
The BFSK scheme use frequencies at +/- 11 Hz of the carrier, and is modulated at a
rate of 1/128 of the carrier frequency.

1
2

E.g. train axles.


E.g. spurious voltages induced by 50 Hz currents.
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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

The output signal from the transmitter can be adjusted by three different
mechanisms.
Coarse power adjustment via the maximum power output jumpers. These are
also known as the HP/LP jumpers.
Fine voltage adjustment via jumpers at the multi-tapped output transformer.
The transformer ratio (as determined by the jumpers) is referred to as the
KEM value.
Normal operation requires that the BFSK modulation function is enabled (via
a jumper).

Figure 1 Block Diagram of TX

Functions
Transmit output level, KEM and
interface to trackside unit
Maximum power output
Turn BFSK modulation on/off
24 V power supply

Terminals
V1, V2, V3, V4, V5, V6, V7, V8
M2, M4, M5
M1, M3
A+, A-

Table 1 TX connections

4.2.3

Receiver (RX)

The receiver is used to detect the absence of a low resistance shunt in the
associated track circuit section. The receiver must recognise the corresponding
transmitted signals carrier frequency, BFSK modulation and detect sufficient signal
strength before energising the track relay (vacant status). Any other scenario will
result in the receiver de-energising the track relay (occupied status).
The receiver is connected to the trackside interface (either a Matching Unit or a
combined Tuning Matching Unit) via a cable.
The input signal, once inside the receiver can be adjusted via jumpers at the multitapped input transformer. The transformer ratio (as determined by the jumpers) is
referred to as the KRV value.
The receiver uses an adjustable pick up time delay to prevent untimely pick-up of the
track relay in the event of a short duration shunting loss (also known as Loss of
shunt timer).
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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

Figure 2 Block Diagram of RX

Functions
Interface to trackside unit
Receiver input level, KRV
Delayed energisation
Track relay output
24 V power supply

Terminals
V1, V2
R1, R2, R3, R4, R5, R6, R7, R8, R9, R10
C, C1, C2
L+, LA+, ATable 2 RX connections

4.2.4

Electrical Separation Joints (ESJs)

An ESJ ensures reliable separation of frequencies on all track circuits common to the
same ESJ. It is also the point at which the track circuit transmitters and receivers
inject/receive power into/from the track.
An ESJ is formed from two Tuning Units 3 connected to the track, with an Air Core
Inductor connected to the track midway. These trackside components in conjunction
with the tracks distributed elements form a semi-distributed filtering network.
Electrical drawings of these trackside components are available in section 9.10.
The ESJ scheme 4 divides the four carrier frequencies into two pairs (V1 and V2),
each pair having frequencies F1 and F2:
Pair V1: 1700 Hz (F1) and 2300 Hz (F2)
Pair V2: 2000 Hz (F1) and 2600 Hz (F2)
I.e. V1F1 is 1700 Hz; it is the F1 frequency of the V1 pair.
An ESJ will be capable of separating a track circuit operating at F1 from an adjacent
track circuit operating at F2, given that they are both from the same frequency pair.
3

Where combined Tuning Matching Units are used, this refers to the Tuning Unit portion of
the complete assembly.
4
For use with CSEE track circuits. The Tuning Units and Air Core Inductor are designed to
support the given scheme. Other jointless track circuit systems will likely have different ESJ
schemes and supporting components.
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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

ESJs are not designed to separate adjacent track circuits operating on different
frequency pairs.
More details on the TUs are available in the corresponding section, but the basic
functionality of the ESJ can be described in an example scenario, in the absence of
any shunts:
To transmitter via
Matching Unit

To receiver via
Matching Unit

TU V2F1

ACI

TU V2F2

2000 Hz

2600 Hz
ESJ
Figure 3 ESJ basic layout

The 2000 Hz track circuit on the left hand side is fed by a TX through the V2F1 TU,
while the 2600 Hz track circuit on the right hand side has a RX connected through
the V2F2 TU.
Consider the behaviour of the V2F1 TU:
V2F1 allows the 2000 Hz signal to pass onto the 2000 Hz track circuit
section.
V2F1 allows the 2000 Hz signal to pass into the ESJ region.
o It will not block the 2000 Hz from further propagation; thats a
function for the V2F2.
V2F1 blocks the 2600 Hz signal from entering the 2000 Hz transmitter.
V2F1 blocks the 2600 Hz signal from further propagating into the 2000 Hz
track circuit section.
o This is the crucial function of the ESJ to functionally isolate two
adjacent track circuits.
Consider the behaviour of the V2F2 TU:
V2F2 allows 2600 Hz signal to pass into the 2600 Hz receiver.
V2F2 allows 2600 Hz signal to pass into the ESJ region.
o It will not block the 2600 Hz from further propagation; thats a
function for the V2F1.
V2F2 blocks the 2000 Hz signal from entering the 2600 Hz receiver and
from further propagating into the 2600 Hz track circuit section.
o This is the crucial function of the ESJ to functionally isolate two
adjacent track circuits.
The above pass and block behaviours are simplifications of the actual circuit
behaviour; a complete steady-state analysis is needed for a full description. Roughly
speaking:
The pass behaviour mimics the circuit behaviour where the joint TU-rail
network exhibits relatively high impedance looking in from the Matching Unit
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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

side. This ultimately allows enough signal strength (from the correct
transmitter) to arrive at the receiver for a vacant status.
The block behaviour mimics the circuit behaviour where the TU presents
with very low impedance. For instance, the V2F2 TU will reactively 5 shunt the
2000 Hz signal; but not the 2600 Hz signal. This frequency selective shunting
is the underlying basis for ESJs.
The real circuit behaviour is such that containment by the reactive shunts is
not absolute, but the signal leakage across the ESJ is far below the strength
detection threshold (if designed, operated and maintained to specifications).

4.2.4.1 Air Core Inductors (ACIs)


An Air Core Inductor is installed at the midpoint of an ESJ, and serves two functions.
It forms a part of the ESJ as a lumped component (increasing the filters Q factor),
and it also balances the track current between rails on which it is installed. The ACI
is not shielded and is sensitive to nearby metallic objects.
The same ACI is used for all frequencies.
ACIs are not designed for balancing traction currents between adjacent lines. They
serve a function of balancing traction currents between rails of a single track circuit
only.
Functions
Interface to track
Interface to both track and TU in
specific instances

Terminals
V1, V2

Table 3 ACI connections

4.2.4.2 Tuning Units (TUs)


Tuning Units contain passive lumped components that form part of ESJs, and are
connected to a TX or RX unit through a Matching Unit.
In ESJ configurations, the TUs are designed for continuous operation where there is
either:
TX and RX connected on opposing sides of an ESJ.
RX and RX connected on opposing sides of an ESJ.
Where two TX are connected on opposing sides of an ESJ, maximum permissible
power dissipation places limitations on the maximum track lengths. Consequently,
the TX and TX configuration at an ESJ is not preferred and should be only
considered as a last resort.
There are four different TU variants, each corresponding to a specific frequency in a
frequency pair:
V1F1
o For use with the V1 frequency pair (1700 Hz and 2300 Hz)

The shunt is reactive in the sense that the TU only contains reactive components. Unlike
resistive shunts (eg train axles and test shunts), reactive shunts are frequency sensitive. TUs
are designed for a frequency response that is compatible with the overall ESJ scheme.
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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual


o

10

Associated with frequency F1 (1700 Hz); connect to 1700 Hz TX or


RX unit
Will reactively shunt a 2300 Hz signal

o
V1F2
o For use with the V1 frequency pair (1700 Hz and 2300 Hz)
o Associated with frequency F2 (2300 Hz); connect to 2300 Hz TX or
RX unit
o Will reactively shunt a 1700 Hz signal
V2F1
o For use with the V2 frequency pair (2000 Hz and 2600 Hz)
o Associated with frequency F1 (2000 Hz); connect to 2000 Hz TX or
RX unit Will reactively shunt a 2600 Hz signal
V2F2
o For use with the V2 frequency pair (2000 Hz and 2600 Hz)
o Associated with frequency F2 (2600 Hz); connect to 2600 Hz TX or
RX unit
o Will reactively shunt a 2000 Hz signal

Each TU consists of an inductor and capacitor(s).


At the frequency associated with the TU (eg 2300 Hz for a V1F2 TU), it is
sufficiently far away from the resonance point to have relatively high
impedance.
o Associated with the pass behaviour described in the ESJ section.
At the TUs shunting frequency (eg 1700 Hz for a V1F2 TU), it is at or near
resonance, with very small impedance.
o Associated with the block behaviour described in the ESJ section.

Figure 4 TU diagrams

Functions
Interface to track
Interface to MU

Terminals
V1, V2
1, 4
Table 4 TU connections

4.2.4.3 Matching Units (MUs)


A Matching Unit is installed between the TU and either a TX or RX. In specific cases,
the TU is bypassed and the MU connects directly to the rail.
The MU has a number of pre-determined configurations. The transformer ratio, or
KMU is typically fixed by the configuration choice.
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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

11

In the TX configuration, MUs are 10:1 transformers; it also has the series inductor to
limit the current flow while the transmitter is being shunted.
In the RX configuration, MUs are 1:1 transformers.
In one of the PPD configurations, MUs are transformers; in the other PPD
configuration, the MU is substituted with a variable resistor.
In the DCR configuration, MUs are 1:1 transformers with the series resistor added.
Functions
Interface to TU
Interface to track in specific
instances
Interface to TX
MU transformer ratio, KMU and
interface to RX
Series resistor bypass
Series inductor

Terminals
V1, V2
E1, E2
5, 6, 7, 8, 9, 10, 11, 12, 13, 14
R1, R2
L3, L4

Table 5 MU connections

4.2.4.4 Dual Matching Units


A Dual Matching Unit is the combination of two Matching Units within one trackside
case.
4.2.4.5 Tuning Matching Units (TMUs)
A Tuning Matching Unit is the combination of a Tuning Unit and Matching Unit within
one trackside case.
Typical installations with a separate TU and MU will have a back-to-back
arrangement. TMUs allow the use of a single case instead; the form factor change
means that the connection arrangements are slightly different to the scenario with
separate units.
Note that TMUs do not have a built in resistor for the DCR configuration.
Functions
Interface to track
Internal interface to TU from MU
Internal interface to MU from TU
Interface to TX
MU transformer ratio, KMU and
interface to RX

Terminals
Exterior metallic tabs
V1, V2 in upper terminal row
1,4 in upper terminal row
E1, E2
5, 6, 7, 8, 9, 10, 11, 12

Table 6 TMU connections

Note that internal jumpers between V1 to 1 and V2 to 4 are prefit at factory.


4.2.5

Track compensation capacitors

In order to extend the maximum of length of a track circuit, track compensation


capacitors can be used. Track compensation is only used if there is a need for it.
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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

12

The working principle behind track compensation is the reduction of the tracks
characteristic impedance.
Without track compensation, the characteristic impedance of the physical track tends
to be very inductive and relatively high in magnitude. The transmitters impedance
and the track impedance determine the amount of power that can be injected into the
track 6 .
With track compensation, shunt capacitors are inserted into the track circuit section
at predetermined regular intervals, reducing the tracks characteristic impedance.
This lower characteristic impedance results in better impedance matching between
the track and the transmitter; more power is now injected into the track, allowing for a
longer track circuit.
4.3

Intermediate Data Collectors (IDCs)

Intermediate Data Collectors (IDCs) are auxiliary receivers, which can be installed
within the parent track circuits limits. They provide the ability to split the parent
track circuit into two sub-track circuits without the full cost of installing two separate
track circuits. This approach is not always technically appropriate and the limits of
IDCs need to be kept in mind.
An IDC creates two sub-track circuit sections; one covers the RX IDC section, and
the other the TX IDC section. When only the RX IDC section is occupied, only
the RX IDC section is reported as occupied. However when the TX IDC section
is occupied, both the RX IDC and TX IDC sections are reported as occupied.
There are two types of IDCs, one operating in voltage mode and one in current
mode.
IDCs are not compatible with track compensation. The electrical behaviour of a
compensated track being shunted is different to the electrical behaviour of a
non-compensated track being shunted. This is not an issue with the parent track
circuit, since the receiver does not see this change in electrical behaviour. However,
IDCs, being in the middle of the track circuit, will see the full extent of this behaviour;
IDCs are not designed to operate under these conditions and may contribute to a
failure in such a scenario.
4.3.1

Pin Point Detectors (PPDs)

A Pin Point Detector is a current-mode IDC. It works in conjunction with a MU or an


adjustable resistor; there is no associated TU. Use of a MU gives better noise
immunity, whereas the use of an adjustable resistor gives more flexibility in the
design / installation.
The demarcation point between the two sub-track circuit sections is sharp and
located at the PPD. PPDs can be used to provide overlaps and release of level
crossings.
The PPD operates by monitoring the current through a rail. The PPD unit is a
contact-free inductive device tuned to one of the track circuit carrier frequencies.
While the TX PPD sub-track circuit section is not being shunted, current is flowing
6

In other words, the transmitter and the track are not impedance matched by design.
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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

13

through the rails (either through the RX or through a shunt on the RX PPD subtrack circuit section), resulting in the PPD providing an output above the detection
threshold. The moment the TX PPD sub-track circuit is shunted, current is diverted
through the shunt and current through the PPD is reduced to near zero, resulting in
the PPD providing an output below the detection threshold.
PPDs are available in four variants, each corresponding to a track circuit carrier
frequency. They connect to a standard RX unit through the MU / resistor.
The output of the PPD is voltage-mode, and is proportional to the tuned current being
sensed in the rail. Consequently, there is a minimum requirement on the track circuit
current for the PPD to function properly.
A boosting unit located near the PPD can be used to increase the track circuit current
to meet the minimum current requirement. It is a passive unit composed of a
shunting resistor, isolated from the DC track current through blocking capacitors.
There is a choice of boosting unit values to accommodate requirements.
If a track shunt is applied or a train occupies the track section between the PPD and
the RX, operation of the PPD may be unreliable. For this reason the design should
ensure that the parent track is not occupied while train detection in only the TX
PPD section is required.

Figure 5 PPD operation

4.3.2

Data Collectors (DCRs)

A Data Collector is a voltage-mode IDC. It works in conjunction with a MU; there is


no associated TU. The MU has the series resistor in circuit to increase the input
impedance of the DCR, reducing the load it presents to the parent track circuit.
The demarcation point between the two sub-track circuit sections is not precisely
defined, as it varies with ballast resistance. It can vary from 35m to 80m from the
DCR location, in the direction of the parent RX.
The DCR operates by monitoring the voltage across the rails. If the voltage is above
a threshold, then the DCR can assume that the sub-track circuit section between the
DCR and the transmitter has not been shunted, and report it as vacant.

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

14

If the voltage is below a threshold, then something is shunting the sub-track circuit
section between the DCR and transmitter, and the sub-track circuit is reported as
occupied.
4.4
4.4.1

Track Circuit Specifications


Drop shunt

The maximum resistance of a non inductive resistor which, when connected between
the rails causes track circuit to be detected as occupied is called the Drop Shunt.
Outside of the ESJ, a Minimum Drop Shunt value of 0.1 is guaranteed, in the
absence of external contaminants.
In the ESJ, the Drop Shunt value varies downwards from 0.1 and there is an
overlap of the shunt areas of the two successive track circuits with RX / TX and RX /
RX ESJ. There is no overlap for TX / TX ESJs, however this arrangement should be
avoided.
The Drop Shunt value is similarly defined for IDCs; a value of 0.1 is guaranteed
between the transmitter and the IDC.
4.4.2

Traction return

UM71 track circuits are not designed to operate in single-rail mode under traction.
4.4.3

Storage conditions

Track circuit equipment needs to be stored in dry, well ventilated area. Do not store
near equipment releasing corrosive vapours such as lead acid batteries. Storage
temperature range is -30 C to +70 C.

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual


SECTION 5.0
5.1
5.1.1

15

DESIGN

Signal Arrangement Level Design


General

1. Track circuits and associated equipment are immunised against DC traction


(provided that proper bonding is provided) and can be used in:
a. DC traction areas
b. Areas with no traction supply
2. Track circuit lengths shall be measured between the following objects, unless
otherwise specified:
a. ACI to ACI
b. ACI to IRJ
c. IRJ to IRJ
3. Applicable reference drawings are:
a. STD_G0059 UM71 cabling layout and track connections
b. STD_G0060 UM71 track circuit connections
c. STD_G0242 Layout of signal, trainstop, TPWS and UM71 track circuit
5.1.2

Physical arrangement: End-fed track circuit

In this arrangement, one end of the section is fed by a transmitter (TX), with the other
end attached to a receiver (RX).
The conventional configuration is the use of this arrangement with ESJs terminating
the track circuit on both sides.
End-fed track circuit

Receiver (RX)

Transmitter (TX)
Figure 6 End-fed track circuit

The following table shows the length limits for various track circuit separation
methods.
Configuration
Without track
compensation

ESJ to ESJ
ESJ to IRJ
IRJ to IRJ
ESJ to ESJ, ESJ to IRJ,
IRJ to IRJ

With track
compensation

Minimum length
100 m
50 m
50 m
600 m

Maximum length
650 m
650 m
1100 m

Table 7 End-fed track circuit lengths

5.1.3

Physical arrangement: Centre-fed track circuit

In this arrangement, transmitter (TX) feeds two branches from the centre of the track
circuit. Receivers (RX-A and RX-B) are installed at each branch end. If either
branch (ie RX-A to TX or RX-B to TX) is occupied, the entire track circuit will be
reported as being occupied.

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

16

This arrangement is also alternately known as an Intermediate Transmission track


circuit.
Centre-fed track circuit

Receiver A (RX-A)

Receiver B (RX-B)

Transmitter (TX)
Figure 7 Centre- fed track circuit

The following table shows the length limits for various track circuit separation
methods.
Configuration
Minimum length Maximum length
ESJ to ESJ
Without track
100 m per
650 m per
ESJ to IRJ
compensation
branch
branch
IRJ to IRJ
200 m overall
1300 m overall
ESJ to ESJ
With track
600 m per
1100 m per
ESJ to IRJ
compensation
branch
branch
IRJ to IRJ
1200 m overall
2200 m overall
Table 8 Centre-fed track circuit lengths (short form)

Ideally the transmitter is located at the halfway point to give an even split. However,
some length imbalance (ie difference between long and short branch lengths) is
permitted, to a maximum of 30% of the ideal branch length.
The following table illustrates the limits without track circuit compensation,
incorporating these factors:
maximum imbalance at 30% of ideal branch length
100m minimum branch length
650m maximum branch length
Constrained for total track circuit length
Total track
circuit length
200
210
220
230
240
250
260
270
280
290
300
400
500
600
700

Ideal branch length


100
105
110
115
120
125
130
135
140
145
150
200
250
300
350

Minimum length of
short branch
100
100
100
100
102
106.25
110.5
114.75
119
123.25
127.5
170
212.5
255
297.5

Maximum length of
long branch
100
110
120
130
138
143.75
149.5
155.25
161
166.75
172.5
230
287.5
345
402.5

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual


800
900
1000
1050
1100
1150
1200
1250
1300

400
450
500
525
550
575
600
625
650

340
382.5
425
446.25
467.5
500
550
600
650

17

460
517.5
575
603.75
632.5
650
650
650
650

Table 9 Centre-fed track circuit lengths without compensation

The following table illustrates the limits with track circuit compensation, incorporating
these factors:
maximum imbalance at 30% of ideal branch length
600m minimum branch length
1100m maximum branch length
Constrained for total track circuit length
Total track
circuit length
1200
1250
1300
1350
1400
1450
1500
1550
1600
1650
1700
1750
1800
1850
1900
1950
2000
2050
2100
2150
2200

Ideal branch length


600
625
650
675
700
725
750
775
800
825
850
875
900
925
950
975
1000
1025
1050
1075
1100

Minimum length of
short branch
600
600
600
600
600
616.25
637.5
658.75
680
701.25
722.5
743.75
765
786.25
807.5
850
900
950
1000
1050
1100

Maximum length of
long branch
600
650
700
750
805
833.75
862.5
891.25
920
948.75
977.5
1006.25
1035
1063.75
1092.5
1100
1100
1100
1100
1100
1100

Table 10 Centre-fed track circuit lengths with compensation

5.1.4

Physical arrangement: Track circuit over points

In this arrangement, transmission is provided at the converging end of the track


circuit. Receivers are installed at the other ends of the track circuit. This is
effectively a centre-fed arrangement with one leg folded back on the other; additional
requirements apply on account of the points bonding required between the two legs.
This is a non-preferred configuration within the Metropolitan area; Infrastructure
Manager approval is required prior to selection in design.

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

18

Figure 8 Track circuit over points

Refer to the centre-fed arrangement section (5.1.3) for length limitations.


5.1.5
1.
2.
3.

4.

Track circuit separation and frequency selection


Adjacent track circuits shall be separated through either an ESJ or IRJ.
If track circuit is adjacent to a non-UM71 track circuit, then an IRJ shall be
used for separation.
Track circuits have a choice of four carrier frequencies, grouped in two
frequency pairs.
a. Frequency pair V1 consists of 1700 Hz (F1) and 2300 Hz (F2), and is
generally allocated to the down track.
b. Frequency pair V2 consists of 2000 Hz (F1) and 2600 Hz (F2), and is
generally allocated to the up track.
Track circuits installed on adjacent parallel tracks shall operate on a different
frequency pair.

5.1.5.1 Separation with ESJ


1.
2.

Adjacent track circuits shall use different frequencies from the same
frequency pair.
Adjacent track circuits shall not use frequencies from different pairs.

Figure 9 Frequency arrangement with multiple tracks

3.
4.

An ESJ may be configured with:


a. Two receivers, or
b. A transmitter and a receiver.
An ESJ configured with two transmitters is not preferred on account of
excessive power dissipation in the TUs and is subject to additional
restrictions:

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

19

a.
b.
c.
d.

An IRJ solution shall first be considered.


This TX-TX configuration shall be a solution of last resort.
Agreement of the Infrastructure Manager is required.
The length of the short track circuit TC-A shall be 50% of the longest
possible track (ie 50% of 650 m is 325 m).
e. The use of boosting units or track compensation further increases power
dissipation and is advised against.

Figure 10 Non-preferred TX-TX configuration

5.1.5.2 Separation with IRJ


1.
2.

Adjacent track circuits shall not use the same frequency.


Adjacent track circuits may use frequencies from different frequency pairs.

5.1.5.3 ESJ leading into non-track circuited area


1.
2.

A short circuit shall be placed 19 m from the TX or RX connection, into the


non-track circuited area in lieu of a TU.
ACI shall not be used in this configuration.

Two wires of 95mm2

Figure 11 ESJ into non-track circuited area

5.1.5.4 ESJ co-located with TPWS unit


1.
5.1.6
1.
2.
3.

Refer to 012.0.2 Signalling Principles Signal Enforcement


Track compensation
Compensation shall not be used on a track circuit with an IDC overlaid.
Transmitter shall have the high power jumpers installed (M2-M4 and M2-M5).
The capacitor value shall be determined by the following table:

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual


Track circuit frequency (Hz)
1700
2000
2300
2600

20

C (F)
35
35
20
20

Table 11 Track compensation capacitance

4.

5.

The capacitor shall satisfy or better the following characteristics:


a. +/- 5% tolerance on capacitance
b. Not of electrolytic construction
c. Not polarised
d. AC working voltage rating of 420Vrms
The spacing of the capacitors shall be determined via the following full-step /
half-step scheme:
a. 100 m spacing (full-steps) between successive compensation capacitors.
b. 35 m to 85 m spacing (half-steps) between the first and last capacitor and
the adjacent TU track connection points.
c. The two half-steps on both ends of the track circuit shall be equal in
length.
d. Additional variations to this scheme shall require agreement from the
Infrastructure Manager.

Figure 12 Track compensation

Example 1:
The track circuit is ESJ to ESJ with a length between TU of 750m.
The amount of capacitors required is 7 (750 100 = 7.5, rounded down).
The half steps are 75m (750 600 = 150 2 = 75m).

Figure 13 Track compensation example 1

Example 2:
The track circuit is ESJ to IRJ with a length between TU and IRJ of 936m.
The amount of capacitors required is 9 (936 100 = 9.36, round down).
The half steps are 68m (936 800 = 136 2 = 68m).

Figure 14 Track compensation example 2

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual


5.1.7
1.
2.
3.
4.
5.
6.
7.
8.
5.1.8
1.
2.
3.
4.
5.

21

Traction requirements
General bonding and traction requirements are defined in VRIOGS 010.7
Track Bonding, Track Circuit Connections and Traction Interfaces.
Track circuits shall be configured for double-rail operation where the tracks
may carry traction current.
A cross-bond shall not be formed between two track circuits with the same
frequency.
Traction return shall be provided primarily by rail and impedance bonds.
Track circuit components (such as ACIs) shall not be used in lieu.
Impedance bond used shall have an impedance higher than 17 at the
carrier frequency of the track circuit.
Impedance bond shall not be installed within 20m of a track compensation
capacitor.
Impedance bond shall not be installed within 100m of an ACI.
a. This restriction does not apply for an IRJ terminated track circuit where
the ACI is co-located with the impedance bond.
Impedance bond shall not be installed between a TX and PPD.
Use of Intermediate Data Collectors
IDCs shall not be used within compensated track circuits.
Maximum of one IDC is permitted per track circuit branch.
a. In a centre-fed arrangement, an IDC can be installed for each branch.
b. In an end-fed arrangement, only a single IDC can be installed.
Designer shall be aware that the DCR configuration will not provide a clearly
defined sub-track circuit boundary.
Minimum sub-track circuit length shall be 20 m, dependent on worst case
rollingstock 7 .
The following length limits shall be complied with.
Configuration

Maximum length of parent track circuit


branch
PPD without boosting unit Without track
250 m
8
compensation
PPD with boosting unit
400 m
DCR
650 m
Track compensation can not be used in this arrangement.
Table 12 IDC limits on parent track circuit lengths

6.

7
8

Specific requirements for PPDs:


a. PPD shall not be installed more than 100 m from the TU track connection
point on the TX side.
b. The necessity and size of the boosting unit shall be determined during the
testing and commissioning process.
c. The boosting unit, if used, shall be located 1 m from the PPD on the RX
side.

Ensures trains do not straddle a sub-track circuit, causing false vacancy indications.
In-field testing will positively determine whether a boosting unit is required.
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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

5.2

22

Detailed Level Design


Cable and wire requirements

5.2.1

Location
to
trackside

Connection
TX to MU,
RX to MU for all
except for IDCs
RX to PPD (with
adjustable resistor)

At
trackside
only

RX to PPD (with MU)


RX to MU (DCR
configuration)
MU to TU
TU to track, ACI to
track
TU to ACI
MU to track (DCR
configuration)

Within
location
only

Jumper Maximum
power output
Jumper KEM, KRV,
Modulation, Delayed
energisation
Wiring for track relay,
power supply, etc.

Sizing
0.90mm2 2 Pair Cable
(VRIOGS 012.6.18)
1.5mm2 2 Conductor
Cable (Refer to SECTION
10.0 for specification)
7 / 0.85mm 2 Core Cable
(VRIOGS 012.6.5)
0.90mm 2 Pair Cable
(VRIOGS 012.6.18)
7 / 0.85mm 2 Core Cable
(VRIOGS 012.6.5)
Aluminium 95mm2 1 Core
Wire (VRIOGS 012.6.33)

Copper 84 / 0.30mm,
6mm2 cable (VRIOGS
012.6.31 and 012.6.32)
24/0.20 1 Core Wire
(VRIOGS 012.6.3)

Length
< 150 m

Other

151 m
600 m
< 100 m

1000
adjustable
resistor

< 1000 m
As per
typical
As per
typical
430 mm
+/- 20mm

As short as
possible
Along wire
length between
lug hole centers
Short and direct
< 50 mm

As short as
possible

< 90 mm
Not
defined

Table 13 Sizing requirements

5.2.1.1 Extended length cabling from location to trackside


1.

5.2.2
1.

5.2.3
1.

If the 1.5mm2 2 Conductor Cable is required for a length exceeding 600 m,


Infrastructure Manager approval is required.
Cable frequency allocation
A single multi-pair cable shall not carry TX and RX circuits of the same
frequency.
Track circuit adjustments
All adjustable values and jumper connections for each track circuit, where
practicable, shall be estimated and provided for installation. The following
table is provided as reference, as the connection details (aside from KEM and
KRV) are shown in the typical drawings in Appendix B.

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual


Connections available
for cable or jumper.
KEM

Connections
are applicable
for which unit:
TX

23

Connection details
As covered by 5.2.3.3.

V1, V2, V3, V4, V5, V6,


V7, V8
R1, R2, R3, R4, R5,
R6, R7, R8, R9, R10
R1, R2, V1, V2, E1,
E2, L3, L4, 5, 6, 7, 8, 9,
10, 11, 12, 13, 14
M2, M4, M5

MU

Various, see typical drawings


in Appendix B.

TX

Delayed
energisation

C, C1, C2

RX

Modulation

M1, M3

TX

Without track compensation:


M2, M4, M5 not connected
With track compensation:
M2-M4 and M2-M5 shorted
Default: C-C2 shorted to give
2.3 s delay.
C-C1 shorted will give 0.5 s
delay, where required.
M1-M3 shorted

KRV
KMU
Maximum
power output

RX

Table 14 Configurable jumpers

2.
3.

4.

5.2.4
1.
2.
3.

TMUs are configured in a similar 9 fashion as the individual MUs and TUs,
refer to the TMU wiring diagrams in Appendix B.
KEM and KRV ratios shall be estimated where practicable, depending on the
track circuit arrangement:
a. End-fed track circuits with ESJs on one or both sides shall use the
universal adjustment method as per 5.2.4.
b. All other track circuit arrangements, including the following, use the
specific adjustment method as per 7.4.5, and estimation is not required.
i. All centre-fed track circuits
ii. All IDC sub-track circuit RXs
iii. End-fed track circuits with IRJs on both sides
iv. Track circuit over points
v. Special scenarios Track circuits in the Melbourne Underground
Loop
Appendix B 9.1 and 9.2, KEM and KRV Connections shall be used as the
reference in providing the jumper and cable connections for a given KEM or
KRV ratio.
Universal adjustment
Universal adjustment is a pre-computed tabular approach to estimating the
required KEM and KRV ratios.
Appendix A KEM and KRV Universal Adjustment shall be used as the
reference.
Appendix A is the collection Appendices from one of the source documents
on which this standard is based, giving KEM and KRV settings for a number
of different arrangements.

Note that there are some wiring changes eg the removal of L3 and L4 by the use of a
different wiring scheme (same functionality isolation of the inductor - is still provided for).
TMUs no longer support the DCR configuration, so the resistor has been removed
completely.
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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual


4.
5.
6.
7.
8.
9.
10.

5.2.5
1.

2.

5.2.6
1.

5.2.7
1.
5.2.8
1.

5.2.9
1.

24

Tables are based on carrier frequency, track circuit separation method, track
compensation, track circuit arrangement and an expected minimum ballast
resistance of 1.5 -km.
Appendix As distances are measured between the TUs defining the track
circuit, rather than ACI-ACI, ACI-IRJ or IRJ-IRJ distances as per 5.1.1.
Track circuit length shall be rounded up to the nearest entry in the Appendix A
tables for the purposes of determining KEM and KRV ratios.
Appendix A uses terminology which may not be immediately familiar.
a. Term End of section transmission is equivalent to End-fed
b. Term IJ is equivalent to IRJ
Appendix 1 within Appendix A covers:
a. End-fed, ESJ on both ends of track circuit, without track compensation
b. End-fed, ESJ on both ends of track circuit, with track compensation
Appendix 2 within Appendix A covers:
a. End-fed, ESJ on TX end, IRJ on RX end, without track compensation
b. End-fed, ESJ on TX end, IRJ on RX end, with track compensation
Appendix 3 within Appendix A covers:
a. End-fed, IRJ on TX end, ESJ on RX end, without track compensation
b. End-fed, IRJ on TX end, ESJ on RX end, with track compensation
ESJ requirements
ESJs shall be situated on formations that have uniform dielectric
characteristics, so far as practicable. The following are the minimum
requirements:
a. All sleepers within ESJ to comprise of either timber or concrete, but not a
mixture.
b. ESJ shall not be installed across two different formation types, such as
ballast and slab.
ESJs shall be installed on rails that have uniform transmission line
characteristics. The following are the minimum requirements:
a. ESJ track wires shall not be crossed, and shall be as short and direct as
possible.
b. ESJs shall not be installed near metal objects, such as metal bridges,
railing.
c. ESJs shall not contain mechanical joints.
d. ESJs shall not be directly connected to non-ESJ components, such as
spark gaps.
TU requirements
Each track circuit shall be bracketed by TUs of the matching variant. e.g. A
track circuit operating at V1F1 (ie 1700 Hz) is bracketed by V1F1 TUs.
ACI requirements
ACIs shall not be installed near metal objects, such as metallic railing.
MU requirements
If a Dual Matching Unit is used, it shall be placed at the TX side of the ESJ to
minimise the cable length from the MU to the transmitting TU.
PPD requirements
A PPD can be connected to the RX via a MU or an adjustable resistor.

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

2.

5.2.10
1.

2.

5.2.11
1.
2.
3.
4.

25

a. MU is better for noise immunity.


b. Adjustable resistor allows for more flexibility.
A PPD configuration shall require the TX to be set for high maximum power
output.
Delayed energisation
The standard configuration shall be a 2.3 s delay to the energisation of a
receivers associated track relay, implemented via setting a C C2 jumper.
In this instance, no external timer is required for typical applications; the 2.3 s
delay is provided by the receiver.
The alternate configuration of a 500 ms delay, implemented via a C C1
jumper, shall only be considered for CBI installations where vital software
timers are used for loss of shunt purposes.
Ventilation
The ventilation requirements in this section are specific to UM71 track circuit
equipment installed on the NS1 equipment rack.
TX units require a ventilation module mounted immediately above.
RX units require a spacer module mounted between it and a vertically
adjacent TX unit.
Spacer modules may be occupied by equipment other than TX or RX units
(eg relays).

Figure 15 Ventilation arrangements

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual


5.2.12
1.
2.
3.

26

Lightning protection
Requirements specified in this section are over and above any generic
lightning protection requirements for a location or site.
The screen from 0.90mm2 2 Pair Cables (VRIOGS 012.6.18) used to connect
the TX or RX to the MU shall be earthed only at the TX or RX location.
It is preferable that lightning arrestors are installed to protect the incoming
local cables. The lightning arrestors shall be type approved and installed as
per type approval conditions.

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual


SECTION 6.0
6.1
1.

6.2
1.

27

Installation

All cabling
If cable selections were not specified by the designer, the cable requirements
specified in 5.2.1 shall be used.
Trackside units
The following table lists the different trackside units and their variants; each
unit resides in a single trackside case (including the Dual Matching Unit).
Unit Type
Tuning Unit
Matching Unit
Tuning Matching Unit
Air Core Inductor

Variant Type
Frequency
Form factor
Frequency
N/A

Variants
V1F1, V1F2, V2F1, V2F2
Single, Dual
V1F1, V1F2, V2F1, V2F2
Single

Table 15 Trackside unit variants

2.

6.2.1
1.

6.2.2
1.
6.3
1.
2.
3.
4.
5.
6.

Trackside equipment shall be installed on mounting posts as per marked-up


version of drawing F5723 included in this Standard (refer to 9.11).
a. The 1M type shall be used for supporting a single trackside case.
b. The 2M type shall be used for supporting two trackside cases back-toback.
c. Mounting post shall be stabilised using a concrete base.
d. Mounting post shall be ideally installed 1.5 m from the closest rail. A
maximum distance of 2.5 m is permitted if site constrained.
e. Top of mounting post shall be 500 mm above ground.
Matching Unit (Single)
Where an end fed configuration is used, MU shall be mounted back-to-back
with the TU associated with the TX.
Air Core Inductor
Vandal proof metal boxes shall not be used on an ACI.
On-track and cabling from track to trackside
All connection to the rail is by type approved bolted connections and
connectors.
Cables shall be routed in parallel throughout their common travel and
positioned on the sleeper edge.
Cables shall be measured and cut to suit location; direct to rail and length
minimised.
Cables shall not be twisted around each other in any way.
Cables shall be secured together by means of UV resistant black heavy nylon
cable ties, at approximate intervals of 250 mm.
Cables shall not be placed in close proximity with metallic objects other than
the rail, including:
a. Being secured with metallic fittings.
b. Enclosed in metallic pipes.

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

28

cable ties

cable tie

0.5m

Figure 16 Trackside equipment

6.3.1
1.
2.
6.3.2
1.

6.3.3
1.

6.3.4
1.

2.
3.
6.3.5
1.

ESJ arrangement
ESJ length shall be 23 m 0.15 m.
The ESJ requirements stated in 5.2.3 shall be complied with.
ACI track connection
ACI track connection point shall be placed at the ESJ midpoint 0.2 m,
nominally 11.5 m from the nearest TUs.
TU track connection
TU track connection point shall be placed such that the trackside cabling to
the TU is perpendicular to the rail.
Configuration: PPD
Refer to Appendix 9.7 for PPD plans:
a. Pin Point Detector
b. Pin Point Detector Installation Plan
c. Pin Point Detector Configuration with MU
d. Pin Point Detector Configuration with adjustable resistor
Holes shall be drilled for the possibility of mounting a boosting unit, 1 m from
the PPD on the RX side. The boosting unit itself shall not be installed; the
setup process will cover that.
PPD shall be installed via mounting brackets cembred onto the nearest rail.
Configuration: DCR
Refer to Appendix 9.6 for DCR plans:
a. Data Collector
b. Data Collector Installation Plan
c. Data Collector Configuration

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual


6.3.6
1.

6.3.7
1.

2.
3.

29

Configuration: ESJ
Refer to Appendix 9.3 for various ESJ configurations:
a. ESJ with Dual Matching Unit
b. ESJ with Single Matching Units or Tuning Matching Units
c. ESJ Installation Plan MU / TU or TMU
d. ESJ Installation Plan ACI
e. ESJ Configuration TX / RX with Dual MU
f. ESJ Configuration TX / RX
g. ESJ Configuration RX / RX with Dual MU
h. ESJ Configuration RX / RX
Configuration: Centre-fed TX
Refer to Appendix 9.5 for the centre TX in a centre-fed track circuit:
a. Centre-fed Transmission
b. Centre-fed Transmission Installation Plan
c. Centre-fed Transmission Configuration
ACI and TU shall be mounted back-to-back with the ACI facing the track.
The TU to ACI connection length as per 5.2.1 shall be strictly observed. In
particular, the length is measured between centres of lug holes.

+/- 20mm

Figure 17 TU to ACI cable

6.3.8
1.

2.
3.
4.

Configuration: IRJ
Refer to Appendix 9.4 for various IRJ configurations:
a. IRJ TX / RX
b. IRJ Installation Plan MU / TU or TMU
c. IRJ Configuration TX
d. IRJ Configuration TX with Impedance Bond
e. IRJ Configuration RX with Impedance Bond
ACI and TU shall be mounted back-to-back with the ACI facing the track.
The TU to ACI connection length as per 5.2.1 shall be strictly observed. In
particular, the length is measured between centres of lug holes.
ACI shall be connected to the impedance bond associated with the IRJ, rather
than a direct track connection, if practical.

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

30

cable tie

Figure 18 Trackside equipment with IRJ

6.4

Location equipment and cabling from location to trackside

1.

The cable / frequency allocation requirement stated in 5.2.1.1 shall be


complied with.
Each pair of wires connecting from the outgoing cable termination to either
the output of the TX or the input of the RX shall be twisted.

2.

6.4.1
1.
2.

Equipment coding
Each TX and RX is mechanically coded for the NS1 equipment rack, to
prevent incorrect positioning.
Following table shows the different codes for the RX / TX frequencies.

EQUIPMENT TYPE
Transmitter
V1F1
V1F2
V2F1
V2F2
Receivers
V1F1
V1F2
V2F1
V2F2

FREQUENCY (Hz)

CODE

1700
2300
2000
2600

13-7-23
13-7-25
13-7-26
13-7-34

1700
2300
2000
2600

248-26
248-34
248-35
248-36

Table 16 TX and RX mechanical coding

3.

Refer to Appendix 9.8 for images of the TX coding plug placements, and
Appendix 9.9 for images of the RX coding plug placements.

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual


6.4.2
1.

31

Ventilation
The ventilation requirements stated in 5.2.11 shall be complied with.

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual


SECTION 7.0
7.1
1.
2.
3.
4.

7.2
1.
2.
3.

4.
5.
6.
7.

7.3
1.

7.3.1
1.
2.
3.
4.

32

Testing and Commissioning

General
VRIOGS 012.5 remains as the top-level T&C document.
T&C requirements specified in this document are intended to supplement
VRIOGS 012.5 in terms of detail that is specific to UM71 track circuits.
Typically the requirements in this section are sequential in nature, and shall
be read accordingly.
Where there are deviations from the typical setup, eg if the 2.3sec LOS timer
is not set, they need to be accounted for in the following steps.
Track circuit setup
Prior to testing, the track circuits need to be setup for operation.
IDC sub-track circuits are excluded from this setup stage; they require the
parent track circuit to be commissioned first.
TX need the following to be set through jumpers:
a. Output level, also known as KEM
b. Maximum power output
c. Modulation output
RX need the following to be set through jumpers:
a. Input level, also known as KRV
Each MU need the following to be set through jumpers:
a. Configuring MU for proper interfacing
Depending on track circuit configurations, the installer may have installed
preliminary (jumper) settings as specified by the designer. In these cases,
the setup is now deemed to be complete.
Where preliminary settings were not installed (intentionally or otherwise), the
setup shall occur in the field.
a. Section SECTION 5.0 and typicals in Appendix B shall be used to
determine the jumper settings.
b. If the specific adjustment method is required, refer to 7.4.5.
IDC setup
Before an IDC can be setup for operation, its parent track circuit shall first be
commissioned and set to work.
PPD setup
If the MU configuration is used, boosting unit selection is the only setup
required.
If the adjustable resistor configuration is used, the resistor shall be adjusted to
give a typical voltage of 330 mV across R1- R2 at the PPDs RX, with a
minimum of 270mV.
KRV jumpers are not be used.
Boosting unit selection
a. Four variants are available: 10 , 7.5 , 5 and 2.5 , all rated at 10 W.
b. A variable resistor shall be used to determine which boosting unit variant
(if any) is selected.
c. The boosting unit, if required, shall have the highest resistance that is
reasonable and suitable.
d. Boosting units shall not be operated above their rated power.

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

7.3.2
1.
2.
7.4
1.

2.

3.
7.4.1
1.
2.

7.4.2
1.
2.
3.
4.
5.

7.4.3
1.
2.
3.
4.
5.

33

DCR setup
The DCRs RXs R1-R2 voltage shall have a target value equal to the parent
branchs RXs R1-R2 voltage.
The DCRs KRV ratio shall be less than the parent branchs KRV.
Checking
Following references are provided for convenience:
a. Appendix 9.3 for ESJ configurations
b. Appendix 9.4 for IRJ configurations
c. Appendix 9.5 for centre-fed TX configuration
d. Appendix 9.7 for PPD configuration
e. Appendix 9.6 for DCR configuration
Confirm that the bonding, wiring and connections are complete for:
a. On-track (bonding), and track connection points
b. Track to trackside units
c. Trackside units to location
d. Within location
Confirm jumpers on the TX and RX units are in place as per plans.
Checking TX
Power up the TX and check voltage on terminals A+ and A- is 24 volts (22.5V
to 28.8V).
Check the output of the TX is between maximum and minimum values shown
on the universal adjustment tables in Appendix A, where applicable.
Checking RX
Power up the RX and check voltage on terminals A+ and A- is 24 volts (22.5V
to 28.8V).
Check the track relay has energised. The track relay will energise at 200
210mV and de-energise at 170 180mV.
Check the RX for the C C2 jumper (2.3 second loss of shunt timer)
Perform the measurements specified on the track circuit data sheet. Check
that the measured values fit within the specified values of the universal
adjustment tables in Appendix A, where applicable.
Perform the 0.1 ohm test shunt at the extremes and centre of the track circuit.
a. Verify the track relay itself has de-energised.
b. Check there is a perceptible delay prior to relay energisation after shunt
removal.
c. Shunts shall be placed 1m inside the track circuit from each TU for the
tests at extremities.
Checking PPD
Check that the PPD is placed 65 mm from running edge of rail.
Check that the boosting unit is 1 m from the PPD on the RX side.
Check the RX for the C C2 jumper (2.3 second loss of shunt timer)
Power up the RX and check voltage on terminals A+ and A- is 24 volts (22.5V
to 28.8V).
If the adjustable resistor configuration is used, confirm minimum voltage at
R1-R2 of 270 mV.

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual


6.
7.

34

Check the track relay has energised.


Perform the 0.1 ohm test shunt at the extremes of the sub-track circuit.
a. Verify the track relay itself has de-energised.
b. Check there is a perceptible delay prior to relay energisation after
shunt removal.
c. Shunts shall be placed 1m inside the sub-track circuit from either the
TU or the PPD.

Figure 19 PPD test shunt locations

7.4.4
1.
2.
3.
4.
5.
6.

Checking DCR
Check the MU does not have a jumper across R1-R2. The series resistor
must not be bypassed.
Check the RX for the C C2 jumper (2.3 second loss of shunt timer)
Verify KRV ratio for the DCR is less than the KRV ratio of the parent branchs
RX.
Power up the RX and check voltage on terminals A+ and A- is 24 volts (22.5V
to 28.8V).
Check the track relay has energised.
Perform the 0.1 ohm test shunt at the extremes of the sub-track circuit.
a. Verify the track relay itself has de-energised.
b. Verify the R1-R2 voltage is less than 150 mV.
c. Check there is a perceptible delay prior to relay energisation after
shunt removal.
d. Shunts shall be placed 1m inside the sub-track circuit from either the
TU or the DCRs MU.

Figure 20 DCR test shunt locations


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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

7.4.5
1.
2.
3.
4.
5.

6.

35

Specific adjustment
Specific adjustment is an empirical approach to setting the KRV ratio.
It has been colloquially referred to as the 350 Rule.
Specific adjustment shall only be used with the consent of the Infrastructure
Manager, and where the universal adjustment method is either not directly
applicable or has failed to provide a stable track circuit.
The weather condition (very wet/wet/dry, etc) shall be recorded.
KRV ratio, in the first instance, shall be determined by the following formula,
with the result rounded up:
KRV = 350mV x 58
V1V2
a. V1V2 is the voltage across RXs V1-V2.
Where additional KRV adjustments are required for track circuit operation, the
following limits are in place:
a. Voltage across RXs R1-R2 does not fall below 240 mV, if adjustment is
made in wet weather.
b. Voltage across RXs R1-R2 does not exceed 450 mV if adjustment is
made in dry weather.
c. Infrastructure Manager approval is particularly critical if additional
adjustments are used.

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

SECTION 8.0

36

Appendix A

KEM and KRV Universal Adjustment


The data presented has been transcribed from the existing UM71 adjustment tables from the PTC era.
The document was labelled as:
CS Transport
Public Transport Corporation, Melbourne
UM71 Track Circuit Adjustment Tables, Revision A
Author: M. Guillard
Dated 28/2/95
CTR/SPS/GML/95/40.333
Document header was co-signed by:
A. Gros (Checker)
M. Guicharnaud (Project Manager)
A. Delorme (Quality Assurance)
The tables are presented in the following order:
End-fed track circuit, ESJs at both transmitter and receiver
End-fed track circuit, ESJ at transmitter and IRJ at receiver
End-fed track circuit, IRJ at transmitter and ESJ at receiver
Modifications from original document:
Compensation capacitance values were adjusted (during the PTC era) from 22 uF and 33 uF to 22 uF and 35 uF
respectively on account of parts availability. This is now reflected in the configuration heading in the following
tables.

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

37

Configuration: End-fed track circuit with no compensation; Frequency is 1700 Hz; Transmitter on ESJ; Receiver on ESJ

3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5

TRANSMITTER
UTR (V)
ltr (mA)
V Output
average
min
Max
45
51
190
45
51
185
45
51
181
45
51
178
45
51
176
45
51
174
45
51
173
45
51
172
45
51
172
45
51
171
45
51
171
45
51
171

TRANSMISSION
UVT (V)
UVR (V)
V Output
Track V RxEnd
min
Max
min
Max
2.02
2.80
1.13
1.95
2.06
2.87
1.03
1.79
2.10
2.93
0.93
1.64
2.14
2.99
0.85
1.52
2.17
3.04
0.78
1.41
2.19
3.08
0.71
1.31
2.22
3.12
0.66
1.23
2.24
3.15
0.61
1.15
2.25
3.18
0.56
1.09
2.27
3.21
0.53
1.03
2.28
3.23
0.49
0.97
2.29
3.26
0.46
0.92

UV1V2(V)
V @ V1 + U2
min
Max
1.24
2.13
1.12
1.95
1.02
1.79
0.93
1.66
0.85
1.54
0.78
1.43
0.72
1.34
0.67
1.26
0.62
1.19
0.57
1.12
0.54
1.06
0.50
1.01

3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5

45
45
45
45
45
45
45
45
45
45
45

2.29
2.30
2.31
2.31
2.31
2.32
2.32
2.32
2.32
2.32
2.32

0.47
0.44
0.41
0.39
0.36
0.34
0.32
0.30
0.29
0.27
0.26

Length
TC
(m)
100
125
150
175
200
225
250
275
300
325
350
375

KEM

400
425
450
475
500
525
550
575
600
625
650

51
51
51
51
51
51
51
51
51
51
51

171
171
171
171
172
172
172
172
173
173
173

3.28
3.29
3.31
3.33
3.34
3.35
3.36
3.38
3.39
3.40
3.40

0.43
0.40
0.38
0.35
0.33
0.31
0.30
0.28
0.26
0.25
0.23

0.88
0.84
0.81
0.77
0.74
0.71
0.69
0.66
0.64
0.62
0.60

0.96
0.92
0.88
0.84
0.81
0.78
0.75
0.72
0.70
0.68
0.66

RECEIVER
KRV

12
13
14
15
17
18
20
21
23
25
26
28

UR1R2 (V)
V @ R1 + R2
min
Max
0.25
0.45
0.25
0.44
0.24
0.44
0.24
0.43
0.25
0.45
0.24
0.45
0.24
0.47
0.24
0.46
0.24
0.47
0.24
0.49
0.24
0.48
0.24
0.49

30
32
34
36
38
40
43
45
48
51
54

0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24

0.50
0.51
0.52
0.53
0.53
0.54
0.56
0.56
0.58
0.60
0.61

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

38

Configuration: End-fed track circuit with 35 uF compensation capacitors; Frequency is 1700 Hz; Transmitter on ESJ; Receiver on ESJ
Length
TC
(m)
600
700
800
900
1000
1100

KEM

3
3
3
3
3
3

TRANSMITTER
UTR (V)
ltr (mA)
V Output
average
min
Max
39
44
191
39
44
195
39
44
194
39
44
191
39
44
191
39
44
193

TRANSMISSION
UVT (V)
UVR (V)
V Output
Track V RxEnd
min
Max
min
Max
1.83
2.64
0.88
1.80
1.80
2.52
0.81
1.90
1.76
2.33
0.73
1.76
1.78
2.44
0.64
1.58
1.80
2.59
0.58
1.55
1.80
2.54
0.53
1.60

UV1V2(V)
V @ V1 + U2
min
Max
0.96
1.97
0.89
2.08
0.80
1.93
0.70
1.72
0.64
1.69
0.58
1.75

RECEIVER
KRV

15
16
18
20
22
24

UR1R2 (V)
V @ R1 + R2
min
Max
0.24
0.51
0.24
0.58
0.24
0.60
0.24
0.60
0.24
0.64
0.24
0.73

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

39

Configuration: End-fed track circuit with no compensation; Frequency is 2000 Hz; Transmitter on ESJ; Receiver on ESJ

3.75
3.75
3.75
3.75
3.75
3.75
3.75
3.75
3.75
3.75
3.75
3.75

TRANSMITTER
UTR (V)
ltr (mA)
V Output
average
min
Max
48
54
176
48
54
172
48
55
168
48
55
166
48
55
164
48
55
163
48
55
162
48
55
161
48
55
161
48
55
161
48
55
160
48
55
160

TRANSMISSION
UVT (V)
UVR (V)
V Output
Track V RxEnd
min
Max
min
Max
2.15
2.98
1.19
2.07
2.19
3.06
1.08
1.89
2.24
3.13
0.97
1.73
2.27
3.19
0.89
1.60
2.31
3.24
0.81
1.48
2.33
3.29
0.74
1.38
2.36
3.33
0.68
1.29
2.38
3.37
0.63
1.21
2.39
3.40
0.58
1.14
2.41
3.43
0.54
1.08
2.42
3.46
0.50
1.02
2.43
3.48
0.47
0.97

UV1V2(V)
V @ V1 + U2
min
Max
1.31
2.26
1.18
2.07
1.07
1.90
0.97
1.75
0.89
1.63
0.81
1.51
0.75
1.42
0.69
1.33
0.64
1.25
0.59
1.18
0.55
1.12
0.51
1.07

3.75
3.75
3.75
3.75
3.75
3.75
3.75
3.75
3.75
3.75
3.75

48
48
48
48
48
48
48
48
48
48
48

2.44
2.44
2.45
2.45
2.45
2.46
2.46
2.46
2.46
2.46
2.46

0.48
0.45
0.42
0.39
0.37
0.35
0.33
0.31
0.29
0.27
0.25

Length
TC
(m)
100
125
150
175
200
225
250
275
300
325
350
375

KEM

400
425
450
475
500
525
550
575
600
625
650

55
55
55
55
55
55
55
55
55
55
55

161
161
161
161
161
162
162
162
162
163
163

3.51
3.53
3.54
3.56
3.58
3.59
3.60
3.62
3.63
3.64
3.65

0.44
0.41
0.38
0.36
0.34
0.32
0.30
0.28
0.26
0.25
0.23

0.93
0.89
0.85
0.81
0.78
0.75
0.73
0.70
0.68
0.66
0.64

1.02
0.97
0.93
0.89
0.86
0.83
0.80
0.77
0.74
0.72
0.70

RECEIVER
KRV

11
12
13
15
16
18
19
21
22
24
25
27

UR1R2 (V)
V @ R1 + R2
min
Max
0.24
0.43
0.24
0.43
0.24
0.43
0.25
0.46
0.24
0.45
0.25
0.47
0.24
0.47
0.25
0.48
0.24
0.48
0.24
0.49
0.24
0.49
0.24
0.50

29
31
33
35
38
40
43
45
48
51
54

0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24

0.51
0.52
0.53
0.54
0.56
0.57
0.59
0.60
0.62
0.63
0.65

NOTE: This document is controlled only when viewed on the DOT Engineering Standards website. Any other copy of this document is uncontrolled, and the content may be
inaccurate.

VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

40

Configuration: End-fed track circuit with 35 uF compensation capacitors; Frequency is 2000 Hz; Transmitter on ESJ; Receiver on ESJ
Length
TC
(m)
600
700
800
900
1000
1100

KEM

3.25
3.25
3.25
3.25
3.25
3.25

TRANSMITTER
UTR (V)
ltr (mA)
V Output
average
min
Max
42
47
191
42
47
187
42
47
187
42
47
189
42
47
189
42
47
187

TRANSMISSION
UVT (V)
UVR (V)
V Output
Track V RxEnd
min
Max
min
Max
1.82
2.47
0.99
2.12
1.82
2.45
0.87
1.88
1.87
2.65
0.78
1.80
1.85
2.62
0.71
1.85
1.83
2.44
0.63
1.73
1.85
2.55
0.56
1.58

UV1V2(V)
V @ V1 + U2
min
Max
1.09
2.33
0.95
2.06
0.86
1.97
0.78
2.03
0.70
1.90
0.62
1.74

RECEIVER
KRV

13
15
17
18
20
23

UR1R2 (V)
V @ R1 + R2
min
Max
0.24
0.53
0.24
0.54
0.25
0.58
0.24
0.63
0.24
0.66
0.24
0.69

NOTE: This document is controlled only when viewed on the DOT Engineering Standards website. Any other copy of this document is uncontrolled, and the content may be
inaccurate.

VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

41

Configuration: End-fed track circuit with no compensation; Frequency is 2300 Hz; Transmitter on ESJ; Receiver on ESJ

Length
TC
(m)
100
125
150
175
200
225
250
275
300
325
350
375

KEM

4
4
4
4
4
4
4
4
4
4
4
4

TRANSMITTER
UTR (V)
ltr (mA)
V Output
average
min
Max
51
58
166
51
58
162
51
58
159
51
58
156
51
58
155
51
58
154
51
58
153
51
58
152
51
58
152
51
58
152
51
58
152
52
58
152

400
425
450
475
500
525
550
575
600
625
650

4
4
4
4
4
4
4
4
4
4
4

52
52
52
52
52
52
51
51
51
51
51

58
58
58
58
58
58
58
58
58
58
58

152
153
153
153
153
154
154
154
154
154
155

TRANSMISSION
UVT (V)
UVR (V)
V Output
Track V RxEnd
min
Max
min
Max
2.26
3.15
1.24
2.16
2.31
3.23
1.12
1.97
2.36
3.31
1.01
1.81
2.40
3.38
0.91
1.67
2.43
3.43
0.83
1.55
2.46
3.49
0.76
1.44
2.49
3.53
0.70
1.35
2.51
3.57
0.64
1.26
2.52
3.61
0.60
1.19
2.54
3.64
0.55
1.13
2.55
3.67
0.51
1.07
2.56
3.70
0.48
1.02

UV1V2(V)
V @ V1 + U2
min
Max
1.36
2.37
1.22
2.16
1.11
1.98
1.00
1.83
0.92
1.70
0.84
1.58
0.77
1.48
0.71
1.39
0.65
1.31
0.61
1.24
0.56
1.17
0.52
1.12

2.56
2.57
2.57
2.58
2.58
2.58
2.58
2.58
2.58
2.58
2.58

0.49
0.45
0.42
0.40
0.37
0.35
0.32
0.30
0.28
0.27
0.25

3.72
3.74
3.76
3.78
3.79
3.81
3.82
3.84
3.85
3.86
3.87

0.44
0.41
0.39
0.36
0.34
0.31
0.29
0.28
0.26
0.24
0.23

0.97
0.93
0.89
0.85
0.82
0.79
0.76
0.74
0.71
0.69
0.67

1.06
1.02
0.97
0.93
0.90
0.87
0.84
0.81
0.78
0.76
0.73

RECEIVER
KRV

11
12
13
14
16
17
18
20
22
23
25
27

UR1R2 (V)
V @ R1 + R2
min
Max
0.25
0.45
0.25
0.45
0.24
0.45
0.24
0.45
0.25
0.47
0.24
0.47
0.24
0.46
0.24
0.48
0.25
0.50
0.24
0.49
0.24
0.51
0.24
0.52

29
31
33
35
38
40
43
46
49
52
55

0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24

0.53
0.55
0.56
0.57
0.59
0.60
0.62
0.64
0.66
0.68
0.70

NOTE: This document is controlled only when viewed on the DOT Engineering Standards website. Any other copy of this document is uncontrolled, and the content may be
inaccurate.

VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

42

Configuration: End-fed track circuit with 20 uF compensation capacitors; Frequency is 2300 Hz; Transmitter on ESJ; Receiver on ESJ
Length
TC
(m)
600
700
800
900
1000
1100

KEM

3.5
3.5
3.5
3.5
3.5
3.5

TRANSMITTER
UTR (V)
ltr (mA)
V Output
average
min
Max
45
51
176
45
51
176
45
51
173
45
51
174
45
51
175
45
51
175

TRANSMISSION
UVT (V)
UVR (V)
V Output
Track V RxEnd
min
Max
min
Max
2.03
2.92
0.96
2.27
1.99
2.63
0.85
2.15
2.00
2.74
0.75
1.91
2.03
2.94
0.67
1.89
2.02
2.84
0.60
1.96
2.00
2.66
0.53
1.82

UV1V2(V)
V @ V1 + U2
min
Max
1.06
2.50
0.94
2.36
0.82
2.10
0.73
2.08
0.66
2.15
0.58
2.00

RECEIVER
KRV

14
15
17
19
22
24

UR1R2 (V)
V @ R1 + R2
min
Max
0.25
0.61
0.24
0.61
0.24
0.62
0.24
0.68
0.25
0.82
0.24
0.83

NOTE: This document is controlled only when viewed on the DOT Engineering Standards website. Any other copy of this document is uncontrolled, and the content may be
inaccurate.

VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

43

Configuration: End-fed track circuit with no compensation; Frequency is 2600 Hz; Transmitter on ESJ; Receiver on ESJ

Length
TC
(m)
100
125
150
175
200
225
250
275
300
325
350
375

KEM

4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25

TRANSMITTER
UTR (V)
ltr (mA)
V Output
average
min
Max
54
61
160
54
61
156
54
61
154
54
61
152
54
61
150
54
61
149
54
61
149
54
61
149
54
61
149
54
61
149
54
62
149
54
62
149

400
425
450
475
500
525
550
575
600
625
650

4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25

54
54
54
54
54
54
54
54
54
54
54

62
62
62
62
62
62
62
62
62
62
62

149
149
150
150
150
150
151
151
151
151
151

TRANSMISSION
UVT (V)
UVR (V)
V Output
Track V RxEnd
min
Max
min
Max
2.35
3.28
1.26
2.21
2.41
3.37
1.13
2.01
2.46
3.46
1.02
1.84
2.50
3.53
0.92
1.69
2.54
3.60
0.83
1.57
2.57
3.66
0.76
1.46
2.60
3.71
0.70
1.36
2.62
3.75
0.64
1.28
2.64
3.79
0.59
1.20
2.65
3.83
0.54
1.14
2.66
3.86
0.50
1.08
2.67
3.89
0.47
1.02

UV1V2(V)
V @ V1 + U2
min
Max
1.39
2.43
1.24
2.21
1.12
2.02
1.01
1.86
0.92
1.72
0.84
1.60
0.77
1.50
0.70
1.40
0.65
1.32
0.60
1.25
0.55
1.19
0.51
1.13

2.68
2.68
2.68
2.69
2.69
2.69
2.69
2.69
2.69
2.69
2.69

0.48
0.44
0.41
0.39
0.36
0.33
0.31
0.29
0.27
0.25
0.24

3.91
3.94
3.96
3.98
3.99
4.01
4.03
4.04
4.05
4.07
4.08

0.43
0.40
0.38
0.35
0.33
0.30
0.28
0.26
0.25
0.24
0.21

0.98
0.93
0.89
0.86
0.83
0.80
0.77
0.74
0.72
0.70
0.68

1.07
1.03
0.98
0.94
0.91
0.87
0.84
0.82
0.79
0.77
0.74

RECEIVER
KRV

11
12
13
14
16
17
19
20
22
24
25
27

UR1R2 (V)
V @ R1 + R2
min
Max
0.26
0.46
0.25
0.46
0.25
0.46
0.24
0.45
0.25
0.48
0.24
0.47
0.25
0.49
0.24
0.49
0.24
0.50
0.25
0.52
0.24
0.51
0.24
0.53

29
31
34
36
39
41
44
48
51
54
58

0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24

0.54
0.55
0.58
0.59
0.61
0.62
0.64
0.68
0.70
0.71
0.74

NOTE: This document is controlled only when viewed on the DOT Engineering Standards website. Any other copy of this document is uncontrolled, and the content may be
inaccurate.

VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

44

Configuration: End-fed track circuit with 20 uF compensation capacitors; Frequency is 2600 Hz; Transmitter on ESJ; Receiver on ESJ
Length
TC
(m)
600
700
800
900
1000
1100

KEM

3.75
3.75
3.75
3.75
3.75
3.75

TRANSMITTER
UTR (V)
V Output
min
Max
48
54
48
54
48
54
48
54
48
54
48
54

ltr (mA)
average
175
172
174
175
173
174

TRANSMISSION
UVT (V)
UVR (V)
V Output
Track V RxEnd
min
Max
min
Max
2.01
2.67
0.99
2.27
2.04
2.81
0.86
2.04
2.06
2.98
0.77
2.05
2.03
2.77
0.69
2.03
2.03
2.75
0.60
1.84
2.05
2.93
0.53
1.78

UV1V2(V)
V @ V1 + U2
min
Max
1.09
2.50
0.95
2.24
0.85
2.26
0.76
2.24
0.66
2.03
0.59
1.96

RECEIVER
KRV

13
15
17
19
21
24

UR1R2 (V)
V @ R1 + R2
min
Max
0.24
0.56
0.24
0.58
0.25
0.67
0.24
0.74
0.24
0.74
0.24
0.81

NOTE: This document is controlled only when viewed on the DOT Engineering Standards website. Any other copy of this document is uncontrolled, and the content may be
inaccurate.

VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

45

Configuration: End-fed track circuit with no compensation; Frequency is 1700 Hz; Transmitter on ESJ; Receiver on IRJ

3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5

TRANSMITTER
UTR (V)
ltr (mA)
V Output
average
min
Max
45
51
181
45
51
180
45
51
178
45
51
177
45
51
177
45
51
176
45
51
175
45
51
175
45
51
175
45
51
174
45
51
174
45
51
174

TRANSMISSION
UVT (V)
UVR (V)
V Output
Track V RxEnd
min
Max
min
Max
2.23
3.11
1.54
2.66
2.24
3.13
1.44
2.52
2.24
3.16
1.35
2.39
2.25
3.18
1.26
2.27
2.26
3.20
1.18
2.16
2.27
3.22
1.10
2.06
2.27
3.24
1.03
1.97
2.28
3.26
0.97
1.88
2.28
3.28
0.91
1.80
2.29
3.29
0.85
1.73
2.29
3.31
0.80
1.66
2.30
3.32
0.75
1.60

UV1V2(V)
V @ V1 + U2
min
Max
1.46
2.52
1.37
2.39
1.28
2.27
1.20
2.15
1.12
2.05
1.05
1.95
0.98
1.87
0.92
1.78
0.86
1.71
0.81
1.64
0.76
1.58
0.71
1.52

3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5

45
45
45
45
45
45
45
45
45
45
45

2.30
2.30
2.30
2.31
2.31
2.31
2.31
2.31
2.31
2.31
2.31

0.67
0.63
0.60
0.56
0.53
0.50
0.47
0.44
0.42
0.39
0.37

Length
TC
(m)
100
125
150
175
200
225
250
275
300
325
350
375

KEM

400
425
450
475
500
525
550
575
600
625
650

51
51
51
51
51
51
51
51
51
51
51

174
174
174
174
174
174
174
174
174
174
174

3.34
3.35
3.36
3.37
3.38
3.39
3.40
3.41
3.41
3.42
3.43

0.71
0.67
0.63
0.59
0.56
0.52
0.49
0.47
0.41
0.41
0.39

1.54
1.49
1.44
1.39
1.34
1.30
1.26
1.23
1.19
1.16
1.13

1.46
1.41
1.36
1.32
1.28
1.24
1.20
1.16
1.13
1.10
1.07

RECEIVER
KRV

10
11
11
12
13
14
15
16
17
18
19
20

UR1R2 (V)
V @ R1 + R2
min
Max
0.25
0.44
0.26
0.46
0.24
0.43
0.24
0.45
0.25
0.46
0.25
0.48
0.25
0.49
0.25
0.50
0.25
0.50
0.25
0.51
0.25
0.52
0.24
0.53

21
22
24
25
27
28
30
32
34
35
38

0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24

0.53
0.54
0.57
0.57
0.60
0.60
0.62
0.64
0.67
0.67
0.70

NOTE: This document is controlled only when viewed on the DOT Engineering Standards website. Any other copy of this document is uncontrolled, and the content may be
inaccurate.

VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

46

Configuration: End-fed track circuit with 35 uF compensation capacitors; Frequency is 1700 Hz; Transmitter on ESJ; Receiver on IRJ
Length
TC
(m)
600
700
800
900
1000
1100

KEM

3
3
3
3
3
3

TRANSMITTER
UTR (V)
ltr (mA)
V Output
average
min
Max
39
44
203
39
44
197
39
44
186
39
44
189
39
44
196
39
44
195

TRANSMISSION
UVT (V)
UVR (V)
V Output
Track V RxEnd
min
Max
min
Max
1.81
2.68
1.36
3.13
1.69
2.09
1.17
2.76
1.77
2.39
1.00
2.19
1.85
2.72
0.91
2.18
1.81
2.69
0.86
2.52
1.75
2.22
0.77
2.42

UV1V2(V)
V @ V1 + U2
min
Max
1.29
2.97
1.11
2.61
0.94
2.08
0.87
2.07
0.82
2.39
0.73
2.30

RECEIVER
KRV

11
13
15
16
17
19

UR1R2 (V)
V @ R1 + R2
min
Max
0.24
0.57
0.25
0.59
0.24
0.54
0.24
0.57
0.24
0.70
0.24
0.76

NOTE: This document is controlled only when viewed on the DOT Engineering Standards website. Any other copy of this document is uncontrolled, and the content may be
inaccurate.

VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

47

Configuration: End-fed track circuit with no compensation; Frequency is 2000 Hz; Transmitter on ESJ; Receiver on IRJ

Length
TC
(m)
100
125
150
175
200
225
250
275
300
325
350
375

KEM

3.75
3.75
3.75
3.75
3.75
3.75
3.75
3.75
3.75
3.75
3.75
3.75

TRANSMITTER
UTR (V)
ltr (mA)
V Output
average
min
Max
48
55
169
48
55
168
48
55
167
48
55
166
48
55
165
48
55
164
48
55
164
48
55
164
48
55
163
48
55
163
48
55
163
48
55
163

400
425
450
475
500
525
550
575
600
625
650

3.75
3.75
3.75
3.75
3.75
3.75
3.75
3.75
3.75
3.75
3.75

48
48
48
48
48
48
48
48
48
48
48

55
55
55
55
55
55
55
55
55
55
55

163
163
163
163
163
163
163
163
163
163
163

TRANSMISSION
UVT (V)
UVR (V)
V Output
Track V RxEnd
min
Max
min
Max
2.36
3.29
1.58
2.75
2.36
3.32
1.47
2.59
2.37
3.35
1.37
2.45
2.38
3.38
1.27
2.32
2.39
3.41
1.19
2.20
2.40
3.43
1.11
2.09
2.41
3.46
1.03
2.00
2.41
3.48
0.96
1.91
2.42
3.50
0.90
1.82
2.42
3.52
0.84
1.75
2.43
3.53
0.79
1.68
2.43
3.55
0.74
1.61

UV1V2(V)
V @ V1 + U2
min
Max
1.51
2.61
1.40
2.46
1.30
2.33
1.21
2.21
1.13
2.09
1.05
1.99
0.98
1.90
0.92
1.81
0.86
1.73
0.80
1.66
0.75
1.59
0.70
1.53

2.44
2.44
2.44
2.44
2.45
2.45
2.45
2.45
2.45
2.45
2.45

0.66
0.62
0.58
0.54
0.51
0.48
0.45
0.42
0.39
0.37
0.35

3.57
3.58
3.59
3.60
3.62
3.63
3.64
3.65
3.65
3.66
3.67

0.69
0.65
0.61
0.57
0.53
0.50
0.47
0.44
0.42
0.39
0.37

1.55
1.50
1.44
1.40
1.35
1.31
1.27
1.23
1.20
1.17
1.14

1.48
1.42
1.37
1.33
1.28
1.24
1.21
1.17
1.14
1.11
1.08

RECEIVER
KRV

10
10
11
12
13
14
15
16
17
18
19
20

UR1R2 (V)
V @ R1 + R2
min
Max
0.26
0.45
0.24
0.43
0.24
0.45
0.25
0.46
0.25
0.47
0.25
0.48
0.25
0.49
0.25
0.50
0.25
0.51
0.24
0.52
0.24
0.53
0.24
0.53

22
23
24
26
28
29
31
33
35
38
40

0.25
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24

0.56
0.57
0.57
0.60
0.62
0.62
0.65
0.67
0.69
0.73
0.75

NOTE: This document is controlled only when viewed on the DOT Engineering Standards website. Any other copy of this document is uncontrolled, and the content may be
inaccurate.

VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

48

Configuration: End-fed track circuit with 35 uF compensation capacitors; Frequency is 2000 Hz; Transmitter on ESJ; Receiver on IRJ

Length
TC
(m)
600
700
800
900
1000
1100

KEM

3.25
3.25
3.25
3.25
3.25
3.25

TRANSMITTER
UTR (V)
ltr (mA)
V Output
average
min
Max
42
47
190
42
47
179
42
47
189
42
47
194
42
47
185
42
47
185

TRANSMISSION
UVT (V)
UVR (V)
V Output
Track V RxEnd
min
Max
min
Max
1.70
2.06
1.33
2.79
1.88
2.62
1.13
2.29
1.94
2.97
1.08
2.59
1.8
2.35
0.99
2.75
1.81
2.33
0.85
2.17
1.89
2.78
0.76
2.08

UV1V2(V)
V @ V1 + U2
min
Max
1.27
2.65
1.07
2.18
1.03
2.46
0.94
2.61
0.80
2.06
0.72
1.97

RECEIVER
KRV

11
13
14
15
18
20

UR1R2 (V)
V @ R1 + R2
min
Max
0.24
0.51
0.24
0.49
0.24
0.60
0.24
0.68
0.25
0.64
0.25
0.68

NOTE: This document is controlled only when viewed on the DOT Engineering Standards website. Any other copy of this document is uncontrolled, and the content may be
inaccurate.

VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

49

Configuration: End-fed track circuit with no compensation; Frequency is 2300 Hz; Transmitter on ESJ; Receiver on IRJ

Length
TC
(m)
100
125
150
175
200
225
250
275
300
325
350
375

KEM

4
4
4
4
4
4
4
4
4
4
4
4

TRANSMITTER
UTR (V)
ltr (mA)
V Output
average
min
Max
51
58
161
51
58
160
51
58
158
51
58
157
51
58
156
51
58
155
51
58
155
51
58
154
51
58
154
51
58
154
51
58
154
51
58
154

400
425
450
475
500
525
550
575
600
625
650

4
4
4
4
4
4
4
4
4
4
4

51
51
51
51
51
51
51
51
51
51
51

58
58
58
58
58
58
58
58
58
58
58

154
154
154
154
154
154
154
155
155
155
155

TRANSMISSION
UVT (V)
UVR (V)
V Output
Track V RxEnd
min
Max
min
Max
2.43
3.4
1.55
2.70
2.44
3.44
1.43
2.52
2.46
3.48
1.31
2.37
2.48
3.52
1.21
2.23
2.49
3.56
1.12
2.10
2.51
3.59
1.03
1.99
2.52
3.62
0.96
1.88
2.53
3.65
0.89
1.79
2.54
3.68
0.83
1.70
2.55
3.70
0.77
1.63
2.55
3.72
0.72
1.56
2.56
3.74
0.67
1.49

UV1V2(V)
V @ V1 + U2
min
Max
1.47
2.57
1.36
2.40
1.25
2.25
1.15
2.12
1.06
2.00
0.98
1.89
0.91
1.79
0.85
1.70
0.79
1.62
0.73
1.55
0.68
1.48
0.64
1.42

2.56
2.57
2.57
2.57
2.57
2.57
2.57
2.57
2.57
2.57
2.57

0.59
0.55
0.52
0.48
0.45
0.42
0.39
0.37
0.35
0.32
0.30

3.76
3.78
3.79
3.81
3.82
3.83
3.85
3.86
3.87
3.88
3.89

0.62
0.58
0.54
0.51
0.47
0.44
0.42
0.39
0.36
0.34
0.32

1.43
1.38
1.33
1.28
1.24
1.20
1.16
1.12
1.09
1.06
1.03

1.36
1.31
1.26
1.22
1.18
1.14
1.10
1.07
1.04
1.01
0.98

RECEIVER
KRV

10
11
12
13
14
15
16
17
18
19
21
22

UR1R2 (V)
V @ R1 + R2
min
Max
0.25
0.45
0.25
0.46
0.25
0.47
0.25
0.48
0.25
0.49
0.25
0.49
0.25
0.50
0.24
0.50
0.24
0.51
0.24
0.51
0.24
0.54
0.24
0.54

24
25
27
29
31
33
35
38
40
43
46

0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24

0.57
0.57
0.59
0.61
0.63
0.65
0.67
0.70
0.72
0.75
0.78

NOTE: This document is controlled only when viewed on the DOT Engineering Standards website. Any other copy of this document is uncontrolled, and the content may be
inaccurate.

VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

50

Configuration: End-fed track circuit with 20 uF compensation capacitors; Frequency is 2300 Hz; Transmitter on ESJ; Receiver on IRJ

Length
TC
(m)
600
700
800
900
1000
1100

KEM

3.5
3.5
3.5
3.5
3.5
3.5

TRANSMITTER
UTR (V)
ltr (mA)
V Output
average
min
Max
45
50
180
45
51
172
45
51
171
45
51
177
45
51
176
45
51
173

TRANSMISSION
UVT (V)
UVR (V)
V Output
Track V RxEnd
min
Max
min
Max
1.95
2.58
1.27
3.16
1.96
2.54
1.07
2.52
2.06
2.98
0.94
2.35
2.04
3.07
0.87
2.65
1.98
2.56
0.77
2.59
2.00
2.66
0.67
2.17

UV1V2(V)
V @ V1 + U2
min
Max
1.21
3.01
1.01
2.40
0.90
2.24
0.83
2.52
0.73
2.47
0.64
2.06

RECEIVER
KRV

12
14
16
17
19
22

UR1R2 (V)
V @ R1 + R2
min
Max
0.25
0.63
0.24
0.58
0.24
0.62
0.24
0.74
0.24
0.81
0.24
0.79

NOTE: This document is controlled only when viewed on the DOT Engineering Standards website. Any other copy of this document is uncontrolled, and the content may be
inaccurate.

VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

51

Configuration: End-fed track circuit with no compensation; Frequency is 2600 Hz; Transmitter on ESJ; Receiver on IRJ

Length
TC
(m)
100
125
150
175
200
225
250
275
300
325
350
375

KEM

4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25

TRANSMITTER
UTR (V)
ltr (mA)
V Output
average
min
Max
54
61
158
54
61
156
54
61
155
54
61
154
54
61
153
54
61
152
54
61
151
54
61
151
54
61
151
54
62
151
54
62
151
54
62
151

400
425
450
475
500
525
550
575
600
625
650

4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25

54
54
54
54
54
54
54
54
54
54
54

62
62
62
62
62
62
62
62
62
62
62

151
151
151
151
151
151
151
151
151
151
152

TRANSMISSION
UVT (V)
UVR (V)
V Output
Track V RxEnd
min
Max
min
Max
2.53
3.56
1.64
2.87
2.54
3.61
1.50
2.69
2.56
3.65
1.38
2.52
2.58
3.69
1.27
2.38
2.59
3.73
1.17
2.24
2.61
3.77
1.08
2.12
2.62
3.80
1.00
2.01
2.63
3.83
0.92
1.91
2.64
3.86
0.85
1.82
2.65
3.89
0.79
1.73
2.66
3.91
0.73
1.66
2.66
3.93
0.68
1.59

UV1V2(V)
V @ V1 + U2
min
Max
1.56
2.74
1.43
2.57
1.32
2.41
1.21
2.27
1.12
2.14
1.03
2.02
0.95
1.92
0.88
1.82
0.81
1.73
0.75
1.65
0.70
1.58
0.65
1.52

2.67
2.67
2.67
2.68
2.68
2.68
2.68
2.68
2.68
2.68
2.68

0.60
0.56
0.52
0.49
0.45
0.42
0.39
0.37
0.34
0.32
0.30

3.95
3.97
3.99
4.00
4.02
4.03
4.05
4.06
4.07
4.08
4.09

0.63
0.59
0.55
0.51
0.48
0.44
0.41
0.39
0.36
0.33
0.31

1.53
1.47
1.41
1.37
1.32
1.28
1.24
1.20
1.17
1.14
1.11

1.46
1.40
1.35
1.30
1.26
1.22
1.18
1.15
1.11
1.08
1.06

RECEIVER
KRV

9
10
11
12
13
14
15
16
18
19
20
22

UR1R2 (V)
V @ R1 + R2
min
Max
0.24
0.43
0.24
0.45
0.25
0.46
0.25
0.47
0.25
0.48
0.24
0.49
0.24
0.50
0.24
0.51
0.25
0.54
0.24
0.55
0.24
0.55
0.24
0.58

23
25
27
29
31
33
35
38
41
43
47

0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24

0.58
0.61
0.63
0.65
0.68
0.70
0.72
0.75
0.79
0.80
0.86

NOTE: This document is controlled only when viewed on the DOT Engineering Standards website. Any other copy of this document is uncontrolled, and the content may be
inaccurate.

VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

52

Configuration: End-fed track circuit with 20 uF compensation capacitors; Frequency is 2600 Hz; Transmitter on ESJ; Receiver on IRJ
Length
TC
(m)
600
700
800
900
1000
1100

KEM

3.75
3.75
3.75
3.75
3.75
3.75

TRANSMITTER
UTR (V)
ltr (mA)
V Output
average
min
Max
48
54
170
48
54
170
48
54
178
48
54
174
48
54
171
48
54
175

TRANSMISSION
UVT (V)
UVR (V)
V Output
Track V RxEnd
min
Max
min
Max
1.97
2.52
1.24
2.68
2.12
3.11
1.10
2.54
2.06
3.03
1.02
2.92
1.99
2.48
0.88
2.56
2.06
2.91
0.77
2.23
2.07
3.11
0.70
2.42

UV1V2(V)
V @ V1 + U2
min
Max
1.18
2.56
1.05
2.42
0.97
2.78
0.84
2.44
0.73
2.13
0.66
2.31

RECEIVER
KRV

12
14
15
17
19
21

UR1R2 (V)
V @ R1 + R2
min
Max
0.24
0.53
0.25
0.59
0.25
0.72
0.24
0.72
0.24
0.70
0.24
0.84

NOTE: This document is controlled only when viewed on the DOT Engineering Standards website. Any other copy of this document is uncontrolled, and the content may be
inaccurate.

VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

53

Configuration: End-fed track circuit with no compensation; Frequency is 1700 Hz; Transmitter on IRJ; Receiver on ESJ

Length
TC
(m)
100
125
150
175
200
225
250
275
300
325
350
375

KEM

3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5

TRANSMITTER
UTR (V)
ltr (mA)
V Output
average
min
Max
45
51
172
45
51
165
45
51
160
45
51
156
45
51
152
45
51
149
45
51
147
45
51
145
45
51
143
45
51
142
45
51
141
45
51
141

400
425
450
475
500
525
550
575
600
625
650

3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5

45
45
45
45
46
46
46
46
46
46
46

51
51
52
52
52
52
52
52
52
52
52

140
140
140
140
140
140
140
140
140
140
141

TRANSMISSION
UVT (V)
UVR (V)
V Output
Track V RxEnd
min
Max
min
Max
2.29
3.19
1.29
2.23
2.35
3.29
1.17
2.05
2.41
3.38
1.07
1.89
2.46
3.46
0.98
1.76
2.51
3.53
0.90
1.64
2.55
3.60
0.83
1.53
2.58
3.66
0.77
1.44
2.61
3.71
0.71
1.36
2.64
3.76
0.66
1.28
2.66
3.80
0.62
1.21
2.68
3.84
0.58
1.15
2.70
3.88
0.54
1.10

UV1V2(V)
V @ V1 + U2
min
Max
1.41
2.44
1.28
2.24
1.17
2.07
1.07
1.92
0.98
1.79
0.91
1.67
0.84
1.57
0.78
1.48
0.72
1.40
0.68
1.33
0.63
1.26
0.59
1.20

2.71
2.72
2.73
2.74
2.75
2.75
2.75
2.76
2.76
2.76
2.76

0.55
0.52
0.49
0.46
0.43
0.41
0.38
0.36
0.34
0.32
0.31

3.91
3.94
3.97
3.99
4.02
4.04
4.06
4.08
4.10
4.11
4.13

0.51
0.48
0.45
0.42
0.40
0.37
0.35
0.33
0.31
0.30
0.28

1.05
1.01
0.96
0.93
0.89
0.86
0.83
0.80
0.78
0.75
0.73

1.15
1.10
1.05
1.01
0.97
0.94
0.91
0.88
0.85
0.82
0.80

RECEIVER
KRV

10
11
12
13
15
16
17
18
20
21
22
24

UR1R2 (V)
V @ R1 + R2
min
Max
0.24
0.42
0.24
0.43
0.24
0.43
0.24
0.43
0.25
0.47
0.25
0.46
0.24
0.46
0.24
0.46
0.25
0.49
0.24
0.48
0.24
0.48
0.24
0.50

25
27
29
30
32
34
36
38
41
43
45

0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24

0.50
0.51
0.53
0.53
0.54
0.55
0.56
0.58
0.60
0.61
0.62

NOTE: This document is controlled only when viewed on the DOT Engineering Standards website. Any other copy of this document is uncontrolled, and the content may be
inaccurate.

VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

54

Configuration: End-fed track circuit with 35 uF compensation capacitors; Frequency is 1700 Hz; Transmitter on IRJ; Receiver on ESJ

Length
TC
(m)
600
700
800
900
1000
1100

KEM

3
3
3
3
3
3

TRANSMITTER
UTR (V)
ltr (mA)
V Output
average
min
Max
39
44
177
39
44
184
39
44
183
39
44
178
39
44
179
39
44
181

TRANSMISSION
UVT (V)
UVR (V)
V Output
Track V RxEnd
min
Max
min
Max
2.15
3.18
1.04
2.18
2.11
2.99
0.96
2.26
2.05
2.68
0.85
2.03
2.07
2.85
0.75
1.84
2.11
3.09
0.68
1.85
2.10
3.02
0.62
1.91

UV1V2(V)
V @ V1 + U2
min
Max
1.13
2.38
1.04
2.46
0.93
2.22
0.82
2.01
0.75
2.02
0.68
2.08

RECEIVER
KRV

13
14
15
17
19
21

UR1R2 (V)
V @ R1 + R2
min
Max
0.25
0.54
0.25
0.60
0.24
0.58
0.24
0.59
0.24
0.67
0.24
0.76

NOTE: This document is controlled only when viewed on the DOT Engineering Standards website. Any other copy of this document is uncontrolled, and the content may be
inaccurate.

VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

55

Configuration: End-fed track circuit with no compensation; Frequency is 2000 Hz; Transmitter on IRJ; Receiver on ESJ

3.75
3.75
3.75
3.75
3.75
3.75
3.75
3.75
3.75
3.75
3.75
3.75

TRANSMITTER
UTR (V)
ltr (mA)
V Output
average
min
Max
48
55
162
48
55
156
48
55
152
48
55
148
48
55
145
48
55
142
48
55
140
48
55
139
48
55
138
48
55
137
48
55
136
48
55
136

TRANSMISSION
UVT (V)
UVR (V)
V Output
Track V RxEnd
min
Max
min
Max
2.39
3.34
1.33
2.32
2.46
3.45
1.21
2.13
2.52
3.54
1.10
1.96
2.57
3.63
1.00
1.82
2.62
3.71
0.92
1.70
2.66
3.78
0.85
1.59
2.69
3.84
0.78
1.49
2.72
3.90
0.72
1.40
2.75
3.95
0.67
1.33
2.77
3.99
0.62
1.26
2.79
4.03
0.58
1.19
2.81
4.07
0.54
1.14

UV1V2(V)
V @ V1 + U2
min
Max
1.46
2.54
1.32
2.33
1.20
2.15
1.10
1.99
1.01
1.86
0.93
1.74
0.86
1.63
0.79
1.54
0.74
1.45
0.68
1.38
0.64
1.31
0.60
1.25

3.75
3.75
3.75
3.75
3.75
3.75
3.75
3.75
3.75
3.75
3.75

49
49
49
49
49
49
49
49
49
49
49

2.82
2.83
2.84
2.85
2.85
2.86
2.86
2.86
2.86
2.86
2.86

0.56
0.52
0.49
0.46
0.43
0.40
0.38
0.36
0.34
0.32
0.30

Length
TC
(m)
100
125
150
175
200
225
250
275
300
325
350
375

KEM

400
425
450
475
500
525
550
575
600
625
650

55
55
55
55
55
55
55
55
55
55
55

135
135
135
135
135
136
136
136
136
136
137

4.11
4.14
4.17
4.20
4.22
4.24
4.27
4.29
4.30
4.32
4.34

0.51
0.48
0.45
0.42
0.39
0.37
0.35
0.32
0.31
0.29
0.27

1.09
1.04
1.00
0.96
0.92
0.89
0.86
0.83
0.80
0.78
0.76

1.19
1.14
1.09
1.05
1.01
0.98
0.94
0.91
0.88
0.85
0.83

RECEIVER
KRV

10
11
12
13
14
15
17
18
19
21
22
24

UR1R2 (V)
V @ R1 + R2
min
Max
0.25
0.41
0.25
0.45
0.24
0.45
0.24
0.45
0.24
0.45
0.24
0.45
0.25
0.48
0.24
0.48
0.24
0.48
0.24
0.50
0.24
0.50
0.24
0.52

25
27
29
31
33
35
37
39
41
44
47

0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24

0.52
0.53
0.55
0.56
0.58
0.59
0.60
0.61
0.62
0.65
0.67

NOTE: This document is controlled only when viewed on the DOT Engineering Standards website. Any other copy of this document is uncontrolled, and the content may be
inaccurate.

VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

56

Configuration: End-fed track circuit with 35 uF compensation capacitors; Frequency is 2000 Hz; Transmitter on IRJ; Receiver on ESJ
Length
TC
(m)
600
700
800
900
1000
1100

KEM

3.25
3.25
3.25
3.25
3.25
3.25

TRANSMITTER
UTR (V)
ltr (mA)
V Output
average
min
Max
42
47
184
42
47
179
42
47
178
42
47
182
42
47
181
42
47
179

TRANSMISSION
UVT (V)
UVR (V)
V Output
Track V RxEnd
min
Max
min
Max
2.06
2.79
1.12
2.40
2.06
2.75
0.98
2.11
2.13
3.07
0.89
2.08
2.11
3.01
0.81
2.13
2.07
2.74
0.72
1.95
2.09
2.90
0.64
1.80

UV1V2(V)
V @ V1 + U2
min
Max
1.23
2.63
1.08
2.31
0.97
2.28
0.89
2.34
0.79
2.14
0.70
1.98

RECEIVER
KRV

12
13
15
16
18
20

UR1R2 (V)
V @ R1 + R2
min
Max
0.25
0.55
0.24
0.52
0.25
0.59
0.24
0.65
0.24
0.67
0.24
0.69

NOTE: This document is controlled only when viewed on the DOT Engineering Standards website. Any other copy of this document is uncontrolled, and the content may be
inaccurate.

VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

57

Configuration: End-fed track circuit with no compensation; Frequency is 2300 Hz; Transmitter on IRJ; Receiver on ESJ

4
4
4
4
4
4
4
4
4
4
4
4

TRANSMITTER
UTR (V)
ltr (mA)
V Output
average
min
Max
51
58
160
51
58
155
51
58
151
51
58
148
51
58
145
51
58
143
52
58
142
52
58
141
52
58
140
52
58
140
52
58
140
52
58
139

TRANSMISSION
UVT (V)
UVR (V)
V Output
Track V RxEnd
min
Max
min
Max
2.44
3.42
1.34
2.34
2.51
3.53
1.21
2.15
2.57
3.63
1.10
1.98
2.62
3.72
1.00
1.84
2.67
3.80
0.91
1.71
2.71
3.87
0.84
1.60
2.74
3.93
0.77
1.50
2.77
3.99
0.71
1.41
2.80
4.04
0.66
1.34
2.82
4.09
0.61
1.27
2.83
4.13
0.57
1.20
2.85
4.17
0.53
1.15

UV1V2(V)
V @ V1 + U2
min
Max
1.47
2.57
1.33
2.36
1.20
2.17
1.10
2.02
1.00
1.88
0.92
1.75
0.85
1.65
0.78
1.55
0.73
1.47
0.67
1.39
0.63
1.32
0.58
1.26

4
4
4
4
4
4
4
4
4
4
4

52
52
52
52
52
52
52
52
52
52
52

2.86
2.87
2.88
2.88
2.88
2.89
2.89
2.89
2.89
2.89
2.89

0.54
0.51
0.47
0.44
0.41
0.39
0.36
0.34
0.32
0.30
0.28

Length
TC
(m)
100
125
150
175
200
225
250
275
300
325
350
375

KEM

400
425
450
475
500
525
550
575
600
625
650

58
58
58
58
58
58
58
58
58
58
58

139
139
140
140
140
140
140
141
141
141
141

4.21
4.24
4.27
4.30
4.32
4.34
4.37
4.39
4.40
4.42
4.44

0.49
0.46
0.43
0.40
0.38
0.35
0.33
0.31
0.29
0.27
0.25

1.10
1.05
1.01
0.97
0.93
0.90
0.87
0.84
0.81
0.79
0.77

1.20
1.15
1.10
1.06
1.02
0.99
0.95
0.92
0.89
0.87
0.84

RECEIVER
KRV

10
11
12
13
14
16
17
18
20
21
23
24

UR1R2 (V)
V @ R1 + R2
min
Max
0.25
0.45
0.25
0.45
0.25
0.45
0.24
0.46
0.24
0.46
0.25
0.49
0.25
0.49
0.24
0.48
0.25
0.51
0.24
0.51
0.25
0.53
0.24
0.52

26
28
30
32
34
36
38
41
44
46
50

0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24

0.54
0.56
0.57
0.59
0.60
0.61
0.63
0.65
0.68
0.69
0.73

NOTE: This document is controlled only when viewed on the DOT Engineering Standards website. Any other copy of this document is uncontrolled, and the content may be
inaccurate.

VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

58

Configuration: End-fed track circuit with 20 uF compensation capacitors; Frequency is 2300 Hz; Transmitter on IRJ; Receiver on ESJ
Length
TC
(m)
600
700
800
900
1000
1100

KEM

3.5
3.5
3.5
3.5
3.5
3.5

TRANSMITTER
UTR (V)
ltr (mA)
V Output
average
min
Max
45
51
173
45
51
173
45
51
170
45
51
171
45
51
173
45
51
172

TRANSMISSION
UVT (V)
UVR (V)
V Output
Track V RxEnd
min
Max
min
Max
2.23
3.25
1.06
2.53
2.17
2.84
0.93
2.33
2.19
3.00
0.82
2.09
2.23
3.28
0.73
2.11
2.21
3.14
0.65
2.16
2.19
2.89
0.58
1.98

UV1V2(V)
V @ V1 + U2
min
Max
1.16
2.78
1.02
2.56
0.90
2.30
0.80
2.32
0.72
2.38
0.64
2.17

RECEIVER
KRV

12
14
16
18
20
22

UR1R2 (V)
V @ R1 + R2
min
Max
0.24
0.58
0.24
0.62
0.24
0.64
0.25
0.72
0.24
0.82
0.24
0.83

NOTE: This document is controlled only when viewed on the DOT Engineering Standards website. Any other copy of this document is uncontrolled, and the content may be
inaccurate.

VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

59

Configuration: End-fed track circuit with no compensation; Frequency is 2600 Hz; Transmitter on IRJ; Receiver on ESJ

4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25

TRANSMITTER
UTR (V)
ltr (mA)
V Output
average
min
Max
54
61
152
54
61
147
54
61
143
54
61
140
55
61
138
55
62
137
55
62
135
55
62
135
55
62
134
55
62
134
55
62
134
55
62
134

TRANSMISSION
UVT (V)
UVR (V)
V Output
Track V RxEnd
min
Max
min
Max
2.57
3.61
1.38
2.43
2.65
3.74
1.24
2.23
2.72
3.86
1.12
2.05
2.78
3.96
1.02
1.90
2.83
4.06
0.93
1.76
2.88
4.14
0.85
1.65
2.92
4.21
0.78
1.55
2.95
4.28
0.72
1.46
2.98
4.34
0.67
1.38
3.00
4.39
0.62
1.30
3.02
4.44
0.57
1.24
3.03
4.48
0.53
1.18

UV1V2(V)
V @ V1 + U2
min
Max
1.52
2.67
1.37
2.45
1.24
2.25
1.12
2.09
1.03
1.94
0.94
1.81
0.86
1.70
0.79
1.60
0.73
1.51
0.68
1.43
0.63
1.36
0.58
1.30

4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25

55
55
55
55
55
55
55
55
55
55
55

3.04
3.05
3.06
3.06
3.06
3.07
3.07
3.07
3.06
3.06
3.06

0.54
0.51
0.47
0.44
0.41
0.38
0.36
0.33
0.31
0.29
0.27

Length
TC
(m)
100
125
150
175
200
225
250
275
300
325
350
375

KEM

400
425
450
475
500
525
550
575
600
625
650

62
62
62
62
62
62
62
62
62
62
62

134
134
134
134
135
135
135
135
136
136
136

4.52
4.56
4.59
4.63
4.65
4.68
4.71
4.73
4.75
4.77
4.79

0.49
0.46
0.43
0.40
0.37
0.35
0.32
0.30
0.28
0.26
0.24

1.13
1.08
1.04
1.00
0.96
0.93
0.90
0.87
0.84
0.82
0.79

1.24
1.19
1.14
1.10
1.06
1.02
0.99
0.95
0.92
0.90
0.87

RECEIVER
KRV

10
11
12
13
14
15
17
18
19
21
22
24

UR1R2 (V)
V @ R1 + R2
min
Max
0.26
0.47
0.26
0.47
0.25
0.47
0.25
0.47
0.24
0.47
0.24
0.47
0.25
0.50
0.24
0.50
0.24
0.50
0.24
0.52
0.24
0.52
0.24
0.54

26
28
30
32
34
36
39
42
45
48
51

0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24
0.24

0.56
0.58
0.59
0.61
0.62
0.63
0.66
0.69
0.72
0.74
0.77

NOTE: This document is controlled only when viewed on the DOT Engineering Standards website. Any other copy of this document is uncontrolled, and the content may be
inaccurate.

VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

60

Configuration: End-fed track circuit with 20 uF compensation capacitors; Frequency is 2600 Hz; Transmitter on IRJ; Receiver on ESJ
Length
TC
(m)
600
700
800
900
1000
1100

KEM

3.75
3.75
3.75
3.75
3.75
3.75

TRANSMITTER
UTR (V)
ltr (mA)
V Output
average
min
Max
48
54
173
48
54
170
48
54
171
48
54
172
48
54
171
48
54
171

TRANSMISSION
UVT (V)
UVR (V)
V Output
Track V RxEnd
min
Max
min
Max
2.21
2.91
1.09
2.47
2.25
3.11
0.95
2.26
2.28
3.35
0.85
2.31
2.24
3.05
0.76
2.24
2.24
3.02
0.66
2.02
2.26
3.28
0.59
1.99

UV1V2(V)
V @ V1 + U2
min
Max
1.2
2.72
1.05
2.48
0.94
2.54
0.83
2.46
0.73
2.23
0.65
2.19

RECEIVER
KRV

12
14
15
17
19
22

UR1R2 (V)
V @ R1 + R2
min
Max
0.24
0.57
0.25
0.60
0.24
0.66
0.24
0.73
0.24
0.73
0.24
0.83

NOTE: This document is controlled only when viewed on the DOT Engineering Standards website. Any other copy of this document is uncontrolled, and the content may be
inaccurate.

VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual


SECTION 9.0
9.1

61

Appendix B

Transmitter Adjustment Table KEM


Transmitter Connection

KEM

Cable

Connection

V4

V7

V5-V6

3.25

V1

V7

V2-V4 & V5-V6

3.50

V2

V7

V3-V4 & V5-V6

3.75

V1

V7

V3-V4 & V5-V6

V7

V8

4.25

V1

V8

V2-V7

4.50

V2

V8

V3-V7

4.75

V1

V8

V3-V7

V4

V8

V5-V7

5.25

V1

V8

V2-V4 & V5-V7

5.50

V2

V8

V3-V4 & V5-V7

5.75

V1

V8

V3-V4 & V5-V7

V6

V8

6.25

V1

V8

V2-V6

6.50

V2

V8

V3-V6

6.75

V1

V8

V3-V6

V4

V8

V5-V6

7.25

V1

V8

V2-V4 & V5-V6

7.50

V2

V8

V3-V4 & V5-V6

7.75

V1

V8

V3-V4 & V5-V6

NOTE: This document is controlled only when viewed on the DOT Engineering Standards website.
Any other copy of this document is uncontrolled, and the content may be inaccurate.

VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

9.2

62

Receiver Adjustment Tables KRV

KRV

R1
to

R2
to

Connections

KRV

R1
to

R2
to

Connections

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

R3
R5
R3
R5
R5
R4
R6
R3
R4
R3
R9
R9
R9
R9
R9
R9
R9
R9
R9
R9
R9
R9
R9
R9
R9
R9
R9
R9
R9
R9
R9
R10
R10
R10
R10
R10

R4
R4
R5
R7
R7
R7
R7
R7
R7
R7
R7
R7
R7
R7
R3
R4
R3
R5
R5
R4
R8
R3
R4
R3
R5
R5
R4
R6
R3
R4
R3
R7
R7
R7
R7
R7

R3-R6
R4-R6
R3-R6
R4-R6
R5-R6
R5-R6
R3-R8 & R5-R6
R4-R8 & R5-R6
R3-R8 & R4-R6
R6-R8
R4-R7 & R6-R8
R5-R7 & R6-R8
R5-R7 & R6-R8
R3-R8
R4-R8
R3-R8
R4-R8
R5-R8
R5-R8
R3-R6 & R7-R8
R4-R6 & R7-R8
R3-R6 & R7-R8
R7-R8
R4-R6 & R7-R8
R5-R6 & R7-R8
R5-R6 & R7-R8
R5-R6 & R3-R9
R5-R6 & R4-R9
R4-R6 & R3-R9
R6-R9
R3-R6 & R4-R9

37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73

R10
R10
R10
R10
R10
R10
R10
R10
R10
R10
R10
R10
R10
R10
R10
R10
R10
R10
R10
R10
R10
R10
R10
R10
R10
R10
R10
R10
R10
R10
R10
R10
R10
R10
R10
R10
R10

R7
R7
R5
R5
R4
R9
R3
R4
R3
R5
R5
R4
R6
R3
R4
R3
R7
R7
R7
R7
R7
R7
R7
R5
R5
R4
R8
R3
R4
R3
R5
R5
R4
R6
R3
R4
R3

R4-R6 &R5-R9
R3-R6 &R5-R9
R3-R9
R4-R9
R3-R9
R4-R9
R5-R9
R5-R9
R3-R6 & R7-R9
R4-R6 & R7-R9
R3-R6 & R7-R9
R7-R9
R4-R6 & R7-R9
R5-R6 & R7-R9
R5-R6 & R7-R9
R5-R6 & R3-R8
R5-R6 & R4-R8
R4-R6 & R3-R8
R6-R8
R3-R6 & R4-R8
R4-R6 & R5-R8
R3-R6 & R5-R8
R3-R8
R4-R8
R3-R8
R4-R8
R5-R8
R5-R8
R3-R6 & R7-R8
R4-R6 & R7-R8
R3-R6 & R7-R8
R7-R8
R4-R6 & R7-R8
R5-R6 & R7-R8
R5-R6 & R7-R8

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual


9.3

63

Electrical Separation Joint ESJ

ESJ with Dual Matching Unit

ESJ with Single Matching Units or Tuning Matching Units

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

64

ESJ Installation Plan MU/TU or TMU

ESJ Installation Plan ACI

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

65

ESJ Configuration TX / RX with Dual MU

ESJ Configuration TX / RX

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

66

ESJ Configuration RX / RX with Dual MU

ESJ Configuration RX / RX

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

9.4

67

Insulated Rail Joint IRJ

IRJ TX / RX

IRJ Installation Plan MU/TU or TMU

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

68

IRJ Configuration TX

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

69

IRJ Configuration TX with Impedance Bond

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

70

IRJ Configuration RX with Impedance Bond

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

9.5

71

Centre-fed Transmission

TX
Cable

Centre-fed Transmission

Centre-fed Transmission Installation Plan

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

72

Centre-fed Transmission Configuration

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

9.6

73

Data Collector

Data Collector

Data Collector Installation Plan

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

74

Alternative setting for 1:1.5 KMU


is V1/V2 connected to 9/12, with
10-11 jumpered at MU.

Data Collector Configuration

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

9.7

75

Pin Point Detector

Pin Point Detector

Pin Point Detector Installation Plan

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

76

Pin Point Detector Configuration with MU

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

77

Pin Point Detector Configuration with adjustable resistor

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

9.8

78

Transmitter Presentation and Coding

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

79

CODING FOR TRANSMITTER 1700Hz

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

80

CODING FOR TRANSMITTER 2000Hz

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

81

CODING FOR TRANSMITTER 2300Hz

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

82

CODING FOR TRANSMITTER 2600Hz

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

9.9

83

Receiver Presentation and Coding

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

84

CODING FOR RECEIVER 1700Hz

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

85

CODING FOR RECEIVER 2000Hz

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

86

CODING FOR RECEIVER 2300Hz

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

87

CODING FOR RECEIVER 2600Hz

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

88

9.10 Trackside Components

Air Core Inductor

Matching Unit

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

89

Tuning Unit (F1)

Tuning Unit (F2)

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

90

Note: Jumpers are prefitted across V1-1 and V2-4


Tuning Matching Unit (F1)

Note: Jumpers are prefitted across V1-1 and V2-4


Tuning Matching Unit (F2)

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

91

+/- 20mm

TU to ACI Cable

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual

92

1500 mm

9.11 CSEE Trackside Box Support Post

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual


SECTION 10.0

93

Specification for extended length TX/RX to MU cables

The underlying specification is from the RIC SPG 1016 cable used in New South
Wales. The cable is a 7/0.5mm cable of 2 core construction. For the purpose of this
Standard, the following specifications override conflicting details in the RIC SPG
1016 cable specification.
1.
2.
3.

4.

Core insulation for the pair shall be coloured Black and White.
Outer sheath shall be coloured Black.
Outer sheath shall be indelibly marked at intervals of not more than 500 mm
throughout the whole length of the cable with:
a.
Manufacturers name or identifying initials.
b.
Year of manufacture.
c.
The word RAILWAYS.
In addition cables shall be marked at 1 metre intervals on the outer sheath of
the cable with the progressive length starting from the inner end of the drum.
Length marking shall be in white numerals on a black background. Numerals
shall be 5.0 mm.

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VRIOGS 012.7.35 - CSEE (UM71) Jointless Track Circuit Application Manual


SECTION 11.0

94

Referenced Documents

1. CSEE Track Circuit notes produced by the PTC Signal School


2. CSEE Track Circuit notes produced by the PTC Signal Maintenance Test Room
3. Thiess Infraco / Bayside Trains, Installation of CSEE Pin Point detector, doc II
MS 0304-06
4. CS Transport, PTC Melbourne, Installation Manual, UM71 Track Circuit, doc
CTR/SPS/GML/95/40.323
5. CS Transport, PTC Melbourne, Adjustment Tables, UM71 Track Circuit, doc
CTR/SPS/GML/95/40.333
6. CS Transport, PTC Melbourne, Maintenance Manual, UM71 Track Circuit, doc
CTR/SPS/GML/95/40.334
7. CS Transport, PTC Mission of the 26th of April 1994, doc
CTR/DED/AGS/94/76527
8. CS Transport, Melbourne PTC, Visits of 29/03/1995 to 01/04/1995, doc
CTR/PSS/GML/95/41047
9. CSEE Transport, Australian Mission February 2002, Ref 19800T6528178-01
10. CSEE Transport, UM71 General Specification, Ref 602507 T 6513 367 X 01
11. AnsaldoSTS, Mainco UM71 Design Guideline No.1 13 July 2009
12. AnsaldoSTS, Mainco UM71 Design Guideline No.2 13 July 2009
13. AnsaldoSTS, Mainco UM71 Design Guideline No.3 14 August 2009
14. Signals Standard Drawing STD_G0059, STD_G0060 & STD_G0242
15. VRIOGS 10.7 Track Bonding, Track Circuit Connections and Traction Interfaces
16. VRIOGS 12.5 Testing & Commissioning

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