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Conventional Paper-II- 2013 Solutions :( ECE)

12V
8
R

Sol.1 (a)
6
5

7
+

R
A
2

R
12V
VCC

GND

Discharge

Trigger

Threshold

6
5

O/P

Reset

Control

2VCC 2R 24 2

16V
3R
3
2V R 24 1
VA reference CC

8V
3R
3
VB reference

Sol.1 (b)

In a PNP Transistor VEB 0.7 volt


in NPN Transistor VBE 0.7volt
Here base currents are neglected because value of is large.
12 0.7 22.6 I 0.7 12 0

22.6 22.6 I

I 1mA

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So value of I02 1mA I01

Y 0, 1, 3, 5, 6, 7, 10, 14, 15

Sol.1 (c)

CD
AB 00
00 0
01

01
0

11
0

10

11

10

Y A B C D A B C A C D

Sol.1 (d)

Character equation is s2 as k 0
2n a

Here

n k

a
2 k

Mr

1
2 1 2

r n 1 22

by solving both n 21.98 Rad/sec

by solving

Sol.1 (e)

k 483.12

a 26.45

3 108
3 1014 Hz
6
110
Stimulated emission rate

Spontaneous emission rate

1
hf
exp
1
KT

Where h 6.6 1034 j sec

T 200 273 473 K


K 1.38 1023 joule/ K
f frequency

Sol.1 (f)

1
6.6 1034 3 1014
exp

23
1.38 10 473

1
9.36 1014
exp 0.03 103

n 1.46
sin c 2

n1 1.48

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c 80.57
N.A. n12 n 2 2 0.2425

Sol.1 (g)
Middle
Valley
Lower
Valley

0.6eV

Upper
Valley
CB
0.8eV

FB

EG = 1.33eV

VB

Sol.1 (h)

Comparison of peak to valley current ratio:


In GaAs diode electron transfer process from lower valley to upper valley is very slow. It is
found that Ga As at a voltage above Threshold, current flow is due to large concentration of
es in lower valley as compared to upper valley. Due to this Low peak to valley ratio is
achieved becoz of large contribution from lower valley.
In InP e transfer takes place faster because of increase in field. This is due to coupling b/w
upper & lower valley is weaker in InP than that in GaAs. To prevent break down due to high
energy lower valley is weakly attached to middle but strongly coupled with upper valley.
Thus In P diode has large peak to valley current ratio than GaAs.
This is the adv. of In power GaAs which leads to high efficiency.
(A 5 F 1)
001010010111110001

1227618
Sol.2 (a)

For M1 :

VGS Vin Vout


VDS VDD Vout
For M1 to be saturation:
VDS VGS VT
ID1 K1 Vin Vout VT
ID2 K 2 VB VSS VT

Here

ID1 ID2

but

K1 2K 2

2 Vin Vout VT VB VSS VT


2

So

So

Vin Vout VT

Vout Vin VT

1
VB VSS VT
2

1
VB VSS VT
2

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VOV ViQ VT Vi VT
VOQ V0

Gain value will be

Av

2 VDD V0
Vi VT

Sol.2 (b)

v1 v0
R0

0 v1 SC0

(1)

v0 v 2 v1 A

v2 v0 v2

R1
R2

by (1) v1 1 SC0 R 0 v0

R
v 2 1 2 v0
R1
v1

v0
1 SC0 R 0

v2

v0 R1
R1 R 2

C0

R0
v1

v2

vo

R2
R1

R1
1

R1 R 2 1 SC0 R 0

v2 v1 v0

v 2 v1 1
S

v0
A t

1 SC0 R 0
S R1

t R1 R 2 1 S2C0 2 R 0 2
Here real part must be zero for oscillations
R1
1

2
R1 R 2 1 0 C0 2 R 0 2

Sol.2 (c) It is related with basic block diagram of open loop OPAMP and can be solved accordingly
Sol.2 (d)
Iin
vin
IL
R1

R2
vx
+
vo
ZL VL
+

R3
vx
R4

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vin v x v x v0

IL
R1
R2

(1)

v x v0 v x

R4
R3

by equation (1)

IL

v0 vx vin vx
R2

by equation (2) v0 v x

v0 v x

R1

R2

R 3 .v x
R4

R3
vx .
R 4R 2

For IL to be independence of v L

R 3vx
v
x then
R 4 R 2 R1

if

by equation (3)

IL

v x vin v x

R1 R1

IL

So Condition is
Sol.3 (a)

vin
R1
R3 R2

R 4 R1

(PS)
A B C

(NS)
A B

Q2
0
0

Q2
0
0

Q1 Q0
0
0
0
1

J2

K2

Q1
0
1

C
Q0
1
0

0
0

J1 K1 J 0

K0

0
1

0
1

1
0

0
0

1
1

0
0

0
1

0
1

1
1

0
1

1
0

1
0

1
0

0
0

0
1

0 1 1
1 1 1

Not used

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Q1 Q0
Q2
00

01

0
1

Q1 Q0
Q2
00

Q1 Q0
Q2
00

01

11

10

11

10

J2 = Q1
01

11

10

K2 = Q1
Q1 Q0
Q2
00 01

11

K1 = 1

Sol.3 (b)

Q1 Q0
Q2
00

01

11

10

11

10

J1 = Q0
Q1 Q0
Q2
00 01

10

J0 = Q1

J0

Q0

K0

Q0

K0 = 1

J0

Q0

J0

Q0

K0

Q0

K0

Q0

NS
PS x 0 x 1

a
b
c

a, 0
c, 0
a, 0

b, 0
d, 0
d, 0

d
e

e, 0
a, 0

f ,1
f ,1

f
g

g, 0
a, 0

f ,1
f ,1

Now it can be reduced further last is redundant


For Reducing State table
Let
a = 000
b = 001
c = 010
d = 011
e = 100
f = 101
This is solved problem of Morris meno. So can check their also.

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Reducing the state table:


PS
Q 2 Q1
0
0
0
0
0
1
0
1

Sol.4 (a)

NS
x0
0 0 0

x 1
0 0 1

0 1 0

Z
x0
0

x 1
0

0 1 1

0 1 1
1 0 1

0 0 0
1 0 0

0
1

Q0

0 0 0

1 0 1

1 0 0

1 0 1

G s H s

K
s 1 Ts

Im

K>0
T>0
O.L.T.F

G(0+)

1
Open loop poles s = 0, s
T

1
T

G(0 )

Real

P 0
Open loop poles at RHS if Im axis = 0
O.LTF
K
G s H s
s 1 Ts

At

G j0 H j0
At

K
90
j0 1 Tj0

G j H j

K
0 180
j 1 Tj

Rough sketches

G j H j

Possibilities

K
j1 Tj

Multiply & divide by 1 Tj

G j H j

K 1 Tj

j 1 T 22

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Separate Real & Imaginary Parts


jK
KT
G j H j

2 2
2 2
1 T 1 T
Imag

Real

For all +ve values of Real part is () ve.

At phase crossover frequency P


Imaginary part = 0
jK

0
1 T 22

Since p system is either highly stable or highly unstable

Put p in G j H j

KT
0
1

Graph or Nyquist plot not touches negative real axis


Actual Nyquist Plot
Since 1 pole at origin ;
jp H jp

It will take 1. ie clockwise encirclement from G 0 to a 0


Im
Real

G(0)

G & G are short circuit

Absolute stability
N P Z

N = No. of encirclement around 1, 0 point


P+ = No of open loop poles on RHS of Imaginer axis
Z+ = For equation zeroes or closed loop poles on RHS of Imaginer axis
Since no encirclement around (1, 0) point
N0
P 0

Z 0

system is highly stable


Relative Stability

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G jp H jp

GM

k
0

1
1

G jp H jp 0

Gain margin = 10 log 0 = dB


Highly stable hence proved
Sol.4 (b)

At p phase cross over frequency Im = 0

1 0.52

2 rad/ sec

At p G jp H jp

Im

1.125
1 2 1 0.25 2
1.125
0.25
3 1.5

w= 2

Real

0.25

Gain margin =

1
4
0.25

GMin dB 12.04dB
Sol.4 (c)

1 G s H s 1
G s H s

k
0
s s 1 s 2

K
s s 1 s 2

Char equation is :

1 G s H s 0
s s 1 s 2 K 0

s
(1)

s s 2 K 0

s3 3s 2 2s K 0
Angle of Asymptotes
k

2K 1180
PZ

where K 0,1, 2

0 60
1 180
2 300

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P Z 0 1 2

1
PZ
3
Centroid (1, 0)
Break away point
dK
0
ds

Centroid

K s3 3s 2 2s
dK
0 3s 2 6s 2 0
ds
s1 0.422

2
K=0 K=0

s 2 1.577

60

K=0

These are 2 breakaway pts.


Check validity:
s1 = valid
s2 = not valid
Sol.6 (a):
(i)

Cut off frequency is f CO

gm
2Cgs

0.05
2 0.6 1012
13.26 GHz

f CO

(ii)

Maximum operating frequency is

f max

f
Rd
CO

2 R s R g R i

13.26 109
450

2
2.5 3 2.5
49.73 GHz
Sol.6 (b)

Power gain of horn antenna 4.5

4 4
Ae
4.5
2

So here G p 72

G parabolic

6 D

D
1600 6
10

D 163.2 cm
70 70 10

D
163.2
4.28

H.P.B.W

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10

Drawback of parabolic reflectors:

(1)
(2)

Wave reflected from parabola back to feed antenna produces interaction & mismatching.
The feed antenna acts as an obstruction which results in increasing side lobes and decreasing
gain.

Sol.6(c)

Projected Path

Ionised
Layer
Actual
Path

(1)

(2)

Actual
heitht

Virtual
height

Critical frequency: It is the maximum value of frequency below which if a ray is incident at
normal then it will return back to ground. Only frequency above (fc) at normal incident will
go into atmosphere.
Maximum usable frequency: It is same as fc with only difference that incident is other than
vertical incidence. If angle of incidence is then
MUF fc sec Secant Law

(3)

Skip distance:

(1)
(2)
Skip distance

It is the distance from transmitter where HF wave after reflecting from Ionosphere reaches at
the earths surface back. It depends upon angle of incidence, degree of ionization and
frequency of wave. No communication is possible by sky wave for points nearer than skip
distance. Important layers are D, E, F1 & F2 layers
F2 Layer
F1 Layer
E Layer
D Layer
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11

At night D layer disappears and F1 and F2 merge together to form F layer.

Pr Pt . G t .G r .

4d

3 108

0.5 101 met


9
6 10

Pt dB Pr dB 22 20log10

d
G t dB G r dB

36000 103
22 20 log10
60 60
2
5 10

22 177.15 120 199.15 dB

Pt

Pr
So

Pr

19
8.22 10

103 W
0.122 1016 W
8.22 1019

Pr 1.22 1017 W
Sol.6 (d)

Bolometer is a power sensor whose resistance changes with temperature as it absorbs


microwave power.
The two most common type of Bolometer is:
(1) Baretter
(2) Thermistor
Baretter is a short thin metallic (Platinum) wire sensor which has +ve temperature coefficient
of resistance.
Thermistor is a S.C. Sensor which has ve temperature coefficient of resistance and be easily
mounted in microwave line
Baretters are more dedicated than thermistors and hence they are used only for low powers (<
few mW). Medium and high power is measured with low power Thermistor Sensor.
Forward
detector

Reverse
detector

Pi/100
Pad

Here

Pr/100

Forward
D.C.

Reverse
D.C.

Pi /100 3MW

Pi 300MW

Pr /100 0.1MW

Pr 10MW

Load
ZL

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Pr
10
1

Pi
300
30

K 0.182
VSWR

Sol.7 (a)

1 K
1 K

1 0.182
1.45
1 0.182

# incldue <stdio.h>
# include <conio.h>
Void main ( )
{
int arr [8] = {7, 10, 13, 8, 6, 1, 19, 5}
int i, j, temp;
clrscr ( );
printf (Bubble sort\n);
printf (\n bfore sorting\n);
for (i = o; i < = 7; i + +)
printf (%d\t, arr [i]);
for (i = o i < = 6; i + +)
{
for (j = o; j < = 5 i ; j + +)
{
if (arr [j] > arr [j + 1])
{
temp = arr [j];
arr [j] = arr [j + 1];
arr [j + 1] = temp;
}
}
}
printf (\n\n array after sorting : \n);
for (i = o; i < = 7; i + +)
printf (%d\t, arr [i]);
getch ( ) ;
}
Output :
Bubble sort
Array before sorting
7
10
13
8
6
1
19
Array after sorting
1
5
6
7
8
10
13

5
19

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13

Sol.7 (b)

Basic block diagram of a computer:

Input
unit

Secondary
Storage
Primary
Storage

Output
unit

Information

Control
unit
CPU
ALU

Role of Control Unit:


1.
How does input device know that it is time for it to feed data into memory.
2.
How does ALU know what should be done with data once they are received.
3.
How is that only final results are sent to output device and not intermediate results.
All above are done by control unit of the computer.
It does not perform any actual processing of data it acts as a central nervous system for other
components of computer system.
It manages and co-ordinates the entire computer system. It obtains instructions from program
stored in main memory, interprets the instructions and issue signals which cause other units
of system to execute them.
Role of Main memory / Primary Storage:
It is used to hold pieces of program instruction and data, immediate results of processing and
recently produced results of processing of jobs, which computer system is currently working
on.
These pieces of information are represented electronically in main memory and while it
remains in main memory the CPU unit can access it directly at a fast speed.
Primary storage cr main memory holds its information while computer is ON Main memory
has limited storage capacity and is expensive.

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Vector
Location
0024

Sol.7 (c)
TRAP

I7.5
RST
7.5

003C

R 7.5
RST 7.5
Interrupt
recognised
RST
6.5

M
7.5

I6.5

0034
M
6.5

RST
5.5

002C
M
5.5

DI
RESET
Any interrupt
recognised

EI

GET
RST
code
from
ext. H/W

INTR

INTEL 8085 has 5 interrupts Namely RST 7.5, TRAP, RST 5.5, RST 6.5 and INTR.
TRAP has highest priority followed by RST 7.5, RST 6.5 RST 5.5 and INTR.
EI Enables all interrupts& DI Disable all interrupts
TRAP is a NMI it need not be enabled. It cant be disabled. It is not accessible to user it is
used for emergency operation.
Memory
Microprocessor

Sol.7 (d)
Buses are namely Address bus, data bus and control bus.

Microprocessor

IOP

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