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Danang University of Science and Technology, The University of

Danang, Vietnam

EE 471 Syllabus and Schedule, Semester 1 20142015


Class: 11ECE
1. Teaching Team:
Instructor:
Teaching Assistant:
Lab Assistant:

Ho Viet Viet
Tang Anh Tuan
Tang Anh Tuan

2. Credits: 5
3. Goals:
To teach the organization and design of modern microprocessors. This is the
undergraduate electrical and computer engineering area core course and a key
course for anyone interested in computer engineering. The course serves as an
introduction to the design and analysis of modern computer architectures. It is
expected that students entering this course will have some high-level language
programming experience such as C/C++ or Java and basic understanding of
digital logic design using Verilog HDL.
4. Text book:
Computer Organization & Design, The Hardware/Software Interface, D. A.
Patterson & J. L. Hennessy, Morgan Kaufmann publisher, 5th Edition, 2013.
Other useful references:
Computer Architecture A quantitative approach, J. L. Hennessy and D.A.
Patterson, Morgan Kaufmann publisher, 5th Edition, 2012

5. Prerequisites by Topic:
C/C++ or Java programming
Elementary digital logic design in Verilog HDL

6. Course structure:
This course consists of 5 credits.
There are 7 hours of lecture every week (including lab hours). There will be a
midterm exam and a final exam, and five homework assignments.

Various homework assignments will be assigned every 2 weeks. Generally, these


must be submitted in class on due date; computer use will be discussed in lectures.
There also will be a 90-minute in-class mid-exam and a 120-minute
comprehensive final exam. The schedule for the mid -exam will be announced in
class; the final exam are scheduled by the Academic Affairs.
There will be 4 lab assignments (involving the design of a single-cycle and
pipelined processor with approximately 5-10 instructions),
Using Verilog HDL and CAD Tools, students will design and simulate a simple
microprocessor through 4 laboratory assignments:
Lab1: Design a Register File
Lab2: Design an Arithmetic Logic Unit
Lab3: Design a Single-cycle microprocessor with a simple instruction set
Lab4: Design a Pipelined microprocessor with a simple instruction set

7. Grading system:
Homework Assignments:
Mid-exam:
Labs:
Final Exam:

10%
20%
40%
30%

8. Duration: From 18 Aug 2014 to 09 Nov 2014


9. Syllabus and Schedule:
Week

Day
Tue
Fri
Tue
Fri

Topics covered
Introduction to the course: Course objectives, How to learn and evaluate
Chapter 1: Introduction to Computer: Hardware, System software, and
Application software
Evaluating computers performance Homework 1 out

Chapter 2: MIPS Instruction Set:


MIPS Arithmetic instructions: add, sub, addi
MIPS Memory organization, Data transfer instructions: lw, sw Homework 1
due Homework 2 out

Tue

No class (Independence Day)

Fri

Chapter 2: MIPS Instruction Set (cont.): Logical, Branches instructions and

Tue

Chapter 3: Computer Arithmetic: Addition and Subtraction, Multiplication,


Division, Floating Point (Group Presentation and Discussion) Homework 2
due

Fri

Chapter 4: Design Processor: Datapath and Control of a single-cycle MIPS


with a simplified instruction set Homework 3 out

Pseudo-Instructions

Tue

Chapter 4: Design Processor (cont.): Pipelining and Hazards

Fri
Tue
Fri

Lab1

Midterm exam Homework 3 due


Lab 2

Tue

Chapter 4: Design Processor (cont.): Datapath and Control of a pipelined


MIPS with a simplified instruction set Homework 4 out

Fri

Lab 3

Tue
Fri
Tue
Fri
Tue
Fri
Tue
Fri
Tue
Fri
Approved by

Chapter 4: Design Processor (cont.): Datapath and Control of a pipelined


MIPS with a simplified instruction set
Lab 3

Chapter 5: Memory Hierarchy, Caches: Direct-Mapped Cache Homework 4


due
Lab 4

Chapter 5: Memory Hierarchy (cont.):


N-way Set Associative and Fully Associative Cache Homework 5 out
Lab 4

Chapter 5: Memory Hierarchy (cont.):


N-way Set Associative and Fully Associative Cache
Lab 4 Homework 5 due

Review
Final Exam

Signature

Ho Viet Viet