Computer Organization and Design

Homework 5
1) This series of 32-bit WORD addresses is accessed (Memory with Word Addressing
scheme):
2, 3, 11, 16, 21, 13, 64, 48, 19, 11, 3, 22, 4, 27, 6, 11
Address
2
3
11
16
21
13
64
48
19
11
3
22
4
27
6
11

DM
Miss-CS
Miss-CS
Miss-CS
Miss-CS
Miss-CS
Miss-CS
Miss-CS
Miss-CS
Miss-CS
Hit
Miss-Conflict w/19
Miss-CS
Miss-CS
Miss-CS
Miss-CS
Miss-Conflict w/27

Line
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

Cached Word
16 64 48
2
3 19 3
4
21
22 6

11 27 11
13

2) Like Problem 1, but now assume that the cache is direct-mapped, 4-word blocks, total
16 word capacity.
Address
2
3
11
16
21
13
64
48
19
11
3
22
4
27

4-Word Block #
0
0
2
4
5
3
16
12
4
2
0
5
1
6

DM
Miss-CS
Hit
Miss-CS
Miss-CS
Miss-CS
Miss-CS
Miss-CS
Miss-CS
Miss-Conflict w/16
Hit
Miss-Conflict w/4
Hit
Miss-CS
Miss-CS

Line
0
1
2
3

Cached Blocks
0 4 16 12 4 0
51
262
3

6
11

1
2

Hit
Miss-Conflict w/6

3) Like Problem 1, but assume that the cache is:

a. 2-way set associative, one-word blocks, total 16 word capacity
b. Fully associative, one-word blocks, total 16 word capacity
Assume a Least Recently Used (LRU) replacement policy where applicable.
Address

2-way SA

Line

2
3
11
16
21
13
64
48
19
11
3
22
4
27
6
11

Miss-CS
Miss-CS
Miss-CS
Miss-CS
Miss-CS
Miss-CS
Miss-CS
Miss-CS
Miss-CS
Hit
Miss-Conflict w/19
Miss-CS
Miss-CS
Miss-CS
Miss-CS
Miss-Conflict w/27

0
1
2
3
4
5
6
7

Address
2
3
11
16
21
13
64
48
19
11
3
22
4
27
6

FA
Miss-CS
Miss-CS
Miss-CS
Miss-CS
Miss-CS
Miss-CS
Miss-CS
Miss-CS
Miss-CS
Hit
Hit
Miss-CS
Miss-CS
Miss-CS
Miss-CS

Line
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14

Cached Blocks
Bank A
16 48
2
3 19 3 11
4
21
22

Cached Blocks
2
3
11
16
21
13
64
48
19
22
4
27
6

Cached Blocks
Bank B
64

11 27
13
6

11

Hit

15

4) We are designing a new embedded processor with word addressing scheme (32bit) used for main memory and we are trying to decide what kind of L1 cache to
include in our existing memory hierarchy (the L2 and main memory have already
been designed. We indicate the miss rate for all accesses that enter a given level).
Our layout team has given us the three options shown below:
Level 1 Cache
Type
8KB Fully-Associative
16 KB 4-way SA
16KB Direct Mapped

Write Policy
Write-Back
Write-Through,
Fetch-On-Write-Miss
Write-Back

Other Parts of Memory System

Type
Miss Rate
128 KB L2 Cache
2%
512 MB Main Memory
0%

Block Size
128 Bytes
64 Bytes

Miss Rate
10%
5%

Access Time
1 clock cycle
1 clock cycle

32 Bytes

8%

1 clock cycle

Access Time
10 clock cycles
100 clock cycles

For each:
a) Draw a picture showing how many rows and columns the cache has. Indicate the
width of each field including data, tag, and any necessary valid or dirty bits.
b) Calculate the number of memory bits required to implement each cache.
c) Calculate the average memory access time for the whole system with each cache.
For each:
a) Draw a picture showing how many rows and columns the cache has. Indicate the
width of each field including data, tag, and any necessary valid or dirty bits.
Fully Associative
Requires a per-word valid bit since we do not have a fetch-on-write policy.
Also, since we do not update memory until we evict a location from the cache,
we need a dirty bit for the block. When we update a lower level in the
caching structure (L2 or Main Memory), we will write the valid words in a
dirty block.

Dirty Valid Tag

Dirty Valid Tag

Dirty Valid Tag

Dirty Valid Tag
1 bit

32 bits 25 bits

Data
Data
64 lines

Data
Data
128 bytes =
32 words =
1024 bits

4-Way SA
Requires a per-word valid bit since we do not have a fetch-on-write policy.
However, since we update memory every time we write, we do not need a
dirty bit.
Valid Tag
Valid Tag

Valid Tag
Valid Tag
16 bits 20 bits

Data
Data
Data
Data
64 bytes =
16 words =
512 bits

Valid Tag
Valid Tag

64 lines
Valid Tag
Valid Tag

Data
Data

16 bits 20 bits

64 bytes =
16 words =
512 bits

Data
Data

Valid Tag
Valid Tag

Valid Tag
Valid Tag
16 bits 20 bits

Data
Data
Data
Data
64 bytes =
16 words =
512 bits

Valid Tag
Valid Tag

64 lines
Valid Tag
Valid Tag

Data
Data

16 bits 20 bits

64 bytes =
16 words =
512 bits

Data
Data

Direct Mapped
Does not require multiple valid bits since we have a fetch-on-write policy.
However, we need a dirty bit since we do not update memory until the block
is evicted from the cache. Although a per-entry dirty bit would be optimal
(since we only have to write the updated words to a lower level in the
memory structure), this is unnecessary since it would still be functionally
correct to write non-updated values to lower levels. After all, these lower
levels are where we got the values initially!

Dirty Tag
Dirty Tag

Dirty Tag
Dirty Tag

Data
Data

1 bit 18 bits

32 bytes =
8 words =
256 bits

512lines

Data
Data

b) Calculate the number of memory bits required to implement each cache.

Fully Associative
(1 + 32 + 25 + 1024 bits per line) * 64 lines = 69248 memory bits
4-Way Set Associative
(16 + 20 + 512 bits per line) * 64 lines * 4 banks = 140288 memory bits
Direct-Mapped
(1 + 18 + 256 bits per line) * 512 lines = 140800 memory bits
c) Calculate the average memory access time for the whole system with each
cache.
Fully Associative
Average memory access time = 90% (1) + (10% * 98%) (11) + (10% *
2%)(111) = 2.2
4-Way Set Associative
Average memory access time = 95% (1) + (5% * 98%)(11) + (5% *
2%)(111) = 1.55
Direct-Mapped
Average memory access time = 92% (1) + (8% * 98%)(11) + (8% * 2%)(111)
= 1.94