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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 5, MAY 2013

Design and Performance Analysis of a 866-MHz

Low-Power Optimized CMOS LNA for UHF RFID
Jack Li and S. M. Rezaul Hasan, Senior Member, IEEE

AbstractAn optimized 866 MHz CMOS LNA for UHF radiofrequency identification reader is presented. It achieves simultaneous impedance and minimum Fmin noise matching at a very
low-power drain of 850 W from a 0.7-V supply voltage. Compared to other GHz LNA designs, this UHF LNA design using
sub-1 V supply voltage is quite challenging due to the inductor
size and bias drain-related noise factor degradation. The LNA was
fabricated using the 130-nm IBM CMOS process. Compared to
previously reported narrow-band LNA designs, inclusion of the
finite gds effect is found to improve the nanometric design optimization. The low-cost packaged LNA was tested using external
lumped element and microstrip line matching. The LNA delivered
a power gain (S21 ) of 17 dB and an input power reflection (S11
@ 866 MHz) of 30 dB. It had a minimum pass-band noise
figure of around 2.2 dB and a third-order input-referred intercept
point of 11.5 dBm.
Index TermsCMOS LNA, impedance matching, intelligent
wireless systems, narrow-band, noise matching, radio-frequency
identification (RFID), VLSI.

I. I NTRODUCTION

ADIO-FREQUENCY IDENTIFICATION (RFID) is a

growing intelligent wireless tracking system for information on goods, animals and even humans in transit. An RFID
system usually consists of a transponder (tag) [1], [2], and
a reader [3], [4]. The front end of the RFID reader requires
a narrow-band LNA tuned at a certain RFID transreceiver
frequency. Various frequency bands are utilized for RFID applications, however, by using a frequency in the UHF range
compared to microwave radio frequency (higher wavelength for
UHF), a wider tracking distance can be achieved at a lower
reader power dissipation. LNA designs for RFID reader at
3 GHz [5] and in the UWB spectrum [6] have been reported
recently. Also, UHF RFID transceiver and LNA at 900 MHz
have been reported by authors in [3], [4], [7], [8]. UHF RFID
reader front ends in the 860 to 960 MHz range was addressed
in [9]. A lower frequency standard for UHF RFID in Europe,
Africa, and New Zealand is 866 MHz. Low-power dissipation is a significant design criterion for RFID applications,
which in combination with sub-GHz impedance matching at
Manuscript received June 8, 2011; revised September 19, 2011,
November 15, 2011, and January 3, 2012; accepted February 17, 2012. Date
of publication March 14, 2012; date of current version January 30, 2013.
The authors are with the Center for Research in Analog and VLSI Microsystems dEsign (CRAVE), School of Engineering and Advanced Technology
(SEAT), Massey University, Albany, Auckland 0632, New Zealand (e-mail:
hasanmic@massey.ac.nz; J.Li.2@massey.ac.nz).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2012.2190953

866 MHz, transforms such RFID LNA design optimization

into a challenging task. Various techniques for narrow-band
LNA optimization with respect to power dissipation, noise,
and impedance matching have been reported, such as, classical
noise matching [10], simultaneous noise and impedance matching (SNIM) [11], power-constrained noise optimization [12],
and power-constrained simultaneous noise and input matching
(PCSNIM) [15]. The above approaches lacked mutual consistency. Hence, the authors in [16], [17], provided an integrated analysis of the above narrow-band LNA optimization
techniques based on a consistent set of noise and matching
expressions. A folded cascode LNA design example was also
provided. However, nanometric optimized UHF LNA designs
for RFID have so far not been reported in detail. In this paper,
we discuss the complete design and optimization of a 0.7-V
low-power 866-MHz CMOS telescopic cascode LNA using an
enhanced PCSNIM technique. Unlike most previous optimization techniques, the effect of finite gds (finite output conductance) has been included in this design and analysis, which
results in additional tradeoffs along with design and performance improvements. At deep nanometric device geometries,
gds is no longer negligible compared to the device transconductance gm , particularly for low-power LNA designs, and
hence, classical LNA design and analysis techniques need a
re-evaluation.
II. O PTIMIZED L OW-P OWER UHF RFID LNA D ESIGN
An inductively source degenerated telescopic cascode topology has been chosen for the 866-MHz RFID LNA design.
This is because the telescopic cascode is inherently a current
reuse structure and consumes less bias current than the folded
cascode. Fig. 1 shows the circuit diagram of the proposed RFID
LNA. M1 is the input inductive source degenerated amplifier
device which creates a noise-free resistive component looking
into the gate input facilitating matching with the source resistance. Lg is an external inductor for complex conjugate input
reactance matching. Ce is an external capacitor to facilitate
matching for low-power design. For low-power deep nanometric CMOS devices, the finite output conductance (gds =
1/ro ) is no longer negligible compared to the transconductance
(gm ) and hence is shown in parallel with the MOS devices in
Fig. 1. Ld, Rd, and Cd form the output tank circuit tuned at
866 MHz with an angular frequency bandwidth of 1/(Rd
Cd). The relative values of Ld and Cd are carefully chosen
so as to prevent tank detuning by the parasitic capacitance at
the drain of M2. The LNA is loaded via an external matching

0278-0046/$31.00 2012 IEEE

LI AND HASAN: DESIGN AND PERFORMANCE ANALYSIS OF A 866-MHz LOW-POWER OPTIMIZED CMOS LNA FOR UHF RFID

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Fig. 3. Front end of the RFID LNA with embedded noise sources and short
circuit output noise current power for noise analysis.

with, gg1 expressed as

Fig. 1.

Proposed narrow-band circuit topology for 866-MHz RFID LNA.

gg1 =

2
2
2 Cgs1
2 1 Cgs1
=
5gdo1
5gm1

(2)

where, 1 and 1 depend on the channel length of the device

M1. The drain current noise is given by
1
i2nd,m1 (f ) = 4KT 1 gdo1 = 4KT gm1
(3)
1
where, the noise parameter 1 also depends on the channel
length of M1. Also, the parameter 1 is given by
gm1
(4)
1 =
gdo1

Fig. 2. General equivalent circuit of the RFID LNA suitable for mesh
analysis to extract gain and noise transfer functions, where ro1 = 1/gds1 and
ro2 = 1/gds2 .

circuit. Cac at the input and at the output are ac-coupling

capacitors, while Cb is an ac grounding capacitor at the gate of
the cascoding device M2. M3 in conjunction with Rref controls
the bias current through the telescopic cascode while a large
Rb ensures that noise and any ac signal pick-up at the gate of
the current mirror device M3 is largely decoupled from the RF
input at the gate of M1. The effect of finite gds on the current
mirror is the deviation of the bias current from that due to
the simple current mirror device ratio. A general equivalent
circuit of the RFID LNA suitable for mesh analysis, for the
extraction of the gain and the noise transfer functions, is shown
in Fig. 2. In this circuit, the output impedances ro1 and ro2
represent the reciprocals of the finite channel conductances gds1
and gds2 , respectively. Also, Fig. 3 shows the noise inserted
circuit diagram of the RFID LNA front end which accounts
for the major noise components contributing to the short circuit
output noise current at the drain of M1. Drain current noise and
induced gate noise are the significant noise components in the
LNA circuit. The individual noise power spectral densities are
as follows: The induced gate noise is given by
i2ng,m1 (f ) = 4KT 1 gg1

(1)

with gdo1 being the zero-bias drain-to-source (channel) conductance for M1 [18]. In all the noise expressions, K is the
Boltzman constant, and T is the ambient temperature in K.
The correlation factor, c1 between the induced gate noise and
the drain current noise for M1 is given by
ing,m1 (f )ind,m1 (f )
c1 = 
.
i2nd,m1 (f )i2ng,m1 (f )

(5)

Using c1 , the induced gate noise for M1 can be divided into

a component given by
i2ngc,m1 (f ) = 4KT 1

2
2 1 Cgs1
|c1 |2
5gm1

(6)

which is fully correlated with the drain current noise, and a

second component given by
i2ngu,m1 (f ) = 4KT 1

2 

2 1 Cgs1
1 |c1 |2
5gm1

(7)

which is fully uncorrelated with the drain current noise. The

other noise sources include the thermal noise of the source
resistance, which is given by
2
VnT,R
(f ) = 4KT Rs
s

(8)

and the thermal noise of the capacitively transformed gate poly

resistor, given by
2
VnT,R
(f ) = 4KT RGe .
Ge

(9)

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Fig. 4.

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 5, MAY 2013

Capacitive transformation of RG due to the addition of Ce across M1.

Noise figure (NF) [18] is the ratio of the total output noise
power to the output noise power due to the input source (the
noise factor) expressed in dB. The different aspects of the
optimized RFID LNA design including the finite gds effect are
discussed next.
Fig. 5. Variation of the analytical Re(Zin ) with finite output impedance
(ro1 = 1/gds1 ) of M1 for nanometric CMOS.

A. Design Methodology
Power constrained SNIM technique is used as the basic
design methodology. The smaller device size of M1 for minimizing power dissipation at highly scaled supply voltage is
compensated by the parallel capacitance Ce across M1 in order
to achieve minimum NF Fmin and impedance matching under
low-power dissipation. One advantage derived as a byproduct
of this capacitive device size compensation is the capacitive
transformation [19] of the poly gate resistance of M1 to a lower
value resulting in lower line drop in the input circuit. This is
shown in Fig. 4 where RG is transformed to RGe , given by
RGe
= RG

(15)

(17)

2 1 Ct2
.
5gm1

(11)

With
2
Cgs1
Ct2

(12)

Ct = (Cgs1 + Ce ).

(13)

Now, the theoretical Fmin given by [16]

2 Cgs1 
Fmin
1 1 (1 |c1 |2 )
=1+
5 gm1

(14)

requires the optimal impedance (Zopt ) for noise match, with

this low-power constraint, to be approximately given by
[16], [17]

1
Zopt =
Cgs1

1
51

(1 |c1 |2 ) + j

21 1
51

(1 |c1 |2 ) +




Ct
Cgs1
Ct
Cgs1

(16)

 
1
+ 1 |c1 | 5
1
 2 .
1
+ 1 |c1 | 5
1

(10)

where, Cgs1 is the gate-to-source capacitance of M1. Next, by

rewriting the expression for the induced gate noise, we have

1mod = 1

Ls gm2
1
gm1
+
Zin
= sLs +
sCt
Ct (gds1 + gm2 )

where gm2 is the transconductance of the cascode device M2.

Fig. 5 shows the plot of the resistive component of Zin ,
Re(Zin ), in (16) with the variation in ro1 (= 1/gds1 ) of M1
(being around 450 ohms in this design) from the long channel
assumption (ro1 ). The plot indicates that the Re(Zin )
at resonance typically changed by 612% with the inclusion
of gds1 in (16). In addition, as shown in Fig. 5, the extent of
the Re(Zin ) inaccuracy with the long channel assumption also
varies with the chosen value of the source inductor Ls . Equation
(16) also indicates that for deep nanometric design, the finite
output conductance of M1 adds an additional tradeoff factor
in determining the value of the capacitor Ce (in Ct ) required
for achieving power constrained input matching. Changing
the overdrive and/or the width of M2 (and hence gm2 ) in
relation to gds1 provides an additional degree of freedom to
reach this value of Ce for input matching. Essentially, this
tradeoff enables a lower value of Ce and hence a higher T1 (
gm1 /Ct ) in achieving input impedance matching for a given
gm1 . In addition, inclusion of the finite gds effect results in
a more accurate power constrained simultaneous optimization
of noise and impedance matching for nanometric CMOS, and
hence, this overall improved technique is termed as enhanced
PCSNIM. It is also to be noted that the above optimization
equations are valid only for reasonably small values of Ls , and
hence inclusion of the gds effect is crucial based on the plot in
Fig. 5. Now, to achieve noise matching, the source resistance
(Rs ) and the matching reactance near the source (Lg ) must
transform the impedance at the source to Zopt . Hence, we have
the equivalences

1
1 5
(1 |c1 |2 )
1

Rs
=
 2

21 1
Ct
1
2
Cgs1 51 (1 |c1 | ) + Cgs1 +1 |c1 | 5
1

2
Cgs1
(Cgs1 + Ce )2

i2ng,m1 (f ) = 4KT 1mod

The input impedance of the RFID LNA (including the output

conductance gds1 of M1) can be easily derived as

LI AND HASAN: DESIGN AND PERFORMANCE ANALYSIS OF A 866-MHz LOW-POWER OPTIMIZED CMOS LNA FOR UHF RFID

1843

 
1
+1 |c1 | 5
1

sLg

=
 2 sLs .

21 1
Ct
1
2
sCgs1 51 (1|c1 | )+ Cgs1 +1 |c1 | 5
1


Ct
Cgs1

(18)
At deep nanometric channel lengths, the value of 1 /1 2
(remains almost unchanged with progressive scaling), 1 < 0.9
and |c1 | < 0.395 as drain and gate noise correlation reduces
with deep nanometric scaling [20][22]. As a consequence, we
have the revised noise matching conditions given by

1
1 5
(1 |c1 |2 )
1
(19)
Rs
Ct2
Cgs1
1
sLs .
(20)
sLg
sCt
Next, for simultaneous input impedance matching, the source
impedance (with matching inductor Lg) must be the complex
conjugate of Zin , so that the real and the imaginary parts in
(16) have the following equivalences, given by
gm1
Ls gm2
= Rs
Ct (gds1 + gm2 )
1
= sLg .
sLs +
sCt

(21)
(22)

Equations (20) and (22) are redundant and can be satisfied

automatically, so that (19) and (21) are the primary design
equations to achieve the enhanced SNIM, which includes the
effect of finite gds in yielding a lower value of the external lowpower matching capacitor Ce . Notably, (19) also indicates why
noise matching becomes more difficult at sub-GHz frequencies
for a source resistance of around 50 .
B. Enhanced PCSNIM LNA Design Algorithm
Since it is necessary to restrict Ls to a reasonably low but
implementable value in order to be able to achieve a low
value of Fmin within the desired power dissipation constraint
P C(= IBIAS VDD ), the starting point of the design is the
selection of a value for Ls and PC. The optimized parameters
(gm1 , W1 , and Cgs1 ) that are derived from this choice of Ls
and PC are then checked for fT (should be at least five times
the selected RFID frequency) and the simultaneous satisfaction
of (19) and (21) by a specific value of Ce (= Ct Cgs1 ).
For a given set of values of Ls and PC, multiple values of
overdrives and widths of M1 (and width of cascode device M2
with gate tied to VDD ) are chosen and simulated for obtaining
optimized values of S-parameters (particularly S11 and S21 )
and a minimum Fmin at the specified RFID frequency. The
optimized values of gm1 and Cgs1 are then plugged into (19)
and (21) and a value of Ce (= Ct Cgs1 ) is next determined
which satisfies (19) and (21) simultaneously at the specified
RFID frequency. Changing the overdrive and/or the geometry
of M2 (and hence gm2 ) in relation to gds1 provides an additional
degree of freedom to reach this value of Ce which is suitably
lower than that by the previous PCSNIM technique which did
not consider the finite gds effect. The unity gain frequencies,

Fig. 6. Diagram of the design steps for the proposed enhanced PCSNIM
algorithm.

fT1 (gm1 /2Ct ), and fT2 (gm2 /2Cgs2 ) are checked next
so that fT1 , fT2 5fRFID . Since a smaller Ce is achieved
using this enhanced technique, the fT1 is larger in this case,
and hence, it is easier to meet the condition fT1 5fRFID .
If a suitable Ce cannot be found or fT1 , fT2 5fRFID , Ls and
PC are changed incrementally and the procedure is repeated
again. Finally, Lg can be obtained automatically from either
of the coincident equations (20) and (22). A diagram of the
algorithm is shown in Fig. 6. Fig. 1 shows the component and
device sizes obtained after several iterations of the algorithm
for Ls 2 nH and PC 800 W for a 0.7-V power supply at
866 MHz. Here, gm1 gm2 0.022 siemens, gds1 gds2
0.0022 siemens (with ro 450 ohms) and Cgs1 128 fF.
Also, the unity gain frequencies, fT1
= 4.5 GHz, and fT2
=
25 GHz are both 5 866 MHz. A Ce of 580 fF results in
a Re(Zin ) 55 ohm at resonance from (16) which closely
satisfies (21) using this enhanced technique. If the previous
design procedure without the finite gds consideration is carried
out, a Ce of around 640 fF (around 10% higher value of Ce )
will be required to closely match the 50-ohm source impedance.
Lg is implemented externally in order to accommodate its size
without any significant Q degradation.
C. Gain and Frequency Response Analysis
The s-domain gain transfer function, AV (s) of the RFID
LNA (with the forward power gain S-parameter, S21 20

1844

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 5, MAY 2013

Fig. 7. Plot of the analytical noise figure with and without the consideration
of finite gds .

Fig. 9. Schematic for circuit simulation including LNA, package parasitics,

and external matching components.

Fig. 10. Band-pass lumped element output matching circuit, (a) matching
network, (b) L-matching network.

Fig. 8. Photomicrograph of the fabricated RFID LNA.

D. Frequency Spectrum of the Noise Figure

log Av (s)) can be easily determined by first finding the short

circuit transconductance (GM1 ) and the open circuit output
impedance (ZOUTM1 ) at the drain of M1 and finally noting
that ZOUTM1 is large compared to ZINM2 (looking into the
common gate stage). Thus, most of the drain current of M1
would flow into the drain of M2, and the voltage gain, AV (s)
would be given by (23), shown at the bottom of the page, where,
gds1 = 1/ro1 . As can be seen from (23), the enhanced PCSNIM
technique may result in reduced gain if Lg is large. A large
Lg may also lead to noise limitations. Also, the finite gate
poly resistance and the matching inductor resistance reduce
the forward gain and increase the input-referred third-order
intercept point (IIP3) of the LNA with respect to the IIP3 of
M1. In addition, a large value of RLs will further degenerate
the voltage gain of the LNA.

Although the RFID LNA optimization for a minimum Fmin

has been performed taking into account the finite gds , the
frequency spectrum of the NF with the inclusion of the finite
gds effect also needs to be derived. A novel technique based on
determining the short circuit output noise current power at the
drain of M1 was used for the noise analysis. In this method, the
output load is shorted compared to the method in [16] where
the output noise current is determined with the output load.
Since the noise factor is defined as the ratio of the total meansquared output noise current due to all the noise sources to the
input source only, and as the noise factor mostly depends on the
front-end noise sources farthest from the output load, almost
the same value of noise factor is obtained using this technique
without the extra calculation, compared to if the output noise
current with the load is used in the computation. Hence, the
noise factors of the front-end noise sources using this short

gm1 +

(sCt +gm1 )(RLs +sLs )

(ro1 +RLs +sLs )

 
sC

1
1
d+ R

1
+ sL

d
d

AV (s) =



r (RLs +sLs )
1 + sCt Rs + RLg + RLs + RGe + sLg + sLs + (gm1 + sCt ) (ro1
o1 +RL +sLs )
s

(23)

LI AND HASAN: DESIGN AND PERFORMANCE ANALYSIS OF A 866-MHz LOW-POWER OPTIMIZED CMOS LNA FOR UHF RFID

Fig. 11. Test board photograph with the LNA in a 28-pin DIP package along
with lumped L-matching components and SMA connectors.

circuit output noise current method are added to obtain the

overall frequency behavior of the noise factor, N(f). The noise
inserted diagram of Fig. 3 was used for this purpose. In
order to keep the analysis manageable, noise contributions
of gate poly and the inductor resistances were considered
negligible. The individual contributions of all the front-end
noise sources to the short circuit output noise current power
are determined and their noise factors are added to obtain
the overall analytical frequency behavior of the noise factor (N(f)) of the RFID LNA given by (24), shown at the
bottom of the page. Fig. 7 shows an approximate comparison of this new expression (considering the finite gds ) with
and without the consideration of the finite gds [16], [25],
for the cascode LNA design in Fig. 1. Clearly, the expression in (24) accurately indicates a NF minima at 866 MHz
compared to the one without the finite gds . In addition, Fig. 7
also indicates that noise optimization at 866 MHz without the
consideration of finite gds can result in higher inductor values
compared to the enhanced technique with the consideration of
finite gds . The MATLAB plot of (24) is also compared with the
simulation and the measurement results.

2 2
1 1 Cgs1
N (f ) = 1 +
5 Rs gm1

1 gm1
1 Rs

+ 2j|c1 |

2
ro1

1 2 Lg Ct 2 Ls Ct

2 Ct2 Ls +
Cgs1 ro1

Fig. 12. Smith chart for open circuit stub microstrip line matching at the input
pin (p8) of the packaged LNA.

Fig. 13. Smith chart for open circuit stub microstrip line matching at the
output pin (p7) of the packaged LNA.

III. S IMULATION AND M EASUREMENT R ESULTS

The proposed 866-MHz UHF RFID LNA was extensively
simulated using the BSIM4 model (including the postlayout

2

2 + 2 L2
2 Ct2 ro1
s

Rs 2 Ct2 Ls +

1 1
5

2
gm1 ro1
Rs L2s + ro1 gm1 L2s + gm1 ro1 Lg Ls 2

gm1 ro1
Ct

2

gm1 ro1
Ct

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2
2
+ 2 ro1 Ls + gm1 ro1
Lg + gm1 ro1
Ls + gm1 ro1 Rs Ls



Ls +

gm1 ro1
Ct

2

2

+ 2 Ct2 Rs2

2

2
2

2 R (L2+r g
2
2
gm1 ro1
s
o1 m1 Ls +gm1 ro1 Lg Ls )
s

2 L +g
2
+ 2 ro1 Ls+gm1 ro1
g
m1 ro1 Ls+gm1 ro1 Rs Ls

2 + 2 L2
ro1
s

2 

(1 2 Lg Ct 2 Ls Ct )2+ 2 Ct2 Rs2

(24)

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 5, MAY 2013

Fig. 14. Complete LNA matching setup using single open circuit stubs and microstrip lines.

Fig. 15. Test board using single open circuit stubs and microstrip lines.

RC extracted circuit). The LNA (as part T8BTAU) was fabricated using the 130-nm IBM CMOS process available through
MOSIS. Fig. 8 shows the microphotograph of the 0.571 sq. mm.
die which was packaged in a plastic DIP. The package pin
numbers are indicated for each bonding pad on the die photo.
The spiral inductors were fabricated using 5 m wide traces
of top thick aluminum layer MA, with copper layer E1 used
as underpass contact to the spiral center. The outer diameters of the inductors were, respectively, 240 m for Ld and
140 m for Ls. The capacitors Ce and Cd were fabricated as
MIM capacitors using multiple thin metal (QY and HY) and
thin dielectric (aluminum nitride) sandwiches interconnected
using enclosing layers E1 and LY, and FT via contacts. The
resistors were fabricated using p+ poly layer with high sheet
resistance (340 /square). In order to consider and design
the appropriate output matching network, the composite LNA
with package parasitics was resimulated, and the overall LNA
performance using the matching network was evaluated. Fig. 9
shows the schematic for the circuit simulation of the composite
LNA with pin parasitics and the external passive matching
components to match to 50 . Initially, performance analysis
was carried out using lumped external components in order
to obtain an initial assessment of the matching performance
and approximate component values. The circuit diagram of the
lumped element output matching circuit using (a) a bandpass
matching network, or, (b) an upward L-match [18], [23], along
with the component values is shown in Fig. 10. At the input, a
series inductor, Lg = 27 nH, was used to provide simultaneous
noise and power match as per the optimization technique in
Section II, including the package parasitics. Forward power
gain and noise considerations influenced the choice of this value
for Lg instead of the simulated value of 45 nH. Photograph
of the test board with the lumped element upward L-match
components, Co = 1.44 pF and Lo = 19 nH, along with the
ac coupling capacitors, Cac = 100 pF and SMA connectors
is shown in Fig. 11. Although resonance was noticed near
866 MHz, the lumped element L-matching was not satisfactory
mostly due to reactance mismatch and resistive loss in the

Fig. 16. Comparison of the measured, simulated and analytical (with and
without the finite gds consideration) plots of the forward power gain S21 of
the RFID LNA.

Fig. 17. Comparison of the measured and simulated input reflection coefficient, S11 (in dB) of the RFID LNA.

external lumped inductors and along the interconnect traces.

Next, microstrip line and open circuit stub matching was carried
out using the simulated values of S11 and S22 at the package
pins for the LNA input and output which includes the reactive
(LC) package parasitics. Figs. 12 and 13 show the Smith charts
for open circuit stub microstrip line matching at the input
pin (p8) and the output pin (p7), respectively, of the packaged LNA. Fig. 14 shows the complete single open circuit
stub and microstrip line LNA matching setup diagram, while
Fig. 15 shows the FR4 test board implementation using open
circuit stubs and microstrip lines. Lg (for simultaneous noise

LI AND HASAN: DESIGN AND PERFORMANCE ANALYSIS OF A 866-MHz LOW-POWER OPTIMIZED CMOS LNA FOR UHF RFID

Fig. 18. Results of 200 iterations of Monte Carlo analysis of the forward
power gain, S21 .

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Fig. 20. S11 measurement results from a lot of 20 RFID LNA dies.

Fig. 21. Comparison of the measured, simulated, and analytical (with finite
gds ) noise figure (NF in dB) of the RFID LNA.
Fig. 19. S21 measurement results from a lot of 20 RFID LNA dies.

and power match) is absorbed in the input matching microstrip lines. Next, the forward power gain, S21 , and the
input reflection coefficient, S11 (in dB) were measured for
the microstrip line matched packaged RFID LNA using an
Agilent 86100C DCA-J Oscilloscope in the TDR/TDT mode.
Fig. 16 shows the plot of the measured S21 along with the
simulated and analytical values (with and without the finite
gds consideration). As the figure indicates, a measured power
gain of 17 dB is achieved, and the analytical S21 with the
consideration of finite gds based on (23) tracks the simulated and measured S21 much more closely compared to the
analytical S21 without the consideration of the finite gds .
Next, Fig. 17 shows the measured input reflection coefficient
S11 which corresponds to a return loss of 30 dB at 866 MHz.
The simulated S11 is also shown in this figure which is roughly
close to the measured value. The accurate estimation of Zin
in (16) with the inclusion of finite gds results in excellent
input matching for the optimized LNA. In order to determine
the effect of process, supply voltage and temperature variation on the RFID LNA circuit, statistical analysis through
Monte Carlo simulations were also carried out. A 15% supply

Fig. 22. The 1-dB compression (from single tone test) and the IIP3 (from two
tone test) points for the UHF RFID LNA.

voltage variation, along with temperature fluctuations between

23 C and 90 C, and Lot-to-lot (and wafer-to-wafer) processdependent threshold voltage deviation (maximum of 15% [26])
was considered. A Gaussian distribution function was used for
the simulations. Fig. 18 shows the results for 200 iterations
of these Monte Carlo simulations, which indicates that the
design is quite robust. Figs. 19 and 20 show the measured

1848

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 5, MAY 2013

TABLE I
S UMMARY OF THE 866-MH Z UHF RFID LNA P ERFORMANCE , AND C OMPARISON W ITH P REVIOUS UHF LNA D ESIGNS

results of S21 and S11 for a lot of 20 packaged RFID LNA

chips received from MOSIS, which indicate quite low foundry
process technology-related performance mismatch or degradation. Fig. 21 shows the comparison of the analytical (with
finite gds ), the simulated and the measured NF spectrums which
verifies the close approximation provided by (24) due to the inclusion of the finite gds effect. The measured minimum NF was
around 2.2 dB (using low DANL noise floor spectrum analyzer
[24]) which compares favorably with other nonoptimized UHF
RFID LNA designs operating with higher power dissipation
from much higher supply voltages. Next, the IIP3 and the 1-dB
compression points were determined to consider the linearity
of the LNA. A singe tone test at 866 MHz indicates a 1-dB
compression point of around 16.1 dBm, while separately
a two-tone test at 866 MHz with a 1-MHz tone separation
indicates an IIP3 of 11.5 dBm. Both of these points are
plotted in Fig. 22. Table I shows a summary of performance
comparison of the proposed UHF LNA with other UHF LNA
designs indicating a very low NF achieved at sub-mW power.
A figure of merit (FOM) based on [27] given by
FOM[mW1 ] =

Gain[abs]
.
(NF 1)[abs] PDC [mW]

(25)

was also used for the comparison. Here, abs and PDC , respectively, represent absolute value and dc power dissipation. The
FOM clearly indicates the advantage of the presented RFID
LNA design compared to the other designs. In addition to
RFID wireless tracking systems, it will also find application in
RFID wireless sensors [28], [29].

IV. C ONCLUSION
The improved power constrained optimization of an UHF
RFID LNA design at 866 MHz considering finite gds effects
is presented, and measurement results using microstrip line
matching are demonstrated. The design achieves very low
NF using only a 0.7-V supply voltage and 850 W power
dissipation.

ACKNOWLEDGMENT
The authors wish to acknowledge CMOS fabrication support
from MOSIS, USC, Los Angeles. Chip photography by Colin
Plaw and Ken Mercer is also acknowledged. In addition, the
quality of the paper has been considerably enhanced through
the comments of the anonymous reviewers.

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1849

Jack Li received the B.Eng. degree in computer engineering from Massey University, Albany,
New Zealand, in 2006. Presently, he is working
toward the Ph.D. degree in integrated circuit design
at the center for research in analog and VLSI microsystem design (CRAVE) at Massey University.
He has published several papers in radiofrequency
integrated circuit design. His areas of research interest include analog, RF, and mixed signal IC design.

S. M. Rezaul Hasan (SM02) received the Ph.D.

degree in electronics engineering from the University
of California Los Angeles, Los Angeles, in 1985.
From 1983 to 1986, he was a VLSI Design
Engineer at Xerox Microelectronics Center in El
Segundo, CA, where he worked in the design of
CMOS VLSI microprocessors. In 1986, he moved
to the Asia-Pacific region and served several institutions including Nanyang Technological University,
Singapore (19861988), Curtin University of Technology, Perth, Western Australia (19901991), and
University Sains Malaysia, Perak, Malaysia (19922000). At University Sains
Malaysia, he held the position of Associate Professor and was the Coordinator
of the Analog and VLSI research laboratory. He spent the next four years
(20002004) in the West Asia-Gulf region where he served as an Associate
Professor of Microelectronics, Integrated Circuit Design, and VLSI Design
in the Department of Electrical and Computer Engineering at the University
of Sharjah, Sharjah, United Arab Emirates. While in Sharjah, he received
the National Bank of Sharjah Award for outstanding research publication
in Integrated Circuit Design. Presently, he is the Director of the Center for
Research in Analog and VLSI microsystems dEsign (CRAVE) at Massey
University, Auckland, New Zealand. He is also a Senior Faculty Member
within the School of Engineering and Advanced Technology in Electronics and
Computer Engineering, teaching courses in Advanced Microelectronics and
Integrated Circuit Design. He has published over 138 papers in international
journals and conferences in the areas of analog, digital, RF and mixed-signal
integrated circuit design, and VLSI Design.
Dr. Hasan has also served as consultant for many electronics companies.
His present areas of interest include analog and RF integrated circuit and
microsystem design, semiconductor device physics, CMOS sensors, CMOS
microbioelectronics, and biological (gene-protein) circuit design. He is an
Editor of the Hindawi journal of active and passive electronic components.