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2012 IEEE 7th International Power Electronics and Motion Control Conference - ECCE Asia

June 2-5, 2012, Harbin, China

High Performance DC-DC Converter for

Wide Voltage Range Operation

River T H, Li Mircea-Florian Vancu Francisco Canales Daniel Aggeler

ABB CRC Switzerland ETH Zurich Switzerland ABB CRC Switzerland ABB CRC Switzerland
river.li@ch.abb.com vancu@lem.ee.ethz.ch francisco.canales@ch.abb.com daniel.aggeler@ch.abb.com

Abstract-This paper presents a galvanic isolated multi-level dc­

dc converter using different modulation strategies for wide vol­
tage range operation. The dc gain of the converter can be
changed in three steps by the proposed modulation schemes and
+ Cin1 +

thus achieve the change in output voltage among Vout, 0.5x Vout 'IGIII "en 1
and 0.25x Vout• The operating frequency of the resonant tank is
the same in all three cases. Therefore, the converter can be de­ D" D,2
signed to operate at the optimal operating point to maintain high +

CQllt R,oaJ V",d

efficiency for a wide voltage range operation. The output voltage
can then be adjusted within the three output voltages depending
on the application by either varying the switching frequency of D" D",

the converter or cascading a second stage dc-dc converter. The

+ C;",2 +
operating principle and the dc characteristics of the proposed "01112 "Cu2
modulation scheme are discussed and demonstrated with a 17kW
five-level half-bridge LLC resonant dc-dc converter prototype
operating at 150 kHz. The input and output voltage of the con­
verters are 750V voltage and, 650V, 325V and 163V output vol­
tages, respectively. The experimental results are closely matched
Figure 1: Schematic of the proposed five-level resonant converter.
with the theoretical predictions.

switching frequency is deviating from the optimal operating

Keywords: multi-level dc-dc converter, resonant converter,
point, which is defmed by the resonant frequency because the
modulation strategies, power electronic transformer
semiconductor tum-off losses as well as conduction losses are
increasing. The change in the modulation strategy leads to
I. INTRODUCTION higher efficiency and can therefore maintain constant high
converter efficiency over wide voltage range operation. How­
Power electronic converters are becoming an important
ever, if the voltage range for certain application is even wider,
element for the future development of critical applications and
two modulation strategies are not any more the best solution.
are entering more and more in technologies, which traditionally
Therefore, this paper proposes a method to reduce the impact
belongs to different engineering disciplines as e.g. power dis­
of wide output/input voltage range in the performance of dc-dc
tribution [1] [2] and universal power supplies [3]. Therefore,
isolated converter for high-input voltage applications. The ap­
the power electronic converter technology has not only to meet
proach combines the use of a five-level structure with proposed
characteristics demanded by the load, but also be able to
modulation strategies allowing two-level, three-level and five­
process energy with high efficiency, high reliability, high pow­
level mode operation according to the output voltage range.
er density and low cost. Furthermore, the possibility of having
Therefore, the required extreme output voltage variations of the
power converters which not only optimize performance and
converter can be achieved without penalizing the performance
minimize the size of magnetic elements, but also allows the
of the converter. As a result, the derating of efficiency encoun­
stabilization and improvement on the grid is of great benefit.
tered by the previous approaches can be avoided.
The use of resonant converters is an attractive option to reach
the aforementioned high requirements [4] [5]. However, for
wide output/input voltage variation, the converter must operate 11. CHARACTERISTIC OF THE PROPOSED FIVE-LEVEL
with a wide range of switching frequency, which complicates RESONANT CONVERTER
the optimization of the converter [6] - [8]. In order to operate in Figure I shows the topology of the proposed 5-level LLC
wide voltage range, it is nearly impossible to process the ener­ resonant converter. By the 5-level configuration, the voltage
gy with a single stage solution as presented in [9]. There, a across the switches, Sj to Ss, is only a quarter of the input vol­
combination of frequency modulation and using two different tage /lin. The power processing is realized in a resonant mode
modulation strategies in order to change the DC gain of the where ZVS is achieved at tum-on and reduced tum-off losses
converter is compared with a single stage solution. It shows result for Sl to Ss. The resonant inductor, Ln can be imple­
that the converter efficiency decreases when the mented by using the inherent leakage inductance of the trans-


978-1-4577-2088-8/11/$26.00 mOl21EEE
former. Thus, the power density of the converter can be in­ Therefore, the output voltage of the converter can be described
creased. The switching frequency of the converter is designed as follow,
to be lower than the resonant frequency of the resonant tanle
The magnetizing current is used to achieve the ZVS condition. (1)
Furthermore, the converter is operated in the region where the
DC gain is insensitive to the load variations. As a result, the
converter operates in an open loop manner which allows the Whereas Vout is the output voltage of the five-level resonant
optimization of the transformer and converter design. It is im­ converter, Np and Ns are the number of turns of primary and
portant to mention that this operation mode will require an ad­ secondary winding of the transformer and I is the number of
ditional conversion stage which will take care of the characte­ levels of the modulation strategies. Therefore, the output vol­
ristics demanded by the load. Due to the LLC resonant tank tages of the resonant converter are VOUb 0.5x Vout and 0. 25x Vout
characteristics, the diodes on the secondary side, Dr! to Dr4, with respect to two-level, three-level and five-level modulation
operate under ZCS condition. Thus, the reverse recovery losses strategies.
are minimized. Due to this reason, standard ultra-fast Si diodes
A. Two-level Modulation
can be used. The converter is operated with a two-level, three­
level or five-level modulation strategy without penalizing the Figure 2 shows the timing diagram of two-level modulation.
performance. The converter behaves as a power electronic The operation is similar to the typical two-level resonant con­
transformer with a variable turns ratio. Figure 2, Figure 4 and verter by applying a square waveform to the resonant tank, vAB,
Figure 5 show the gate signals and the key waveforms for the with a peak value equals to Vin.
proposed modulation strategies. In order to guarantee the same
In the positive half cycle, Sl, Sz, S7 and Sg are closed. VAB
DC gain despite of the input/output voltage variations, the con­
equals to Vin. Drl and Dr4 are conducting in this mode. The re­
duction time of the switches S), Sz, Ss and S7 has to be equal
sonant tank is excited by the input voltage and the resonant
and constant in all given modulation strategies. Tn order to meet
tank current, iLr, is flowing in the positive direction.
this requirement, the switching frequency in each modulation
strategy is different. Tn this case, the switching frequency will In the negative half cycle, S3, S4, Ss and S6 are closed. vAB
be Is for the two-level modulation, O.5xls for three-level mod­ equals to zero. Drz and Dr3 are conducting in this mode. The
ulation and 0.25xls for five-level modulation. Therefore, an resonant tank is excited by the resonant capacitor voltage, vcr,
equal equivalent frequency across the resonant tanl... and trans­ which contains a DC component, and iLr flows in the negative
former are achieved despite of the modulation strategies. The direction.
combination of the five-level structure with the LLC resonant
tank allows high frequency operation with high efficiency. Tn In the two-level modulation, four of the switches have to
this way, the power density of the DC-DC converter is in­ share the full dc link voltage. Sl, Sz, S7 and Sg for the positive
creased when compared with the state of the art ZVS PWM half cycle and S3 to S6 for the negative half cycle. Theoretically,
converters in wide voltage range operation. four of them are switching at the same time in order to evenly
share the dc link voltage. However, the voltage balancing be­
tween the MOSFETs is not guaranteed because of the tolerance
of the parasitic drain-source capacitances, Cds, and the timing
This section presents the operation principle of the pro­ of the gate signals. Moreover, Cds is very sensitive to drain­
posed solution. As mentioned, for voltage conversion from e.g. source voltage and behave highly non-linear. This makes diffi­
a fixed input to a wide output voltage range, it can be realized cult that the drain-source voltage of MOSFETs is naturally
by a single stage resonant converter. However, due to the wide "

operating range, the converter design, and thus the converter's S,S, S,.S S .s,
v. .",
efficiency and performance, can only be optimized at a single .
s.,. s� S.S S,.5
operating point. Tn order to keep a good performance through­ i"
out the operating range, a two stage solution with a front stage
five-level LLC series resonant converter cascaded by a buck
type converter is proposed. This configuration can maintain the
efficiency nearly constant throughout the operating range and
simplified the filter requirements of the buck type converter as
the duty cycle is confmed to a narrower range. In addition, the
rms current in the converter is also minimized. The following
description will be focused on the voltage conversion from a
fixed input to a wide output range. The operation mode for a
voltage conversion with the opposite characteristic, wide input
voltage range to a fixed output voltage, is the same.
The five-level resonant converter can provide three differ­
ent output voltage levels according to the modulation strategies.
As mentioned before, the converter is designed to work with
fixed switching frequency and the DC gain is close to unity.
Figure 2: Timing diagram of the two-level modulation strategy,

before mode 1 and the drain-source voltage of S3 to S6 is equal
to a quarter of Vin respectively. The resonant tank current, iLr,
Co. flows in the positive direction.

VCr(t) =VAR-nVollt +[nVollt +vCr(tO)-VAR]COSOJO(t-to) (3)

iLr(t) =_ _[VAB -nVollt +vcr(to)]sinOJo(t-to) (4)
61----11-----' This mode ends when iLr equals to the magnetizing current
C' ; c� (two -level � C�(dm'c -level) and 2("�(rlVc - b'Cl)
During tl < t < t2, SI, S2, S7 and Sg are still closed. VAB is still
Figure 3: Equivalent circuit for determining the magnetizing inductance. equal to Vin. The output rectifiers Drl and Dr4 turn-off softly
under the resonant process, no high dildt exists and thus the
balanced. In order to tackle the problem, an additional linear reverse recovery current is limited. As a result, no energy can
capacitor is added to each of the drain-source terminals of the be transferred to the secondary side as the resonant tank current
MOSFETs to diminish the non-linear effect of Cds. This helps is smaller than and limited to iLm. The converter enters to the
to share the voltages between the MOSFETs comparatively circulating stage. iLr equals to iLm and the rate of change of iLm
unifonn. The detail operation within half of a switching cycle depends on the voltage on Vpri and the magnetizing inductance
will be explained with the example of two-level modulation of the transfonner. This stage should keep short in order to
and the analysis can be extended to three-level and five-level minimize the conduction losses.
modulation strategies as well. In those cases the magnitude of
vAB has to be changed to O.5x VOU! and 0. 25x VOU! for three-level ( 5)
and five-level modulation strategies.
Figure 3 shows the equivalent circuit to determine the min­
imum magnetizing current for fully charge and discharge all (6)
the capacitors during the switching transient for the three mod­
ulation strategies. The minimum magnetizing current can be
This mode ends when the gate signal of Sb S2, S7 and Sg are
detennined as follow and summarized into Table I.
il Vds Cds eqv During t2 < t < t3, all the switches are open in this operating
JLm,lll. O =-"'----'.:.:.=.:'--..: (2)
mode, the Cds of SI, S2, S7 and Ss is charged and the output ca­
pacitance of S3 to S6 is discharged by iLm. Therefore, the dura­
From Table I, the required hm,mi" for the five-level modula­ tion of this mode depends on the magnitude of the iLm and the
tion is the maximum and thus the design of the magnetizing equivalent capacitance of the loop. The equivalent circuit of
inductance of the transfonner has to be based on this modula­ this mode is shown in Figure 3 where C! is the parasitic tennin­
tion strategy also. The description of the five-level resonant al capacitor of the transformer. This mode ends when VSb VS2,
converter working in two-level modulation is given below with VS7 and VSg equal to a quarter of Vi" and VS3 to VS6 equal to zero.
the assistance of the timing diagram which is shown in Figure The converter is still in a circulating stage and thus no energy
2. is transferred to the secondary side. In order to simplity the
During the period to < t < tl, SJ, S2, S7 and Sg are closed, the calculation, iLm is considered unchanged as the change in iLm is
other switches are open and VAB equals to Vin. Energy is trans­ very small and the duration of this mode is very short.
ferring from the primary side to the secondary side through the
excitation of the resonant tank by the voltage difference be­
iLr (t) =iLn,(t) =ILm (7)
tween vAB and the sum of VCr and the voltage on the primary hm is defmed in Table 1.
winding of the transfonner, Vpri which is equal to the secondary
voltage reflected to the primary side, nVOU! when the output
diodes are conducted. The output rectifiers Drl and Dr4 are con­
ducting in this mode. Cds of S3 to S6 are already fully charged
Table I. Minimum required magnetizing current for fully charged and dis-
During t3 < t < t4, when VS3 to VS6 equal to zero and iLm is
ch arged theC'd, fi
or t he three modulattOn strategIes. still flowing in the positive direction, the body diodes of S3 to
Two-level Three-level Five-level S6 conduct and clamp the drain-source voltages to zero. As VS3
Ceq" O.S(Cd• +2C,) Cd, + 2C, 2Cd, +C, to VS6 equal to zero, VSb VS2, VS7 and Vss are clamped to a quarter
of Vi". The resonant tank is excited by VCr and started a resonant
L'l.VCd, V:n O.Sv,,, 0.2SV,,,
process. As VS3 to VS6 are clamped to zero, gate signals of S3 to
(Cd. +2C,)V,,, (Cd, +C,)v,,, (Cd, + 0.5C,)v,,, S6 should be applied to tum-on the switches in zero-voltage
2L'l.t 2L'l.t 2L'l.t condition before the current direction of iLr reverses polarity.
0.5 Vi" 0.25 Vi" The output rectifiers Dr2 and Dr3 are conducting and this mode
VL1l1 Vin
ends when the gate signals of S3 to S6 are applied. As VAB
Vab Vin 0.5 Vin 0.25 Vin

S, S, s,

S"S, s s.
i" ",
S, ,----s::--'


i 'n, 'so,
InlrlJllo : i.l1,.i i i

s.. n.. ,..

.. !
1 _ _ • _ I , • • I
" �--, r�-,��,��-T�--i,-���-.
'". '
ltSS. VStt

"2 ::i .,-
---- - -- --\

Figure 5: Key waveforms of five-level modulation strategy,

is in the negative direction. Dr2 and Dr3 are conducting in this

Figure 4: Key waveforms of three-level modulation strategy,
Tn mode 3 [t2 - t3], Figure 6 (c), the second positive half
cycle takes place. The operation is equal to mode 1 but VAB is

+ [VC,(t3 )-nVOIII ] cos aJ O ( t-t3 )

equals to zero, the resonance is triggered by the voltage differ­
ence betweenVCr andVpti- supplied byVCss!'
The operation of mode 4, [t3 - t4], mode 6, [ts - t6], and
vc,(t) nVOlll

(9) mode 8, [t7 - ts], are equal to mode 2, Figure 6 (b).

In mode 5 [t4 - ts], Figure 6 (d), a third positive resonant
half cycle occurs. S3, S4, S6 and Ss are closed and the rest of the
devices are open. VAB is equal to the difference between VCin2
(10) andVCssz. SinceVCinl is equal to half of Vin andVCssz is equal to a
+ iL,(t3 ) cos aJo(t-t3) quarter of Ti", v AB is equal to a quarter of Tin. Cin is discharged
and Css2 is charged. Drl and Dr4 conduct in this mode. iLr is in
These are the operation modes for the positive half switch­ the positive direction.
ing cycle and the operation of the negative half switching cycle
is the same but opposite in polarity. Tn mode 7 [t6 - t7], Figure 6 (e), the final positive half cycle
of the complete switching cycle takes place. The operation is
B. Five-level Modulation equal to mode 5 butVAB is supplied byVCss2.
Figure 5 and Figure 6 show the key waveforms and operat­
ing modes of the converter with the proposed five-level mod­ IV. SIMPLIFIED DESIGN GUIDELINES FOR THE PROPOSED
ulation. As mentioned before the operation is similar to the FIVE-LEVEL RESONANT CONVERTER
two-level modulation but the voltage level of v AB is only a
• Determination of the switching frequency,.!;:
quarter of Vin• This can be realized by utilizing the input and
flying capacitors, Cin and Css. together with the switching strat­ The switching frequency of the converter is determined
egy. Therefore, the voltage balancing between the MOSFETs is based on the total losses of the switches and the transformer. In
not sensitive to the tolerances of the Cds under the aid of Cin general, a higher switching frequency selection results in a
and Css. lower magnetic flux, thus the core size, as well as the core loss,
can be reduced. However, higher the switching frequency also
In mode 1 [to - td, Figure 6 (a), the first positive half cycle,
results in higher AC loss on the winding of the transformer and
SJ, S3, Ss and S6 are closed and the other devices are open. v AB
tum-off loss on the switches which penalizes the converter
is equal to the difference between VCin! and VCss!' Since VCin! is
efficiency. As a result, the selection of the switching frequency
equal to half of Vin and VCssl is equal to a quarter of Tin, VAB is
is a compromise of these two effects. Those depend on the
equal to a quarter of Tin. During this period, Cin is providing the
power rating, semiconductor type and operating range of the
energy and Cui is been charged at the same time. Drl and Dr4
conduct in this mode since iLr is in the positive direction.
• Determination of the resonant tank frequency:
Tn mode 2 [tl - tz], Figure 6 (b), the negative half cycle, S3, S4,
Ss and S6 are closed and the other devices are open. The reso­ Tn order to minimize the resistive losses, the duration of the
nant capacitor voltage, VCr, becomes the source of the reson­ circulating stages, mode 2 - mode 3, shown in Figure 2, should
ance process. The DC value of theVCr equals to half OfVAB. iLr

'.j,,;."� Dd Dr1
it.. . iz... ':i:'s .
v B ... L. � CtIIIl' Rioad "DIll
t--- "AB L .. r'r"''----; C"", RbJd V0Iif


(a) Mode 1 [10 - Id.

(e) Mode 7 [16 - 1,].
Figure 6: Operating modes of the five-level modulation strategy.

be minimized. This can be achieved setting the frequency ratio,

in, of the switching frequency, Is, to the resonant frequency of
the resonant tank,.!;, smaller than but close to unity.
iLm ':,::'J .
.... s L.., c_ R..., v�

• + Determination of the transformer's turns ratio

c, As the converter is designed to operate in open loop and in
an operating point insensitive to load variations, the turns ratio
of the transformer will be defmed by the critical output and
(b) Mode 2 [II - 12], mode 4 [11 - I.], mode 6 [15 - 10] and mode 8 [17 - Is]. input voltages defined by the given specifications. For this pa­
per, the critical conditions are minimum input voltage and
maximum output voltage.
L• ..
e.u, .A

j ."
L. C"'" R"; • Determination of the minimum magnetizing current,
¢ S,
hm,mim and magnetizing inductance of the transformer, Lm:
S, - "('f
. The maximum magnetizing current is determined based on
the need to fully charge and discharge the parasitic Cds of the
MOSFETs and the transformer equivalent capacitance during
the time t2 < t < t3 as shown in Figure 2. By using Table T, one
can conclude that the magnetizing current for five-level mod­
(c) Mode 3 [12 IJ]. -
ulation is the most demanding. It is reproduced here for con­
T, /I,.t
Irm,min =8 (13)
2 Cds + C
• Determination of the Q factor:
it.z" �/'::jf

r-s.JJ -
B L"'I COlli Rb:Jd v(Mjf
" In order to minimize the circulating energy and rms current a
small quality factor value, Q for rated power should be set. Q =

0.2 is a desired value[10].

- - c,
• Determination of the resonant tank, Lr and Cr:
With the information of turns ratio and Lm, the transformer
(d) Mode 5 [t. - t5]. can be built. In order to increase the power density of the con­
verter, the leakage inductance of the transformer is utilized as
the resonant inductor, Lr, rather than using an additional induc-

� III " II I � ::�:]
tor. Therefore, the resonant capacitor, C, can be determined by
the measured value of Lr and (8),

�l II II II j' ')

• Determination of the flying capacitors, Css:


I I I I VQ"'�I
1'-'II -.
Css is part of the energy source for the resonant for three­
level and five-level modulations. The voltage variation on Css
will be reflected on the drain-source voltage of the switches in
those modulation modes. Therefore, by setting allowable vol­
tage variation across the capacitor, L1VCs" the capacitance of Css VQ •• 8
- V; '.
can be determined as follow: 7


!\ A f\ f\ Ad"V'' = :-
where k is the allowable percentage of voltage variation on VCss'

'I;�� \J V V V

The proposed converter and modulation scheme are theo­ �

retically verified by simulation using Matlab and Plecs. Figure

7 shows the simulation results of the key waveforms of the
proposed converter at an operating condition of 17k W and
ISOkHz resonant frequency. The switching pattern of the gate

signals is modified according to the modulation scheme. It is ______ --
v'" --,

I -
important to observe that the operating frequency of the reso­ (b)

�l II
nant tank remains unchanged. The output voltage is set to
66SV, 333V and 16SV for the two-level, three-level and five-

�lll II 'J
- V;._

.. .
�l II II

�l II II - ,
v�. 611


]ItII� ,.. - jI

f\ f\ /\ (\ f\, (\

G J \ 1 - Ir"
r \J VVV' VVV \J 1


- v...,




Figure 7: Simulation results of the key waveforms for the three modulations (a)
two-level, (b) three-level and (e) five-level modulations.

Table II. Design parameters and resulting component values for the resonant
converter prototype. "

�\ r,,
Items Value Items Value
;; 150kHz Cd, 2.04nF
n 0.58 C, l20pF ,
,, ,,
f" 0.95 LIt 600ns ,
:, :, I

j,. 158kHz Lm 100J.lH , , ,

C, L, : l
1.65J.lF 0.62J.lH I

C,] and C,,2 (with k= 0.1)


Dd -D,.

4 x IRFP4768PbF APT2xlOIDQI20J

S1-S, ,,


11 1
- - - - - - -
""'rr --,---.- -,- -,- -.-- .- -r- --rr_="".=
__ _ =;]
_ ""
:, '
,, .
_'Hh"'... , :
/\ _100 ..
.., "
f <-...
i \

• 00'
� ..
: ! \ "\
, , \ : Figure 10: Experimental key waveforms with the proposed five-level modula­
\ ;
1 '

� � i ·.......

............ '>••"a.r
J : ,

, :: t,t :'.� :.
.1 , I
: ; :, . - '..
: '"
,f ,
I l� �'
, r I I I "

, 'j:
.-5 H
: .>1'
,: . I '; i
��� tl ;�
: �
: , ." ,
e� ! li ,ru n,hili I' Ii..... Uf.;' j

i U:....'t
�$i 'I Ii Ii!) 'I¢Ii Il: Ii q.,.. q: * pI,�
j5l'l ; IiIi PYY

..' ;-
1.6 , B :!I !I!- ,� 150
I) (IS ! •
FIv.-ln.1 mQdulJidon. P0.1. • 5kW

Figure 8: Experimental key waveforms with the proposed two-level modula­ I� " •• ; Iii "T: Till; if t1Z 1. II • :.
__ �.S,.I. 1 nl.�."_1 ::-r-. -,••
u II l I 1 l .i
ii • J.!
l\ .�'

. \
\ \'.-48
Figure 11: Experimental output voltage and current waveforms of two-level
(top), three-level (middle) and five-level (bottom) modulations.

Therefore, the second stage buck type converter is only respon­

sible to regulate the output voltages between 80V to 150V for
163V input, 150V to 300V for 325V input and 300V to 600V
for 650V input. Taking in account that the input/output voltage
ratios for the buck type converter are almost the same for the
three operating ranges; the duty ratios, as well as the output
current ripple, are almost the same for the three cases. This
feature helps to simply the design of the buck type converter as
\ i
the operating range and condition are limited and similar in the
�I three cases. The component values for the resonant converter
are determined based on the design guidelines given in Section
.. ' IV and summarized in Table II.
Figure 9: Experimental key waveforms with the proposed three-level modula­ Figure 8, Figure 9 and Figure 10 show the experimental key
waveforms and the output voltage and current waveforms of
resonant converter with two-, three- and five-level modulation
level modulations respectively and is closely matched with the
strategies. Figure 10 shows that the voltage level of VAB is
theoretical prediction of equation (1).
around 750V, 375V and 188V respectively. The experimental
A 17kW, 750V input voltage, 80V to 650V output voltage measurement is closely matched with the theoretical prediction
converter has been built to verifY the theoretical prediction. which is summarized in Table I. Similarly, Figure 11 shows
The converter consists of two stages; the front stage is the that the output voltage is about 600V, 295V and 150V for the
150kHz five-level half-bridge LLC resonant dc-de converter; three modulation strategies. Figure 12 shows the efficiency of
and the second stage is a buck type converter. The front stage the proposed power electronic converter.
converter can deliver three different output voltages according
to the modulation strategies; these are 650V, 325V and 163Y.


9250 , .

- .�J '
' ,


-- Buck type .::on'"Cl1cr
.,00 --+-Tow
(a) (b)
Figure 13: Photos of the experimental prototype (a) the proposed 5-level reso­
50 100 ISO 200 250 300 j50 -400 HO 500 550 600 650
nant converter and (b) buck derived converter.

Figure 12: Efficiency curves of the proposed five-level resonant converter operations of the converter are in good agreement with theoret­
with the proposed modulation strategies. ical prediction.
It is important to mention that the design of the resonant REFERENCES
converter is simple as it only operates at the optimal operating [1] M. Kheraluwala, R. Gascoigne, D. Divan, and E. Baumann,
point. Tn this way, the circulating and rms current in the con­ "Performance characterization of a high-power dual active bridge DC­
verter are minimized allowing a positive impact in the design to-DC converter," IEEE Trans. on Industry Applications, vol. 28, no. 6,
of the transformer. As mentioned, the voltage steps feature pp. 1294-1301, Nov.lDec. 1992.
provided by the resonant converter also result in a simplifica­ [2] L. Yang, T. Zhao and A. Huang, "Design and Analysis of a 270kW
tion in the design of the second stage converter. As a result, the Five-level DCIDC Converter for Solid State Transformer Using 19kV
SiC Power Devices," in Proc. of the IEEE Power Electronics specialists
overall system will present high efficiency as shown in Figure Conference (PESC '07), June 2007, 00. 245-251.
12, and power density despite of the sever output voltage varia­
[3] Y. Nomura, "Power Supply device for Electromotive Railcar," US
tions. Patent 6 399 904, 2002.
Finally, Figure 13 shows the experimental prototype. Fig­ [4] R. Steigerwald, "A comparison of half-bridge resonant converter
topologies," IEEE Trans. on Power Electronics, vol. 3, no. 2, pp. 174-
ure 13 (a) shows the primary side of the proposed five-level 182, April 1988.
resonant converter and Figure 13 (b) shows the secondary side
[5] R. P. Severns, "Topologies for three-element resonant converters," IEEE
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