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CMPE 413
Interconnect
Analysis of interconnect is becoming as important as transistors in modern processes.
Modern processes use 6-10 metal layers
Layer T (nm) W (nm) S (nm) AR
Layer stack for 180nm process
Pitch = w + s
Aspect Ratio = t / w
Newer processes have AR ~ 2
2
1
860
2.0
1600
800
800
2.0
540
540
2.0
320
320
2.2
320
320
2.2
250
250
1.9
1000
3
l
860
1000
5
1720
1080
700
700
700
700
700
480
800
Substrate
CMPE 413
Wire Resistance
w
l
w
= resistivity ( m )
l
R = --- ---- = R
tw
R
l
---w
sheet resistance
CMPE 413
Wire Resistance
Older processes used aluminum, today's processes use copper
Special barrier layer required to stop copper from diffusing into silicon and destroying
transistors
Typical sheet resistance values in 180nm process
Layer
Diffusion (silicided)
Sheet Resistance
3-10
Diffusion (unsilicided)
50-200
Polysilicon (silicided)
3-10
Polysilicon (unsilicided)
50-400
Metal1
0.08
Metal2
0.05
Metal3
0.05
Metal4
0.03
Metal5
0.02
Metal6
0.02
3
CMPE 413
Contact Resistance
Contacts and vias also have about 2-20
of resistance.
CMPE 413
Wire Capacitance
Wire have capacitance per unit length to neighboring layers and layers above and below
Ctotal = Cbottom + Ctop + 2Cadjacent
s
w
layer n+1
h2
Ctop
layer n
t
h1
Cbot
Cadj
layer n-1
CMPE 413
Wire Capacitance
Dielectric constant in the previous equation
= k 0
350
300
M1, M3 planes
s = 320
s = 480
s=
200
s = 640
Isolated
s = 320
150
s = 480
s = 640
100
s=
Ctotal (aF/m)
250
50
0
0
500
1000
1500
2000
w (nm)
CMPE 413
CMPE 413
N segments
R
R/N
R/N
C/N
C/N
R
C
L-model
C/2
R/N
R/N
C/N
C/N
R/2 R/2
C/2
-model
C
T-model
CMPE 413
260
260
260
167 fF 167 fF
167 fF 167 fF
167 fF 167 fF
Estimate delay of 10x inverter driving a 2x inverter at the end of the above wire
R = 2.5k m for gates
Unit inverter: 0.36 m for NMOS, 0.72 m for PMOS
781
690
Driver
500 fF 500 fF
Wire
4 fF
tpd = 1.1 ns
Load
CMPE 413
Crosstalk
A capacitor does not like to change its voltage instantaneously
A wire has high capacitance to its neighbor
When neighbor switches from 1-> 0 or 0 -> 1 the wire tends to switch too
Called capacitive coupling or crosstalk
Effects: Noise on non-switching wires and increased delay on switching wires
Assume wires above and below on average are quiet and therefor second terminal of capacitor can be ignored
Modeled as Cgnd = Ctop + Cbottom
A
Cgnd
B
Cadj
Cgnd
DV
Ceff(A)
MCF
constant
VDD
Cgnd + Cadjacent
Cgnd
2VDD
Cgnd + 2Cadjacent
2
10
CMPE 413
Crosstalk
Crosstalk causes noise on non-switching wires
If the victim is floating
model as capacitive voltage divider
Aggressor
Vaggressor
Cadj
Victim
Cgnd-v
Vvictim
C adj
V victim = -------------------------------------- V aggressor
C
+ C adj
gnd v
11
CMPE 413
Aggressor
Cgnd-a
Vaggressor
Cadj
Rvictim
Victim
Vvictim
Cgnd-v
C adj
1
V victim = --------------------------------------- ------------ V aggressor
C gnd v + C adj 1 + k
R aggressor ( C
+ C adj )
aggressor
gnd a
k = ------------------------- = ---------------------------------------------------------------------- victim
+ C adj )
R victim ( C
gnd v
12
CMPE 413
1.8
1.5
1.2
0.9
0.6
0.3
0
0
200
400
600
800
1000
1200
1400
1800
2000
t(ps)
13
CMPE 413
Crosstalk noise
Noise implications:
If the noise is less than the noise margin nothing happens
Static CMOS logic will eventually settle to correct output even if disturbed by a large
noise spike
But these glitches cause extra delay
Also causes extra power from false transitions
Dynamic logic (discussed later) will never recover from noise
Memories and other sensitive circuits can also produce wrong answers
14
CMPE 413
Wire Engineering
Goal: Achieve delay, area and power specifications with acceptable noise
Degrees of freedom
Width, Spacing, Layer and Shielding
0.8
1.8
0.7
2.0
1.6
Delay (ns):RC/2
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.6
WireSpacing
(nm)
320
480
640
0.5
0.4
0.3
0.2
0.1
0
500
1000
1500
Pitch (nm)
vdd a0
a1 gnd a2
a3 vdd
2000
500
1000
1500
2000
Pitch (nm)
a0
b0
a1
b1
a2
b2
15
CMPE 413
Repeaters
R and C are proportional to l
RC delay is proportional to l2
Unacceptably high for long wires
Break long wires into N shorter segments
Drive each segment with an inverter or buffer
Wire Length: l
Driver
Receiver
N Segments
Segment
l/N
Driver
l/N
Repeater
l/N
Repeater
Repeater
Receiver
16
CMPE 413
Repeaters
How many repeaters should we use?
How large should each one be?
Equivalent circuit
Wire length l
Wire capacitance Cw * l, Resistance Rw * l
Inverter width W (NMOS = W, PMOS = 2W)
Gate capacitance C`* W, Resistance R / W
RwlN
R/W
Cwl/2N Cwl/2N
C'W
17
CMPE 413
Repeaters
Write equation for Elmore Delay
Differentiate with respect to W and N
Set equal to 0 and solve
Best length of wire between repeaters, neglecting diffusion parasitics
l
---- =
N
2RC'
--------------Rw Cw
RC w
-----------R w C'
18