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Product specification
UC3842
DESCRIPTION
PIN CONFIGURATIONS
N Package
COMP
VREF
VFB
VCC
ISENSE
OUTPUT
RT/CT
GROUND
TOP VIEW
D Package
COMP
14 VREF
NC
13 NC
12 V
CC
FEATURES
VFB
NC
11 V
C
ISENSE
10 OUTPUT
NC
GROUND
RT/CT
POWER GROUND
TOP VIEW
APPLICATIONS
BLOCK DIAGRAM
7(11)
(12)7
VCC
UVLO
34V
(9)5
S/R
GND
6V
V
8(14) REF
5.0V
50mA
5V
REF
16V
2.5V
INTERNAL
BIAS
(7)4
OSC
RT/CT
6(10)
OUTPUT
ERROR
AMP
VFB
(3)2
S
2R
R
PWM
LATCH
R
COMP
CURRENT
SENSE
(1)1
1V
CURRENT
SENSE
COMPARATOR
(5)3
5(8)
NOTE:
Pin numbers in parentheses refer to the D package.
1100
853-0614 13721
Product specification
UC3842
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
DWG #
0 to +70C
UC3842N
0404B
0 to +70C
UC3842D
0405B
PARAMETER
RATING
UNIT
VCC
Self-Limiting
VCC
Supply voltage
(low impedance source)
30
IOUT
Output current 2, 3
PD
-0.3 to 6.3
10
mA
-65 to +150
300
>70C)2
TSTG
TSOLD
Lead temperature
(soldering, 10sec max)
NOTES:
1. All voltages are with respect to Pin 5; all currents are positive into the specified terminal.
2. See section in application note on Power Dissipation Calculation.
3. This parameter is guaranteed, but not 100% tested in production.
1101
Product specification
UC3842
PARAMETER
TEST CONDITIONS
UC3842
UNIT
Min
Typ
Max
4.90
5.00
5.10
Reference section
VOUT
Output voltage
TJ=25C, IO=1mA
Line regulation
12VIN25V
20
mV
Load regulation
1IO20mA
25
mV
Temp.
stability1
Output noise
voltage1
0.2
Line, load, temp.
4.82
0.4
mV/C
5.18
V
V
10Hzf10kHz, TJ=25C
50
Long-term stability1
25
mV
Output short-circuit
TJ=25
-30
-100
-130
mA
Output short-circuit
-55<TJ0C
-30
-100
-180
mA
Initial accuracy
TJ=25C
47
52
57
kHz
Voltage stability
12VCC25V
0.2
Oscillator section
Temp.
stability1
Amplitude
TMINTJTMAX
VPIN 4 peak-to-peak
1.7
V Pin 1=2.5V
2.42
2VO4V
65
90
dB
MHz
AVOL
Unity gain
bandwidth1
ISINK
ISOURCE
TJ=25C
0.7
TMIN<TJ<TMAX
0.5
2.50
2.58
-0.3
-2
MHz
12VCC25V
60
70
dB
mA
mA
-0.5
-0.8
VOUT High
VOUT Low
0.7
1.1
2.85
3.15
V/V
0.9
1.1
VPIN 1=5V
12VCC25V
PSRR
IBIAS
-2
-10
Delay to output1
150
300
ns
1102
70
dB
Product specification
UC3842
PARAMETER
UC3842
TEST CONDITIONS
Min
Typ
Max
ISINK=20mA
0.1
0.4
ISINK=200mA
1.5
2.2
UNIT
Output section
VOL
Output Low-Level
VOH
Output High-Level
tR
Rise time
CL=1nF
50
150
ns
tF
Fall time
CL=1nF
50
150
ns
ISOURCE=20mA
13
13.5
ISOURCE=200mA
12
13.5
V
V
14.5
16
17.5
8.5
10
11.5
93
97
100
PWM section
Maximum duty cycle
Minimum duty cycle
0.5
mA
11
17
mA
ICC=25mA
34
400
kHz
NOTES:
1. These parameters, although guaranteed, are not 100% tested in production.
2. Parameter measured at trip point of latch with VPIN 2=0.
V PIN 1
3. Gain defined as:
; 0 V PIN 3 0.8V
A
V PIN 3
UNDERVOLTAGE LOCKOUT
2.5V
ON/OFF COMMAND
TO REST OF IC
VCC
0.5mA
+
ZI
2
VFB
VON
UC3842
16V
VOFF
10V
COMP
NOTE:
Error AMP can source or sink up to 0.5mA.
ICC
<15mA
<1mA
VOFF
VON
VCC
NOTE:
During Undervoltage Lock-Out, the output driver is biased to a high
impedance state. Pin 6 should be shunted to ground with a bleeder
resistor to prevent activating the power switch with output leakage current.
1103
Product specification
UC3842
IS
CURRENT
SENSE
COMPARATOR
R
1V
COMP
R
3
CURRENT
SENSE
RS
5
GND
NOTE:
Peak current (IS) is determined by the formula:
I
MAX
1.0V
Rs
45
80
0
Av
60
40
90
20
135
180
20
10
0
0.01
0.03 0.05 0.1
0.3 0.5 1.0
OUTPUT CURRENT, SOURCE OR SINK (A)
1104
45
100
1k 10k 100k 1M
FREQUENCY (Hz)
225
10M
PHASE (DEG)
100
Product specification
UC3842
RT
VCC
2N2222
4.7k
100k
UC3842
COMP
ERROR AMP
ADJUST
5k
ISENSE
ADJUST
0.1F
7
VCC
VFB
0.1F
1k
1W
3
4.7k
8
VREF
OUTPUT
OUTPUT
5
ISENSE
4
GND
RT/CT
GND
CT
NOTE:
High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to Pin 5 in a single point
ground. The transistor and 5k potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to Pin 3.
SHUTDOWN TECHNIQUES
4.7k
1
COMP
3
4.7k
SHUTDOWN
ISENSE
500
SHUTDOWN
TO CURRENT
SENSE RESISTOR
NOTE:
Shutdown of the UC3842 can be accomplished by two methods; either raise Pin 3 above 1V or pull Pin 1 below a voltage two diode drops above ground. Either method causes the
output of the PWM comparator to be high (refer to Block Diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown
condition at Pins 1 and/or 3 is removed. In the examples shown, an externally-latched shutdown may be accomplished by adding an SCR which will be reset by cycling
VCC below the lower UVLO threshold (10V). At this point all internal bias is removed, allowing the SCR to reset.
1105
Product specification
UC3842
USD735
+
4.7k
4W
220F
250V
673-3
0.01F
400V
56k
1W
4700F
10V
DC (5V 25A)
OUT
1N3613
AC
INPUT
1N3613
16V
10F
20V
VCC 7
20k
820pF
1N3613
0.01F
UC3842
2.5k
2
VFB
150k
27
OUT
UFN432
20k
COMP
3.6k
NOTES:
T1: Coilcraft E-4140-B
Primary 97 turns
single AWG24
Secondary 4 turns
4 parallel
AWG22
control 9 turns
3 parallel AWG28
100pF
CUR
SEN
8
VREF
10k
1k
470pF
0.85
4
RT/CT
0.01F
0.0047F
GND
ISOLATION
BOUNDARY
SPECIFICATIONS
Input line voltage:
NOTE:
This circuit uses a low-cost feedback scheme in which the DC
voltage developed from the primary-side control winding is sensed
by the UC3842 error amplifier. Load regulation is therefore
dependent on the coupling between secondary and control
windings, and on transformer leakage inductance. For applications
requiring better load regulation, a UC1901 Isolated Feedback
Generator can be used to directly sense the output voltage.
90VAC to 130VAC
Input frequency:
50 or 60Hz
Switching frequency:
40kHz10%
Output power:
25W maximum
Output voltage:
5V5%
Output current:
2 to 5A
Line regulation:
0.01%/V
Load regulation:
8%/A*
Efficiency @ 25 W,
VIN=90VAC:
70%
VIN=130VAC:
65%
2.5A average
1106
Product specification
UC3842
4
RA
RESET
7
VCC
DISCH
RB
NE555
OUT
RT/CT
4
UC3842
2 TRIG
6 THRESH
5
GND
GND
NOTES:
TO OTHER
UC3842s
1.44
f +
(R A )
2R B) C
MAX
RB
RA )
2R B
1107