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Digital System and IC Design

PART ONE

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System:

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Digital System!

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Digital system Design


System Design:
Large design broken down into sub design with specified characteristics
Eg :Digital computer

Logic Design:
Involves determining how to interconnect basic logic building blocks to
perform a specific function Eg :Binary Addition(Interconnection Logic and Flip Flop)

Circuit Design:
Interconnection such as resistors, Diodes, transistors

Switching Networks
Combinational
Sequential

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Combinational vs. Sequential

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Levels of integrated circuits

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Binary Valued Signals

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Binary Valued Signals contd

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Binary Valued Signals contd

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VLSI:

but why?

Integration improves the design:


lower parasitics = higher speed;
lower power;
physically smaller.
Integration reduces manufacturing cost-(almost) no
manual assembly.

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VLSI and you

Microprocessors:

personal computers;
microcontrollers.

DRAM/SRAM/flash.
Audio/video and other consumer
systems.
Telecommunications.
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Moores Law

Gordon Moore: co-founder of Intel.


Predicted that number of transistors per
chip would grow exponentially (double
every 18 months).
Exponential improvement in technology
is a natural trend: steam engines,
dynamos, automobiles. Moores Law
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Field-programmable gate arrays

FPGAs are programmable logic devices:

Logic elements + interconnect.


Provide multi-level logic.
LE
LE

LE

LE
Interconnect
network

LE

LE
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FPGAs and VLSI

FPGAs are standard parts:

Pre-manufactured, shorter design cycle.


Dont worry (much) about physical design.
Time to market is less, but FPGAs are slower,
larger, more power-hungry.

Custom silicon:

Tailored to your application.


Generally lower power consumption.
Time to market is more
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ASIC Design Flow


System Level Tools
Behavioral HDL
Behavioral Synthesis
Simulation (Behavioral/RTL)
Logic/Test synthesis)

Power Estimation
(RTL, Gate and Transistor Level)
Layout- Verification

Floor Planning & Placement

Static Timing Analysis


Even-Driven Cycle Based Sim:

no

Meets Timing

pre

Formal verification

Yes
Routing

Static Timing Analysis

Parasitic Extraction

Even-Driven Cycle Based Sim:

post

Formal verification
Meets Timing

no

In-Place optimization

Yes
LVS/DRC Sandeepani School of VLSI Design

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Embedded Digital System:

The big picture

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Number System & Conversions

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Examples
1.
2.
3.

(500.21)10 = ( ? )2
(436.71)8 = ( ? )16
Convert (231.3)Base 4 to Base 7
Convert Base 4 to Base 10
Convert Base 10 to Base 7
Ans : (63.515) Base 7
4. 3168 4518 = ?
5. CB2H 972H = ?
6. 0011.10012 0001.11102 = ?
7. 79 - 26 in BCD representation?
8. 5 - 8 in XS-3?
9. Divide (10)10 by (4)10 in binary representation.
10. Convert (847)10 to gray code representation.
11. Perform direct subtraction: (9)10 (10)10 ?

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Binary Arithmetic

Binary
Binary
Binary
Binary

Addition
Subtraction
multiplication
Division

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Boolean Algebra

THEOREMS:

AXIOMS :

DEFINITIONS:

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Problems
Perform the following number system
conversions:
a) (728)8 = ?16
b) 10111100.001010012 = ?8
c) 2AA216 = ?2
d) 201.128 = ?2 = ?16

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Problems
Prove

1.
2.
3.
4.

A + AB = A+B
Sum of products of three variables is equal to 1.
Product of sums of three variables is equal to 0.
ABC+ABC+ABC+ABC+ABC = AB+C

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Block Diagram of a Combinational Circuit

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Analysis of the Logic Network


x1
x2
x3

F= (x1 + x2) . x3

Simplified Logic Network


x1
x2

F= (x1 + x2)

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Analysis and Simplify the Logic Network

x1
x2

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Basic Gates

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Representation Of Numbers

Signed magnitude
1s Complement
2s Complement

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Signed magnitude representation

Humans use a signed-magnitude system: we add + or - in front of a


magnitude to indicate the sign.

We could do this in binary as well, by adding an extra sign bit to the


front of our numbers. By convention:

A 0 sign bit represents a positive number.

A 1 sign bit represents a negative number.


Examples:

11012 = 1310
0 1101 = +1310
1 1101 = -1310

01002 = 410
0 0100 = +410
1 0100 = -410

(a 4-bit unsigned number)


(a positive number in 5-bit signed magnitude)
(a negative number in 5-bit signed magnitude)

(a 4-bit unsigned number)


(a positive number in 5-bit signed magnitude)
(a negative number in 5-bit signed magnitude)
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Signed magnitude
operations

Negating a signed-magnitude number is trivial: just change the sign


bit from 0 to 1, or vice versa.
Adding numbers is difficult, though. Signed magnitude is basically
what people use, so think about the grade-school approach to
addition. Its based on comparing the signs of the augend and
addend:

If they have the same sign, add the magnitudes and keep that
sign.

If they have different signs, then subtract the smaller


magnitude from the larger one. The sign of the number with the
larger magnitude is the sign of the result.
This method of subtraction would lead to a rather complex circuit
5 13 17
6 4 7
+3 7 9
because
3 7 9
+ -6 4 7
2 6 8
-2 6 8
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Ones complement
representation

A different approach, ones complement, negates numbers by


complementing each bit of the number.
We keep the sign bits: 0 for positive numbers, and 1 for
negative. The sign bit is complemented along with the rest of
the bits.
Examples:

11012 = 1310 (a 4-bit unsigned number)


0 1101 = +1310 (a positive number in 5-bit ones complement)
1 0010 = -1310 (a negative number in 5-bit ones complement)
01002 = 410
0 0100 = +410
1 1011 = -410

(a 4-bit unsigned number)


(a positive number in 5-bit ones complement)
(a negative number in 5-bit ones complement)
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Why is it called ones


complement?

Complementing a single bit is equivalent to subtracting it from


1.
0 = 1, and 1 - 0 = 1

1 = 0, and 1 - 1 = 0

Similarly, complementing each bit of an n-bit number is


equivalent to subtracting that number from 2n-1.
For example, we can negate the 5-bit number 01101.

Here n=5, and 2n-1 = 3110 = 111112.

Subtracting 01101 from 11111 yields 10010:


1 1 1 1 1
- 01 1 01
1 00 1 0

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Ones complement
addition

To add ones complement numbers:

First do unsigned addition on the numbers, including the


sign bits.

Then take the carry out and add it to the sum.

Two examples:
1010
(-5)
0101
(+5)
+
0010 + (+2)
+
0010 + (+2)
1100
(-3)
0111
(+7)
0101
(-5)
0101
(+5)
+ 1101
(-2)
+ 1101
(-2)
1 0111
(-7)
1 0010
(+3)
1
1
1000
0011

This is simpler and more uniform than signed magnitude


addition.
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Twos
complement
Our final idea is twos complement. To negate a number, complement
each bit (just as for ones complement) and then add 1.

Examples:
11012 = 1310 (a 4-bit unsigned number)
0 1101 = +1310 (a positive number in 5-bit twos complement)
1 0010 = -1310 (a negative number in 5-bit ones complement)
1 0011 = -1310 (a negative number in 5-bit twos complement)

01002
0 0100
1 1011
1 1100

= 410
= +410
= -410
= -410

(a 4-bit unsigned number)


(a positive number in 5-bit twos complement)
(a negative number in 5-bit ones complement)
(a negative number in 5-bit twos complement)

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Twos complement Addition

0101
0010
0111

(+5)
+ (+2)
(+7)

0101
+ 1110
1 0011

(+5)
(-2)
(+3)

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1010
0010
1101

(-5)
+ (+2)
(-3)

0101
+ 1110
1 1001

(-5)
(-2)
(-7)

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Comparison
Sign and magnitude

1s complement

0111

+7

+7

+7

0110

+6

+6

+6

0101

+5

+5

+5

0100

+4

+4

+4

0011

+3

+3

+3

0010

+2

+2

+2

0001

+1

+1

+1

0000

+0

+0

+0

1000

-0

-7

-8

1001

-1

-6

-7

1010

-2

-5

-6

1011

-3

-4

-5

1100

-4

-3

-4

1101

-5

-2

-3

1110

-6

-1

-2

1111

-7

-0

-1

b3b2b1b0

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2s complement

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Problems
Perform
1. (6)10 (4)10 and
2. (4)10 (6)10 using 1`s complement
Perform
1. (6)10 (4)10 and
2. (4)10 (6)10 using 2`s complement

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Gates:

electronic circuit that realizes a logical expression

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Logical Expressions

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K-Maps

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Arithmetic Circuits
Adders:
Half adder
Full adder
Serial adder
Ripple carry adder
Carry look ahead adder

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Implementation of Half Adder

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Implementation of Full Adder

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4-Bit Ripple carry adder

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4-Bit Carry Adder-Subtractor

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Serial Adder
Xi

Si

Yi

Full Adder

Ci

Ci + 1

Delay

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Carry Look Ahead Adder

Generation and Propagation Circuit

CLA - Generation Circuit

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4-Bit Carry Look Ahead Adder

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BCD Adder

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2bit X 2bit Multiplier

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Magnitude Comparator
Q.

Design a 2-bit digital comparator that accepts two


words A and B and gives three outputs :
G(>),
E(=) and
L(<).

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Magnitude Comparator
Q.

Design a 4-bit digital comparator that accepts two


words A and B and gives three outputs :
G(>),
E(=) and
L(<).

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2-bit Magnitude Comparator


Answer:
let x1 = (A1 ex-nor B1)
x0 = (A0 ex-nor B0)

A=B

= x1. x0

A>B

= A1B1 + x1. A0 B0

A<B

= A1B1 + x1. A0 B0
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4-bit Magnitude Comparator


Answer:
Z

A=B

= x3. x2 . x1. x0

A>B

= A3B3 + x3. A2 B2 + x3. x2. A1B1 + x3. x2. x1. A0 B0

A<B

= A3B3 + x3. A2 B2 + x3. x2. A1B1 + x3. x2. x1. A0 B0

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4 Bit Magnitude Comparator

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Design a 3- way Light controller

Let x1, x2, x3 be the input variables that denote the state
of each switch . Assume light is off if all the switches are
open. Closing any one switch will turn the light on .Then
turning on the second switch will turn off the light.thus the
light will be on if exactly one switch is closed and it will be
off if two or no switches are closed.If the light is off when two
Switches are closed then it must be possible to turn the light
On by closing the third switch.

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Problems
Q.1. Design a circuit which will accept 4-bit binary and
will provide 5-bit BCD code?
Q.2. Design a 3-bit squarer?
Q.3. A circuit accepts a 4-bit I/p data & generates an o/p
Z=1whenever I/p is a prime number. Design the
circuit?

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Problems
Q.4. The conditions under which an insurance company
will issue a policy are :
A married female 25 years old or older, or
A female under 25 years or
A married male under 25 years with no accident record, or
A married male with accident record, or
A married male under 25 years or older with no accident
record.
Obtain a simplified logic expression starting to whom a
policy can be issued.

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Universal Logic Element

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Universal Logic Element


Which of these are Universal logic
elements?
1. 2:1 MUX
2. Ex-or2
3. {f(x,y)=xy}
4. {f(x,y,z)=(x+y)z}
5. Nand2

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Universal Logic Gate Introduction

A set of gates is said to be universal if any


combinational system can be implemented using
gates just from that set.

The set {AND,NOT} or {OR,NOT} is universal


. So any set of gates that can implement either
{AND,NOT} or {OR,NOT} is universal.

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Universal Logic gate : Nand2


Lets start with NAND gate.

NAND(x,y)= (xy) NAND(x,x)=(xx)=x NOT(x)=NAND(x,x)


NOT gate can be implemented by a NAND gate

AND(x,y)= xy = ((xy))=(NAND(x,y)) . From the previous step, we know


how to implement NOT gate by a NAND gate
AND(x,y)=(NAND(x,y))=NAND(NAND(x,y), NAND(x,y))

So,AND gate can be implemented by only using NAND gates


Since we can implement AND and NOT by only NAND gates,
{NAND, NOR} is a universal set,even without NOR gate.
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Universal Logic Gate NAND Function

NAND ::= Negative AND


Y = ( A B )

NOT

AND

A
B

A
Y
B AND 2

OR

A
B

A
B

INV

OR 2

A
B

A
B

A
B

A
Y

=
B

A
B
A
B

NAND 2

NAND 2

NAND 2

NAND 2

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Y
Y

Y
A
B

A
B

NAND 2

NAND 2

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Universal Logic Gate NOR Function

NOR ::= Negative OR


Y = ( A + B )

NOT
AND
OR

A
B

A
Y
B AND 2

A
B

INV

=
=

A
A
B

A
B

OR 2

A
B

A
B

A
B
A
B
A
B

NOR 2

NOR 2

NOR 2

NOR 2

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Y
Y
Y

Y
A
B

NOR 2

A
B

NOR 2

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Universal Logic Gate


Multiplexor Function

Multiplexor
Y = A S + B S

OR

NOT
A

AND

A
B
VCC

VCC

Y
D0 S1 S0
GND
D1
Y
D2 MX4
D3

A
B
D0
D1

S1 S0

D2 MX4
D3

GND

GND

VCC

D0
D1

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S1 S0

D2 MX4
D3

Y
GND

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Basic Data Processing Circuits

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Decoder (3:8)

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2-4 line Decoder with Enable Input

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Problems using Decoder


Q. Implement 4:16 Decoder using two 3:8 Decoders
Q. Realize a full adder using one 3:8 decoder &
residual gates

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4:16 Decoder using 3:8 Decoder

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Full Adder using Decoder

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Problems using Decoder


Q. Design BCD to decimal

with false data rejected

with false data accepted

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Encoder

Decimal-to-BCD Encoder

Octal-to-Binary Encoder

Limitations

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Multiplexer

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4:1 line Multiplexer

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Problems
Q. Realize the following using only one 2:1 Mux
1.
2.
3.
4.
5.
6.

NOT
And2
OR2
Ex-or2
Ex-nor2
Latch

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Problems
Q. Show how two 2-to-1 multiplexers (with no added
gates) could be connected to form a 3-to-1 MUX.
Input selection should be as follows:
If AB = 00, select Io
If AB = 01, select I1
If AB = 1 (B is don`t care), select I2.

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Problems
Q. 1. Realize the function F(A,B,C,D)=m(1,2,3,6,8,9,11,14)
using an 8-to-1 MUX with control inputs A,B, and C.
2. Repeat Q.1 with control inputs A,C, and D.
3. Repeat Q.1 using a 4-to-1 MUX and added gates.

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Problems
Q1. Design a sequence generator that generates
the sequence 11100011.
Q2. Design 1:8 demultiplexer using two 1:4
demultiplexers.
Q3. Implement the following boolean function
using 8:1 MUX,
F(A,B,C,D) = (0,1,3,4,8,9,15)

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Buffer
A Buffer is a logic circuit which has one I/p line &
one output line.
It is a current amplifier & also called as driver.

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Tri-State Buffer

Q. Implement a 2-to-1 Mux with Tri-state buffers

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Answer

2-1 line Mux

2-1 line Mux with Tri-state buffer

Or

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Sequential circuits

Combinational.

Output depends only on current input values.

Sequential.

Output depends on current input values and


present state of the circuit, where the present
state of the circuit is the current value of the
devices memory.

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Bistable Elements

The simplest sequential circuit.


It consist of a pair of inverters connected as
shown below. Notice the feedback loop.

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Digital Analysis

Two stable states.


If Q is HIGH then the lower inverter has a HIGH at its
input and a LOW at its output. This in turn forces the
upper inverters input to be LOW and its output to be
HIGH.
If Q is LOW then the lower inverter has a LOW at its
input and a HIGH at its output. This in turn forces
the upper inverters input to be HIGH and its output
to be LOW.

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Latches and Flip-Flops

Binary cells capable of storing 1 bit of


information.
Generates one of two possible stable states.
Two outputs labeled Q and Q.
One or more inputs.
These sequential devices differ in the way
their outputs are changed:
The output of a latch changes independent
of a clocking signal.
The output of a flipflop changes at specific
times determined by a clocking signal.

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SR Latch with Control Input

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D Latch

This latch eliminates the problem that


occurs in the SR latch when R=S=0.
C is an enable input:
When C=1 then the output follows the
input D and the latch is said to be open.
Due to this fact this latch is also called
transparent latch.
When C=0 then the output retains its
last value and the latch is said to be
closed.

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Edge Triggered D Flip-Flop

This flip-flop is made out of two D latches. The first latch is


the master, and the second the slave.
When CLK_L = 1 the master is open and the slave is closed.
Qm and Ds follow Dm .

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Edge Triggered D Flip-Flop

When CLK_L = 0 the master is closed, the slave is open and


Qm is transferred to Qs . Note that Qs does not change if Dm
changes because the master latch is closed leaving Qm fixed.

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Edge Triggered D Flip-Flop

Positive edge-triggered D flip-flop.


Q* = D

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JK Flip Flop

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Excitation table of Flip Flops

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Flip Flop to Flip Flop conversions

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FF FF conversions
1.
2.
3.
4.
5.
6.
7.

D-T
T-D
D-JK
D-SR
T-SR
JK-SR
SR-JK

D=TQ
T=DQ
D=QJ+QK

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D from JK Flip Flop

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Sequential Circuit Example

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Problems
Q. Design a circuit that generates two waveforms of 90 phase shift.
Q. Design a 50% duty cycle frequency doubler for an input
clk pulse of 50% duty cycle.
More Problems, Many more Problems. Let us continue!

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Timing Issues

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Timing Issues

Timing parameters
Timing diagram
Set up time
Hold time
Clock Skew
Slack
Critical path
Maximum Frequency of Operation

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Timing parameters

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Timing parameterscontd

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Timing parameterscontd

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Timing diagram

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Setup and Hold Time

Setup and hold time define a window of time which the D input must
valid and stable in order to assure valid data on the Q output.

be

Setup Time (Tsu) Setup time is the time that the D input must be valid before the
Flip-Flop samples.
Hold Time (Th) Hold time is the time that D input must be maintained valid after the
Flip-Flop samples.
Propagation Delay (Tpd) Propagation delay is the time that takes to the sampled D
input to propagate to the Q output.
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Clock Skew

Synchronous systems using edge triggered flip-flops work


properly only if all flip-flops see the triggering edge at the
same time.
The difference between arrival times of the clock at different
devices is called clock skew.
Q2

Q1

IN
FF1

FF2
CLOCKD

CLK

A LONG SLOW PATH

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Slack
AT

At each node is a group of events


modeling signal transitions

RT

Q
QB

SLEW

Arrival Time (AT) - when the signal arrives


Required Time (RT) - when the signal is needed
Slew (SLEW) - time for signal transition from logic levels
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Slack
Q. Am I meeting timing at this node?
AT

+SLACK

RT

SLEW

SLACK = RT - AT

Timing is met when slack is greater than or equal to zero

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Maximum Operating Frequency

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Recap
Shift registers: SISO, PISO, PIPO, SIPO
Shift register counters- ring counters and twisted ring counters
Asynchronous/ synchronous counters

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Solve these:
Q1: Design a JK counter that goes through the states
1,2,3,6,7,8,11,13,1, Implement the circuit and avoid locout condition
Q2. Design a MOD 5 counter (divide by 5) counter using JK
flip-flop. Also construct the timing diagram. Also draw the
timing diagram of MOD 10 counter.

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Solve these: contd


Q3. Design a asynchronous MOD 10 (decade) counter.
Q4. Design a non-sequential ripple counter, which will go
through the states 3,5,7,8,9,10,3,..
Q5. Determine fmax for the 4-bit synchronous counter if tpd for
each flip-flop is 50 ns and tpd for each AND gate is 20 ns.
Compare this with fmax for a MOD-16 ripple counter.

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Interesting Problems:
Q1. Design a divide-by-3 counter with 50% duty cycle?

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Interesting Problems: contd


Q2. Design a divide-by 1.5 counter?
Q3. Design a black box whose input clock and
output relationship as shown in diagram
below.

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Finite State Machines

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Topics
FSM Basics
Types of Machines
Example Designs

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Finite State Machines

Finite state machines are so named because the sequential


logic that implements them can be in only a fixed number
of possible states.
FSM is a systematic way of specifying any
sequential logic.
Ideally suited for complex sequential logic.

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What is an FSM?
Design Specification Point of View

State machines are a means of specifying


sequential circuits which are generally
complex in their transition sequence
and depend on several control inputs.

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What is an FSM?
Digital Circuit Point of View

State machines are a group of flip-flops, whose


group-state transition pattern from one set of
values to another and depends on several control
inputs

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FSM Structure
CURRENT
STATE

CONTROL
INPUTS

COMB.
LOGIC
for
NEXT
STATE

NEXT
STATE

MEALY

CURRENT
STATE

OUTPUTS
STATE
REGISTER
FLIP-FLOPS

COMBO. FOR
OUTPUT

CLOCK
ASYNC
CONTROL

PORTS

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Mealy Machine

The outputs depend on the current state and


the present value of the inputs.
Mealy outputs are asynchronous and can
change in response to any changes in the
inputs, independent of the clock.
Glitches-How to avoid?
Require less no. of states compared to
Moore Machine.
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Moore Machine

The outputs depend only on the present


state.
The outputs are computed by a
combinational logic block whose only
inputs are the flip-flops' state outputs
The outputs change synchronously with the
state transition and the clock edge.
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Finite state machine


FSM Structure:. State register
- Stores current state
. Next state decoder logic (A)
- Decides next state based on
current state and inputs
. Output logic (B)
-Decodes state (or states and
inputs) to produce outputs

A
c1k

c1k
.Outputs from the FSM can be a
function of:
- Current state only (moore)
- Current state and the current
inputs (Mealy)
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Moore FSM

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FSM Design examples


Q1. Design a circuit that asserts its single output
whenever its input string has two 1's in
sequence.
Cases:
(i) Non-overlapping
(ii) Overlapping of sequence

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FSM Design examples


Q2. Assume a stream of 50k bits are given to the
circuit whose output Z=1 when no. of 1`s in
50k bits are odd else Z = 0. Design the
circuit. (using Mealy machine)

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FSM Design examples


Q3. Design a circuit to detect a sequence 010 and
1001
(i) non-overlapping
(ii) overlapping
using Mealy machine or Moore.

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FSM Design examples


Q4. A sequential circuit accepts two i/p`s X & Y
and generates an o/p Z = 1 whenever the i/p`s
are equal for consecutive 4 clock cycle.
Design a Mealy machine.(check overlapping
)
Note: If any state machine has n inputs, no.
of arrows leaving the state will be 2n .
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FSM Design examples


Q6. A sequential circuit has one I/p and one o/p. when
I/p sequence 110 occurs the o/p becomes 1 and
remains 1 until the sequence 110 occurs in
which case the o/p returns to zero. The output
remains zero until 110 occurs the third time.
Draw the state diagram and state table.

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Problems, more problems


Q. Design a pulse train generator circuit
using shift register for the following pulse
train:
1 0 0 0 1 1 0
Next Question: Now can you design a circuit to
generate a specified waveform.

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Introduction Memories

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Classification
MEMORY

RAM

HYBRID

ROM

SRAM

FLASH

PROM

DRAM

EEPROM

EPROM
MASKED

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Memory array architecture

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Latch and Register based Memory

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RAM

Types : SRAM & DRAM


Primary difference: lifetime of the data they
store.
Which to choose & on what basis?
Speed, Area & Cost.

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ROM

Types : MASKED, PROM & EPROM

They are class of PLD s.

Distinguished by the methods used to write new


data to them (usually called programming) and
the number of times they can be rewritten.

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ROM

MASKED : Programmed by manufacturer.

PROM : One time programmable.

EROM : Erased & re-programmable again & again.

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PLD s

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ROM

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ROM

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ROM

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HYBRID

Combine features of both

EEPROM: Once written, the new data will remain


in the device forever--or at least until it is
electrically erased.

FLASH: The major difference is that flash devices


can only be erased one sector at a time, not byteby-byte as in EEPROM.
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Comparison: memories
Type Volatile Writeable Erase Size Cost(per Byte) Speed
SRAM

Yes

DRAM

Yes

Yes
Yes

Byte

Expensive

Fast

Byte

Moderate

Moderate

Masked
RAM

No

PROM

No

EPROM

No

Yes

EEPROM No

Yes

FLASH

Yes

No

No
Only once

N/A

Inexpensive

Fast

N/A

Moderate

Fast

Moderate

Fast

Byte

Expensive

Fast

Sector

Moderate

Fast

Entire Chip

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