SERVICE MANUAL

Model:
LCT2701TD
Safety Instructions.....................................................................1~2
Production specification.........................................................3~11
LCD COMBO Connection...........................................................12
Panel Inverter Power............................................................ 13-29
Basic Operations & Circuit Description.....................................30
PCB Function...........................................................................31
PCB Failure Analysis................................................................32
Basic Operation of LCD-TV......................................................32
LCD Basic Display Theory........................................................33
LCD Panel................................................................................34
IC Descriptions.....................................................................35~64
LCD Panel specification.......................................................65~95
Exploded View Diagram.............................................................96
Spare parts list.....................................................................97~98
V-Chip Password.......................................................................99
Software Upgrade................................................................99~100

This manual is the latest at the time of printing, and does not
include the modification which may be made after the printing,
by the constant improvement of product.

I. Safety Instructions
The l ig h tn i ng fla sh w i th arro wh e ad symb ol ,
within an equilatera l triangle, is intended to alert
the user to the presence of uninsulated dangerous
voltage within the prod uct s enclosure that may
be of sufficie nt mag nitud e to consti tute a risk of
electric shock to persons.

CAUTION
RISK O F ELECT RIC SHO CK
DO NO T O PEN

The excla mati on po i nt wi thi n a n e q ui l ate ra l

tri a n gl e is i nte n de d to a le rt th e u se r to th e
presence of important operating and maintenance
(s e rv i ci n g ) i n str u ct i o n s i n th e l i te r a tu re
accompanying the appliance.

CAUTION: TO REDUCE THE RISK OF ELECTRIC

SHOCK, DO NOT REMOVE COVER (OR BACK). NO
USER-SERVICEABLE PARTSINSIDE. REFER
SERVICING TO QUALIFIED SERVICE PERSONNEL
ONLY.

PRECAUTIONS DURING SERVICING

WARNING:

1. In a ddition to safe ty, othe r parts and assemblies are

speci fied for conformance with such regulatio ns as
those applyi ng to sp urious radiation . These must
also be replace d only with specifie d replacements.
Exampl es: RF converters, tun er units, a ntenna
selection switches, RF cables, noise-blo cking
capacitors, noise-bl ocking filters, etc.
2. Use sp ecified inte rnal Wiring . Note especially:
1) Wires covered with PVC tubing
2) Do uble insulated w ires
3) Hig h voltage leads
3. Use specified i nsulating material s for haza rdous
live pa rts. Note espe cially:
1) In sulating Tape
2) PVC tubing
3) Spa cers (insu lating barriers)
4) Insula ting sheets for transistors
5) Plastic screws for fixing micro switches
4. When replacing AC primary side compo nents
(tran sformers, power cords, n oise blo cking
capacitors, e tc.), wra p ends o f wires securely about
the te rminals be fore solde ring.

Before servicing this TV receiver, read the X-RAY

RADIATION PRECAUTION, SAFETY INSTRUCTION
and PRODUCT SAFETY NOTICE.

X-RAY RADIATION PRECAUTION

1. Excessively high can prod uce potentially hazardous
X-RAY RADIATION. To avoid such hazards, the high
volta ge must no t exceed the speci fied limit. The
normal va lue of the high voltage of this TV receiver
is 2 7 KV at zero b ean current (mi nimum b rightne ss).
The high voltage must no t exceed 30 KV u nder any
circu mstances. Each time when a re ceiver req uires
servici ng, the high voltage sho uld be checked. The
readi ng of the high voltage is re commended to be
reco rded as a part o f the service record, It is
important to u se an accurate and reliable high
voltage meter.
2. The only source of X-RAY RADIATION in this TV
receiver is the picture tube. For con tinued X-RAY
RADIATION protectio n, the repla cement tube must be
exactly the sa me type as specified in th e parts list.
3. Some parts in this TV receiver have special safety
related characteristics fo r X-RADIATION protection.
For continued safety, the parts rep lacement should
be under taken only afte r referring the PRODUCT
SAFETY NOTICE.

5. Make sure that w ires do no t contact heat generating

parts (he at sin ks, oxide me tal fi lm resistors, fusi ble
resistors, etc.)
6. Check if replace d wires do not conta ct sharply edged
or po inted pa rts.
7. Make sure that foreign objects (screws, solder
drop lets, etc.) do not remain insi de the set.

SAFETY INSTRUCTION
The se rvice shoul d not be attempted by anyone
unfamiliar with the ne cessary i nstructio ns on th is TV
receiver. The fo llowing are the necessary instru ctions
to be ob served before se rvicing.
1. An isolation transformer shoul d be con nected i n the
power li ne between the receiver and the AC line
when a service is performed o n the primary of the
conve rter tra nsformer of the set.
2. Comply wi th all caution an d safety related provided
on th e back of the cabi net, inside the cabinet, o n the
chassis or p icture tube.
3. To avo id a shock hazard, alw ays discharge the
pictu re tube's anode to the chassis g round be fore
removi ng the anod e cap.

MAKE YOUR CONTRIBUTION TO PROTECT THE

ENVIRONMENT
Used batte ries wi th the ISO symbol
for recycling a s well as small
accumu lators (re chargeable batteries), mini-batteries
(cell s) and starter b atteries should not be thrown
into the garbage can.
Please leave the m at an ap propriate depot.

-2-

PRODUCT SAFETY NOTICE

4. Completely discharge the high pote ntial voltage of the

picture tube before handli ng. The pi cture tube is a
vacuum and if bro ken, the gl ass will explode.
5. When rep lacing a MAIN PC B in the cabinet, always
be certai n that all protective are installed properly
such as co ntrol knobs, adjustment co vers o r shie lds,
barri ers, iso lation resistor networks etc.
6. When se rvicing is re quired, observe the origin al lead
dressing. Extra precau tion sho uld be gi ven to a ssure
correct lead dressing in the high voltage area.
7. Keep wires away from high voltage or high te mpera
ture compone nts.
8. Befo re returning the set to the customer, al ways
perform an AC leaka ge current check on the exposed
meta llic parts of th e cabine t, such as anten nas,
termin als, screw heads, meta l overlay, control shafts,
etc., to be sure the set i s safe to operate without
danger of electrica l shock. Plu g the AC lin e cord
directly to the AC outlet (do not use a line iso lation
transformer d uring th is check). Use an AC voltmeter
havin g 5K ohms volt sen sitivity or more i n the
following manner.
Conne ct a 1.5 K ohm 10 watt resistor pa ralleled by a
0.15F AC type capacito r, between a go od earth
ground (water pipe, conductor etc.,) and the exposed
metallic parts, one a t a ti me.
Measure the AC vol tage across the combination of
the 1 .5K ohm resistor and 0.15 uF capacitor. Re verse
the AC p lug at the AC o utlet and repea t the AC
volta ge measurements fo r each exposed metallic
part.
The me asured voltage must not exceed 0.3 V RMS.
This correspo nds to 0.5mA AC. Any val ue exceeding
this limit co nstitute s a poten tial sho ck hazard and
must be corrected immedia tely.
The resista nce me asureme nt shou ld be done
betwe en accessi ble exposed metal parts and power
cord plug prong s with th e power switch "ON". The
resi stance should be mo re tha n 6M o hms.

Many e lectrical an d mechanica l parts in this TV

receiver have special safety-related characteristics.
These characteri stics are offer passed unnoticed by
visual spection and the protecti on afforded by them
cannot necessari ly be obta ined by using replacement
compon ents rates for a hig her voltag e, wattage , etc.
The replacemen t parts w hich have these sp ecial
safety characteristics are identifie d by
marks on
the schematic diag ram and on the parts l ist.
Before replacin g any of these compo nents, rea d the
parts list in thi s manua l care fully. The use of
substitute re placemen t parts which do not have the
same safety chara cteristics as speci fied in the p arts
list may cre ate shock, fire, X-RAY RADIATION or
other h azards.

AC VOLTMETER

Goo d ea rth grou nd

su ch as th e wat er
p ip e , c o n du c t or ,
etc.

Pl ace this pro be

on eac h e x p os ed me t al li c
part

AC Leak age Curr ent Check

-3-

KAWA ELECTRONIC RESEARCH & DEVELOPMENT CENTRE

Reference No

: LCT2701TD

Product Specification
1.1 VIDEO SECTION

Display size
Display Resolution
Pixel Pitch
Peak Brightness
Contract Ratio
View Angle
Color Deeps
PC Resolution Supporting
HDTV Compatible
Progressive Scanning
Film Mode Pull Down
GAMMA Correction
Color Temperature Control
Comb Filter
Second De-interlace for Sub picture
Wide Mode
TV System
Dual Tuner System
AV Input Color System
PIP
1.2 AUDIO SECTION
Audio Output Power
Sound Effect
Tone Control
1.3 Input Terminals

1.4 Output Terminals

1.5 Others
Closed Caption / V-Chip
Teletext
No
OSD Language

CHIMEI V270B1-L01
MK8205
USA
27/16:9
1366 X 768
0.1460mm0.4365mm
550(nits)
1000:1, Typical (1/100 White Window, Dark Room)
Hor. And Vert. 170 degree
16.7M Color (R / G/ B each 256 Scales)
VGA, SVGA, XGA,WXGA
480i / 480p / 720p / 1080i
Yes
Yes
Yes
Yes
Yes
No
Normal, Full, Wide 1, Wide 2, Wide 3, 4:3, No scale and
Panoramic.
NTSC M
No
PAL /NTSC
Basic mode (video on graphic mode,resolution 1024768)
6W2 Max.(8 ohm)
Spatial Effect and Surround
Yes
D-Sub 15 Pin Type(Analog-RGB Input ) 1
D-Sub 9 Pin (RS-232)
RF (F-type Input) 1
Component Video-YPbPr 1 RCA Terminals
S-Video Input (Mini Din 4Pin) 1
Video Input RCA Terminals
Stereo Audio Input for YPbPr x 1
(3.5mm Phone Type) x 1
Audio Output (RCA ; L&R Type) 1
Yes
English, Franais, Espaol

KAWA ELECTRONIC RESEARCH & DEVELOPMENT CENTRE

Reference No

MTS with SAP

Stereo Decode
Power Rating
Power Consumption

AC 120 V, 60Hz
200W

1.6 Support the Signal Mode

This machine can support the different from VGA signal mode in 7 kinds
No
Resolution
Horizontal
Vertical
Frequency(Hz)
Frequency(KHz)
1)
2)
3)
4)
5)
6)
7)

640480
640480
800600
800600
800600
800600
1024768

: LCT2701TD

31.50
37.86
35.16
37.90
46.90
48.08
48.40

60.00
72.81
56.25
60.32
75.00
72.19
60.00

Dot Clock
Frequency(MHz)
25.18
31.50
36.00
40.00
49.50
50.00
65.00

1.7 HDTV Mode (YPbPr)

No
1)
2)
3)
4)

Resolution
480i
480p(720
720p(1280
1080i(1920

Horizontal
Frequency(KHz)

Vertical
Frequency(Hz)

15.734
31.468
45.00
33.75

59.94
59.94
60.00
60.00

Dot Clock
Frequency(MHz)
13.50
27.00
74.25
74.25

1.8 Remote Control

Power (
): Press to turn on and off.
Mute (
): Press to mute the sound. Press
again or press VOL+/- to restore the sound.
CCD: Press to select the Closed Caption mode.
V-Chip: Press to select the child protect mode.
MTS: Press repeatedly to cycle through the Multichannel TV sound (MTS) options: Mono, Stereo
and SAP (Second Audio Program).
Favorite: Press repeatedly to cycle through the
favorite channel list.
PIC.Size: Press repeatedly to cycle through the
picture size that best corresponds your viewing
requirements: Normal, Full, Wide1, Wide2,
Wide3, 4:3, No scale, Panoramic and Normal.
Freeze: Press to freeze the picture, press again
to restore the picture. (This button is not available
for
. VGA mode.)
P.Mode: Press repeatedly to cycle through the
picture mode: Hi-Bright, User, Dark, Normal
and Vivid.
Display: Press to display the channel information
and it disappear after 3 seconds.
Sleep: Press repeatedly until it displays the time
in minutes (5 Min, 10 Min, 15 Min, 30 Min, 60
Min, 90 Min, 120 Min and, OFF) that you want
the TV to remain on before shutting off. To
cancel sleep time, press Sleep button repeatedly
until sleep OFF appears.
Zoom: Press to zoom the image. (This button is not
avialable for VGA mode.)
S.Mode: Press repeatedly to cycle through the
sound mode: Normal, News, Cinema, Flat and
User.
System: Press repeatedly to cycle through the
system options: AUTO and NTSC3.58.
(This button is activate for AV, S-Video input
source.)
Add/Erase: Press to add or delete favorite channel.
Color TMP: Press to select the color temperature.
0~9 Number Buttons: In TV mode, press 0~9 to select a channel; the channel changes after 2
seconds. In DVD mode, press 0~9 to input the items.
CH Edit: Press to edit channel name.
VGA ADJ: Press to auto adjust VGA position.
Source: Press to select the signal source, such as TV, AV, S-Video, Component, DVD, or VGA.
Recall: Press to return previous channel.
Enter: To select an item, press Enter to confirm.
VOL + / : Press to adjust the volume.
CH + / : Press to scan through channels. To scan quickly through channels, press and hold
down either channels.
, , , : Press , , , to move the on-screen cursor.

Menu: Press to enter on-screen setup menu,

press again to exit.
,
: Press to search the backward
forward.
: Press to play or pause the DVD disc.
: Press to stop playing the disc.
,
: Press to skip the backward or
forward.
: Press to open or close the disc tray.
DVD Menu: Press to return DVD disc menu.
Prog: Press to display the program menu. Press
it again to exit.
Repeat: Press repeatedly to cycle through the
options: CHAPTER, TITLE, ALL and nothing.
Subtitle: Press to select desired DVD subtitle.
Audio: Press to select desired audio track.
Setup: Press to display a menu. Press it again
to exit menu.
Angle: Press to select desired viewing angle of
the Video (disc feature).
Title: Press to display to DVD disc title.
DVD Info: Press to display DVD information.
Note: Press CH +/- on the remote control can turn on
TV set from last preview mode.

KAWA ELECTRONIC RESEARCH & DEVELOPMENT CENTRE

Reference No

: LCT2701TD

Technical Data
1. Power supply

TV
Remote control
2. TV system
RF input
Video input
3. Receiving channels TV

4. Intermediate
frequencies
5 . Scanning
6 . AC plug

7. Panel
8. Speaker

9. Operating
temperature
Accept

CATV

1~125CH

Picture

45.75MHz

Horizontal (Hz)
Vertical (Hz)

15625/15750
50/60
UL Plug
V270B1-L01
8 ohm 6W (max) 2

Internal
Fulfill all specifications

picture/sound
reproduction
10. Operating relative Fulfill all specifications
humidity
Accept
picture/sound
reproduction
11. Electrical &
optical
specification
12. Circuit diagram
drawing No.
13. Cabinet
14. Cabinet color
15. Packing
16. Container stuffing
method
17. Dimension (mm)
(No packing)
18. Net weight
19. Cell Defect

AC 120V , 60Hz
Battery 3V (UM-3/R6P/AA2)
NTSC M
PAL/NTSC 3.58/NTSC 4.43
VHF-L : 2~6CH
VHF-H : 7~13CH
UHF
: 14~69CH

15 C ~ 30 C
5 C ~ 33 C
45% ~ 75%
20% ~ 80%
See the attachment 1.

LCT2701TD

1 set per
RD/05/P/LC26HAB/CSI/02 REV: 01

LCD-TV
Remote control unit
LCD-TV
Remote control

698(W) x 513(H) x 99(D)mm (w/o Stand)

698(W) x 554(H) x 250(D)mm (with Stand)
183(L) x 53(W) x 28(T)mm
13.9Kg (with Stand) approx
70g (approx)
Subject to Panel supplier specification

KAWA ELECTRONIC RESEARCH & DEVELOPMENT CENTRE

Reference No

: LCT3201TD

Attachment 1Electrical & Optical Specification

No.

Items

Instruction

Typical

Limit

Unit

Video sensitivity

For 30dB S/N

44

51

dBuV

FM sound sensitivity

For 30dB S/N

21

35

dBuV

Color sensitivity

For RF transmission

37

40

dBuV

CCD sensitivity

TV screen refreshes 40 times

number of mistakes8

43

50

dBuV

Minimum NICAM threshold

Without crackline noise

N/A

N/A

dBuV

Stereo Channel Separation

BTSC.

18

15

dB

AGC static characteristic

Accept. Picture/Sound repr.

90

90

dBuV

Selectivity

Adjacent sound carrier

30

28

Below adjacent sound carrier

30

30

Adjacent picture carrier

45

40

Up adjacent picture carrier

40

30

55

45

dB

VHF

57

45

dB

UHF

55

40

IF rejection

10

Image rejection

dB

11

AFT pull-in range

1.0

1.0

MHz

12

Chroma sync pull-in range

500

200

Hz

13

Color killer function

-11

-10

dB

14

Resolution

PAL

300

300

Lines

NTSC

260

240

Lines

PAL

410

400

Lines

NTSC

320

300

Lines

Horizontal

450

450

Lines

Vertical

400

400

Lines

RF

Horizontal
Vertical

Video

15
16

Color
Coordination
View
Angle(Lo/3)

White

XW

Full Pattern

YW
Horizontal

0.295

0.2950.02

0.300
170

0.3000.02
170

Degree

Vertical

17

Overscan

Cross hatch signal

96

94~98

18

Picture position

In all direction

mm

19

H sync pull-in range

400

200

Hz

20

V sync pull-in range

Hz

21

Audio frequency response

0.15~12

0.2~12

KHz

3dB ref. to 1KHz

KAWA ELECTRONIC RESEARCH & DEVELOPMENT CENTRE

Reference No

: LCT3201TD

72

5.02

1KHz 10% THD

62

4.02

THD

Po=0.5W

0.5

25

Signal to buzz ratio

coeighting

50

30

dB

26

Minimum volume hum

coeighting

10

mVrms

27

Maximum woofer output power

N/A

N/A

28

Woofer audio frequency

response

3dB ref. to 15Hz AV

mode

N/A

N/A

Hz

29

Tone low frequency

100Hz ref. to 1KHz

AV mode

dB

30

Tone high frequency

10KHz ref. to 1KHz

AV mode

dB

31

Balance

Center

Max.

>2

Min.

-35

-30

22

Max Audio Output Power

23

Audio output power

10% THD

24

dB

32

Video input level

1.0

10.3

Vpp

33

Audio input level*1

1.0 *

0.50.3

Vrms

34

Video output level

N/A

N/A

Vrms

35

Audio output level*2

0.3 *

0.50.3

Vrms

36

AV Audio input max. level

Vrms

37

AV Audio output L/R

Separation

35

30

dB

38

Power consumpution

Operating

200

200

Stand by

0 Degree
5m

60

45

Degree

20

15

Degree

10

mArms

39

IR receiving distance

40

IR receiving
angle

left/right
Up/down

41

Dielectric strength

DC 3KV

1min.

42

The vibration noise from

The distance between
electromagnetic devices in LCD- the tester and the
TV set
LCD-TV set is four
times as many as the
screen height

No obvious vibration noise can be

heard

KAWA ELECTRONIC RESEARCH & DEVELOPMENT CENTRE

Reference No

: LCT3201TD

Test Condition
All tests shall be performed under the following conditions unless otherwise specified
1

Picture Modulation

87.5%

Sound Modulation

27KHz Dev. For DK/I/BG

15KHz Dev. For M/N

Picture to Sound Ratio

10dB

8 ohm

Sound Artificial Load

Resistor
Video signal

Audio signal

1KHz sine wave 0.5Vrms

Other conditions:
A. Switch LCD-TV on and let it warm up for more than 30 minutes.
Viewing distance: 3H (H: Panel High) in front of LCD, about 2M.
Ambient light: 0.1 cd/ m2
B. Brightness, Contrast, Saturation, Tint, sharpness set at normal.
C. Connect RMS volt meter to speaker terminals and adjust the LCD volume to get 500mW RMS
power at each terminals.
D. With image sticking protection of LCD module. The luminance will descend by time on a same
still screen and rapidly go down in 5 minutes, when measuring the color tracking and luminance
of a same still screen, be sure to accomplish the measurement in one minute to ensure its
accuracy.
E. Due to the structure of LCD module. The extra-high-bright same screen should not hold over 5
minutes for fear of branding on the panel.
F. RF test point: Video output.

Note:
*(1) Now this project cannot fit the limited spec. the typical audio input level is 1.0 Vrms,
*(2) The audio out level is controlled by the volume level, the range is from 0 to 0.5Vrms.

Stair and Special

DVD player's spec. For LCD-TV Combo

Division

Section
name
Marketing Area( setup default language)
General
Power supply
Power Consumption
Manufactruer of Loader mechanism
Opitical Pick UP
DVD Module
Chipset used
Playback
Playable Media Type
Disc Type
Playable Disc Type
Disc Size
Regional code
NTSC/ PAL Disc playback
Video
Video output signal
Video DAC
Audio
Audio DAC
Dynamic range
Dolby digital decoder
DTS decoder
SRS + TruSurround for 2 channel
3D Virtual surround for 2 channel
Playback
Fast forward/backward
Features
Slow motion forward
Slow motion backward
Still picture
Frame by frame forward/reverse
Skip forward/reverse
Repeat function
DVD closed caption
Transition Effect for picture CD
Rotation of picture for picture CDs
Last Memory
Display
Graphical user interface
user
OSD Language
operation
Subtitle
Screen saver
Resume play
Program function
PBC ON/OFF
Parental lock
Picture mode selector
Intro scan
Digest in VCD
Time search
Multi angle
Selectable audio language streams
kalaoke function
Front Panel
VFD/ LED
No. of keys
Rear Panel
Composite Video output
Component Video output
Progressive scan output (480P)
2 channel audio output
Coaxial audio output

Remarks
AKAI
USA
+5v,+3.3v
15W
Foryou DL06-LS
Sanyo HD-62/65
MTK 1389FE
Playable Disc Type: DVD, CD,
DVD(Single/ Dual layer, Double sided), CD
8cm/12cm
Regional 1
O/O
NTSC
27MHz/ 10bit
48Khz/ 96KHz/24-bit:selectable
Present
Present
optional
Not present
Not present
x2,x4,x8,x16,x32
x1/2,x1/4,x1/8,x1/16
optional
Present
Forward only (Step function)
Present
Present
Present
Not present
Present
Present
Not present
3 (ENG is base ,SPA and French)
Present
Present
Present
Present
Default on PCB
Passward : 0000
16:9, 4:3 LB, 4:3 PS(4:3 PS as default)
Not present
Present, only for PIC CD
Present
Present
Present
x
x
3(Open/Close, Play, Stop)
x
x
Present
Present
Present

LCD COMBO Connection

L

Key Board

R
PWM
On/Off

Turner+Amp

LVDS1

Main board

Panel

PWM

Backlight
+24V

+24V

IR1
+5V
+5V IR2
Key Board

DVD

+5V STB

+12V

Power board
Y/Pb/Pr (480p)
L/R

Dimming
BL_ON/OFF

Dimming
BL_ON/OFF

PANEL INVERTER POWER

Inverter_PWR

HOLE/GND

H1
9
8
7
6

2
3
4
5

CE1
470uF/50v

CE2
470uF/50v

C1
0.1uF

Inverter_PWR

C2
0.1uF

2
3
4
5

PWR_GND

9
8
7
6

2
3
4
5

2
3
4
5

Dimming
BL_ON/OFF

1
9
8
7
6

2
3
4
5

1
2
3
4
5
6
7
8
9
10

C3
0.1uF

2
3
4
5

2
3
4
5

8x1 W/HOUSING
SIP6\2.54

HOLE/GND

H5
9
8
7
6

10x1 W/HOUSING R.A.

SIP10\2

2
3
4
5

2
3
4
5

FB2
120R

9
8
7
6

1206

FB9
120R

2
3
4
5

9
8
7
6
1

FB1
120R
1206

HOLE/GND

H4
9
8
7
6

PWR_GND

PWR_GND

FB7
120R

INVERTER_PWR

1
2
3
4
5
6

12x1 W/HOUSING R.A

SIP12\2
J3

9
8
7
6

J2

FB6
120R

HOLE/GND

H3
B

1
2
3
4
5
6
7
8
9
10
11
12

R. ANGLE

9
8
7
6
1

9
8
7
6

Inverter_PWR

HOLE/GND

H2
C

J1

R. ANGLE

FB5
120R

FB8
120R

Title
Size
A

Date:

<Title>
Document Number
<Doc>
Wednesday, August 24, 2005
2

Rev
<RevCode>
Sheet

of

J5

J4
VGA AUDIO
PHONEJACK/DIP

VGA_R

Dimming

VGA_L

RSTXD
VGA_R

K1
K2
K3
K4
K5

1
2
3
4
G

11

VGA_SDA

12

HS YNC#

13

VSYNC#

14

VGA_SCL

15

DSUB15/DIP/F
DB15
1
6
2
7
3
8
4
9
5
10

BL_ON/OFF

1
3
5
7
9
11
13
15
17
19
21
23
25
27

VGA_L

SC_IN
2
SC_GND1 1

3
4

GREEN
GRN_GND
VGA_PWR

AV1_IN
SC_IN
SC_GND1
SY _IN

2
4
6
8
10
12
14
16
18
20

1
3
5
7
9
11
13
15
17
19

J8

CB1_INB
CB1_GNDB

AUIO IN/OUT GND

Y1_INB
Y1_GNDB

3
4

CB1_INB
CB1_GNDB

5
6

CR1_INB
CR1_GNDB

J10

AV_L
AV_R
SY_GND1

1
2

YPBPR1/L

3
4

YPBPR1/R

RCA1X2
RCA2/4P/DIP
J11

FB4
120R

ANALOG INPUT GND

1
2

RCA1X3
RCA3/6P/DIP

YPBPR1/L
YPBPR1/R

VIDEO CONNECTOR
DIP10X2/P2.54/R2

FB3
120R

SY _IN
SY_GND1

HS YNC#
VGA_SCL

J9
Y1_INB
Y1_GNDB
CR1_INB
CR1_GNDB

J6
CON\SVHS

RSRXD

PC CONNECTOR
DIP14X2/P2.54/R2

RED
RED_GND
GREEN
GRN_GND
BLUE
BLU_GND
RSTXD
VGA_PWR

17

RSRXD

VGA_SDA
VSYNC#

16

J7

RED
RED_GND
BLUE
BLU_GND

2
4
6
8
10
12
14
16
18
20
22
24
26
28

Dimming
BL_ON/OFF

Dimming
BL_ON/OFF

1
2

AV1_IN

3
4

AV_L

5
6

AV_R

RCA1X3
RCA3/6P/DIP

DIGITAL GND

Title
Size
A
5

Date:

<Title>
Document Number
<Doc>
Wednesday, August 24, 2005
2

Rev
<RevCode>
Sheet

of

J1

VSYNC
HSYNC
R
G
B
CLK1+
CLK1CLK2+
CLK2ORO1

VSYNC
HSYNC
R
G
B

3
3
3
3
3

CLK1+
CLK1CLK2+
CLK2-

3
3
3
3

ORO1

AN0
AP0
AN1
AP1
AN2
AP2

+12V

AP[0..7]
AN[0..7]

+12V

+12V

VCC

AN5
AP5

Optinal for 12V pannel.Added by bin_wang 16/7/05

FB1
75R

0805
AP[0..7]
AN[0..7]

CLK1CLK1+
AN3
AP3
AN4
AP4

AN6
AP6
CLK2CLK2+
AN7
AP7

FB2
75R/NC
0805

3
3

Add LVDS VCC control by Zheng_guo 15/9/05.

Q9

F1

4A/32v
1206

CE1
330uF/25v

C330UF25V/D8H14

1
2
3
4

S1
G1
S2
G2

LVDSVDD

8
7
6
5

D1
D1
D2
D2

IR7314
SOP8

+12V

CE2
220uF/16v

+ CE3
220uF/16v

C1
0.1uF

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

C2
0.1uF

CRT OUT
R
R1
75 1%

75 1%

HSYNC

FI-SE30P-HF
LVDS/30P/P1.25/S

VSYNC

GND

VS

R3

HS

GND

RGB OUTPUT FOR DEBUGGING

R211

R2

R209 R210
22k
22k

ORO1 High :LVDSVDD POWER OFF

ORO1 LOW :LVDSVDD POWER ON

GND

75 1%

ORO1

Q10
2N3904

1
2

2k

ORO3
PWM0
Dimming
BL_ON/OFF

ORO3
PWM0
Dimming
BL_ON/OFF

3
3
6
6

ORO3 High :PANEL BACKLIGHT POWER OFF

ORO3 LOW :PANEL BACKLIGHT POWER ON

FOR CHI-MEI INVERTER

CONNECTOR

VCC

R4

0
R5
10k

PWM0

R6
R7

Q1
2N3904
SOT23

C3
0.1uF

VCC

4.7k

Dimming

100k

R8
10k

Back Light circuit

ORO3

BL_ON/OFF
R9

Q2
2N3904
SOT23

1
2

4.7k
1

MiCO Confidential
Title
Size
C
Date:
A

MiCO LCD TV - MediaTek MT8203 Solution

Doc Number

LVDS/CRT/BACKLIGHT CONTROL

Wednesday, September 28, 2005

E

Sheet

of

Rev
V0.1
10

VGASOG
RED+
REDGREEN+
GREENBLUE+
4

VGASOG

RED+

RED-

GREEN+

GREEN-

3
3

BLUE-

CB+
CBCR+
CRY+
Y-

R13
R12

CVBS0

C5

18
22

BLUE+

BLUE-

CB+

CB-

CR+

CR-

Y+

Y-

SY+

SY-

R11

CVBS0+

C9

C4

100

R16

Y_GND

CVBS0-

C8

100

R21

22

R19

CB

C11

CVBS1+

R24

CB_GND

C15

CVBS1_GND

C14

100

CVBS1-

CB+

47nF

C12
15pF

47nF

C10

100

C13
330pF

Y-

47nF

47nF

CVBS1

Y+

47nF

C6
15pF

C7
330pF

R17

CVBS0_GND

47nF

R15
56

CB-

47nF

Change.
SY+
SY-

47nF

R27

CR

C16

100

SC+
SCCVBS0+
CVBS0CVBS1+
CVBS1-

SC+

SC-

CVBS0+

CVBS0-

CVBS1+

CVBS1-

C17
15pF
R29

CR_GND

C18

100

Change.

R31

C19

SY

MPX1
MPX2

MPX1

MPX2

+
C23
15pF/NC

OUTPUT

C22

8.2K

C24
15pF/NC

C21

SY_GND

R37

47nF

C25

SC
22

CB
CB_GND
CR
CR_GND
SOY
SY
SY_GND
2

SC
SC_GND

Y_GND

CB

CB_GND

CR

CR_GND

SOY

3,7

SY

SY_GND

SC

SC_GND

AF Path
AF1_OUT

SC+

47nF
C27
330pF
C28

SC_GND

47nF/NC

SC-

CE5
R40

39k

R41

C29
15pF

39k

Y_GND

SY-

47nF

MPX1

C26
Y

C20
330pF

47uF/16v /NC

R35

SIF1_OUT

SY+

47nF

CE4

FROM Tuner

CR-

47nF

22
3

CR+

47nF

C30
15pF

47nF

MPX2

47uF/16v

ATTENTION:WHEN PCB LAYOUT,MUST NEAR VGA INPUT PORT! BIN_WANG. 16/7/05

RED

R42

C31

68

RED+

47nF
C32
5pF
R44

RED_GND

C33

100

RED-

47nF

FB4
70R

C34

VGASOG

4.7nF

CVBS0
CVBS0_GND
CVBS1
CVBS1_GND
SIF1_OUT
AF1_OUT
RED
GREEN
BLUE
RED_GND
GRN_GND
BLU_GND

CVBS0

CVBS0_GND

CVBS1

CVBS1_GND

SIF1_OUT

AF1_OUT

RED

GREEN

BLUE

RED_GND

GRN_GND

BLU_GND

GREEN

R46

C35

68

GREEN+

47nF
C36
5pF
R48

GRN_GND

100

C37

FB6

GREEN-

47nF

70R

R49

BLUE

68

C38

BLUE+

47nF
C39
5pF
BLU_GND

R51

100

C40

BLUE-

47nF

FB8
70R

INPUT
MODIFIED BY BIN_WANG 16/7/05.

MiCO Confidential
Title
Size
C
Date:
A

MiCO LCD TV - MediaTek MT8203 Solution

Doc Number

Rev
V0.1

AV IN

Thursday, September 15, 2005

E

Sheet

of

10

TXD
RXD
Dimming
BL_ON/OFF

TXD
RXD

3
3

Dimming
BL_ON/OFF

9
9

VGA_IN_L
VGA_IN_R
VGASDA
VGASCL
HSYNC_VGA

VGA_PLUGPWR

RSRXD
RSTXD

C41 0.1uF

+5V

C42

0.1uF

C44

0.1uF

C46

0.1uF

U1
13
8
11
10

R1IN
R2IN
T1IN
T2IN

1
3
4
5
2
6

C+
C1C2+
C2V+
V-

R1OUT
R2OUT
T1OUT
T2OUT

VCC
GND

VGAVSYNC#
RED_GND

VGA_PLUGPWR

12
9
14
7

RED

TXD
C43

RXD

16
C45
0.1uF

0.1uF

MAX232A

R52
4.7k

U2
1
2
3
4

NC
NC
NC
GND

VCC
WP
SCL
SDA

8
7
6
5

Modified by MICO.
Dimming
RSTXD
VGA_R
RED
RED_GND
BLUE
BLU_GND
VGA_SDA
VSYNC#

28
26
24
22
20
18
16
14
12
10
8
6
4
2J2

27
25
23
21
19
17
15
13
11
9
7
5
3
1

VGA_R

BL_ON/OFF
RSRXD

VGA_L

R53
4.7k

GREEN
BLUE

10
10
3
3
3

VGAVSYNC#

RED_GND

GRN_GND

BLU_GND

RED

GREEN

BLUE

VGASCL
VGASDA

EEPROM 24C02

GRN_GND
BLU_GND

+5V

15

VGA_PLUGPWR

VGA_IN_L
VGA_IN_R
VGASDA
VGASCL
HSYNC_VGA

GND

R54

15K

R55

15K

VGA_L

VGA_IN_L
R56
75K

GREEN
GRN_GND

VGA_IN_R

R57
75K

VGA_PWR
HSYNC#
VGA_SCL

PC CONNECTOR
DIP14X2/P2.54/R1

VCC
FB9

VSYNC#
70R
0603

VGASDA

R59

33

VGAVSYNC#

R58
2.2k

D1

VGA_PWR

R60

33

VGA_SCL

VGA_PLUGPWR
DIODE SMD
1N4148/SMD

VGA_SDA
FB10

VGASCL

DIODE SMD
1N4148/SMD

D2
C47
100pF

HSYNC#

HSYNC_VGA
70R
0603

R61
2.2k

C48
5pF

MiCO Confidential
Title
Size
B
Date:
A

MiCO LCD TV - MediaTek MT8203 Solution

Doc Number

Rev
V0.1

VGA IN & PC AUDIO IN

Thursday, September 15, 2005

Sheet
E

of

10

F_D[0..7]
F_A[0..21]

F_D[0..7]
F_A[0..21]

3
3

A_DQS[0..3]
A_RA[0..11]
A_BA[0..1]
A_DQM[0..1]
A_DQ[0..31]

A_DQS[0..3]
A_RA[0..11]
A_BA[0..1]
A_DQM[0..1]
A_DQ[0..31]

3
3
3
3
3

A_CLK
A_CLK#
A_CKE
A_CS#
A_RAS#
A_CAS#
A_WE#

A_CLK
A_CLK#
A_CKE
A_CS#
A_RAS#
A_CAS#
A_WE#

3
3
3
3
3
3
3

SDV25
VREF
IOWR#
IOCE#
F_OE#

SDV25
VREF
IOWR#
IOCE#
F_OE#

3
3
3
3
3

F_D[0..7]

F_D[0..7]

F_OE#

F_OE#

F_A[0..21]

F_A[0..21]

RN4
7
5
3
1

A_RA4
A_RA5
A_RA6
A_RA7

RN5
7
5
3
1

22x4

A_RA8
A_RA9
A_RA11
A_RA10

RN7
7
5
3
1

22x4

8
6
4
2

D_RA3
D_RA2
D_RA1
D_RA0

8
6
4
2

D_RA4
D_RA5
D_RA6
D_RA7

8
6
4
2

D_RA8
D_RA9
D_RA11
D_RA10

SDV25

SDV25
U4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33

D_DQ0
D_DQ1
D_DQ2
D_DQ3
D_DQ4
D_DQ5
D_DQ6
D_DQ7

22x4

D_DQS0

RN9
7
5
3
1

8
6
4
2

D_DQ0
D_DQ1
D_DQ2
D_DQ3

A_DQ4
A_DQ5
A_DQ6
A_DQ7

RN11 47x4
7
5
3
1

8
6
4
2

D_DQ4
D_DQ5
D_DQ6
D_DQ7

A_DQ8
A_DQ9
A_DQ10
A_DQ11

RN13 47x4
7
5
3
1

8
6
4
2

D_DQ8
D_DQ9
D_DQ10
D_DQ11

A_DQ12
A_DQ13
A_DQ14
A_DQ15

RN14 47x4
7
5
3
1

A_DQ16
A_DQ17
A_DQ18
A_DQ19

RN24
7
5
3
1

A_DQ20
A_DQ21
A_DQ22
A_DQ23

RN26
7
5
3
1

A_DQ24
A_DQ25
A_DQ26
A_DQ27
A_DQ28
A_DQ29
A_DQ30
A_DQ31

D_DQM0
D_WE#
D_CAS#
D_RAS#
D_CS#
D_BA0
D_BA1
D_RA10
D_RA0
D_RA1
D_RA2
D_RA3

VSS
VDD
DQ15
DQ0
VSSQ
VDDQ
DQ14
DQ1
DQ13
DQ2
VDDQ
VSSQ
DQ12
DQ3
DQ11
DQ4
VSSQ
VDDQ
DQ10
DQ5
DQ9
DQ6
VDDQ
VSSQ
DQ8
DQ7
NC
NC
VSSQ
VDDQ
UDQS
LDQS
NC
NC
VREF
VDD
VSS
DNU
UDM
LDM
CK
WE
CAS
CK
CKE
RAS
NC
CS
A12
NC
A11
BA0
A9
BA1
A8
A10/AP
A7
A0
A6
A1
A5
A2 8M x 16
DDR
A4
A3
VSS
VDD

66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34

D_DQ15
D_DQ14
D_DQ13
D_DQ12
D_DQ11
D_DQ10
D_DQ9
D_DQ8
D_DQS1

0.1uF

D_RA11
D_RA9
D_RA8
D_RA7
D_RA6
D_RA5
D_RA4

D_DQ17
D_DQ18

47x4

RN27 47x4
7
5
3
1

8
6
4
2

D_DQ24
D_DQ25
D_DQ26
D_DQ27

RN29 47x4
7
5
3
1

8
6
4
2

D_DQ28
D_DQ29
D_DQ30
D_DQ31

A_DQS0

R65

47

D_DQS0

A_DQS1

R66

47

D_DQS1

A_DQS2

R201

47

D_DQS2

A_DQS3

R202

47

D_DQS3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33

D_DQ16

D_DQ19
D_DQ20
D_DQ21
D_DQ22
D_DQ23
D_DQS2

D_DQM1
D_WE#
D_CAS#
D_RAS#
D_CS#
D_BA0
D_BA1
D_RA10
D_RA0
D_RA1
D_RA2
D_RA3

VSS
VDD
DQ15
DQ0
VSSQ
VDDQ
DQ14
DQ1
DQ13
DQ2
VDDQ
VSSQ
DQ12
DQ3
DQ11
DQ4
VSSQ
VDDQ
DQ10
DQ5
DQ9
DQ6
VDDQ
VSSQ
DQ8
DQ7
NC
NC
VSSQ
VDDQ
UDQS
LDQS
NC
NC
VREF
VDD
VSS
DNU
UDM
LDM
CK
WE
CAS
CK
CKE
RAS
NC
CS
A12
NC
A11
BA0
A9
BA1
A8
A10/AP
A7
A0
A6
A1
A5
A2 8M x 16
DDR
A4
A3
VSS
VDD

66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34

D_DQ30
D_DQ29

7
5
3
1

A_BA1

R67

A_BA0

R68

8
6
4
2
22x4

D_DQ26
D_DQ25
D_DQ24

RN28
D_DQ20 2
D_DQ21 4
D_DQ22 6
D_DQ23 8

D_DQS3
VREF
D_DQM1
D_CLK#
D_CLK
D_CKE

RN30
D_DQ27 1
D_DQ26 3
D_DQ25 5
D_DQ24 7

C208
0.1uF

D_RA11
D_RA9
D_RA8
D_RA7
D_RA6
D_RA5
D_RA4

RN31
D_DQ31 1
D_DQ30 3
D_DQ29 5
D_DQ28 7

D_BA1

22

D_BA0

A_DQM0

R71

22

D_DQM0

A_DQM1

R206

22

D_DQM1

A_CKE

R73

22

D_CKE

A_CLK

R75

22

D_CLK

A_CLK#

R77

22

7
5
3
1
75x4

DV33A
1
3
5

75x4

R63

75

10k

D_RAS#
D_CS#
D_BA0
D_BA1

1
2
3
4

D1V25
VREF

VREF

4.7k
U5

D1V25

SDV25

GND
VTT
SD
PVIN
VSENSE AVIN
VREF
VDDQ

8
7
6
5

IC LP2996 DDR Termination SOP8

D_CLK#

C83

C84

0.1uF

0.1uF

IOWR#

DV33A

8
6
4
2

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
RY/BY
A19
A20
CE
OE
WE

12

RESET

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A18
NC
WP/ACC
BYTE

29
31
33
35
38
40
42
44
30
32
34
36
39
41
43
45
16
13
14
47

VCC

37

GND1
GND2

27
46

F_D0
F_D1
F_D2
F_D3
F_D4
F_D5
F_D6
F_D7
DV33A
4

R62

F_A0
F_A19

10k

DV33A

FLASHVCC
C49
0.1uF

MX29LV800BT

TSOP 48 pin
D1V25

75x4

D1V25

8
6
4
2

C50
0.1uF

C51
0.1uF

C52
0.1uF

C53
0.1uF

C54
0.1uF

C55
0.1uF

C56
0.1uF

C57
0.1uF

C192
0.1uF

C193
0.1uF

C194
0.1uF

C195
0.1uF

C196
0.1uF

C197
0.1uF

C198
0.1uF

C199
0.1uF

C58
3300pF

C59
3300pF

C60
3300pF

C61
3300pF

C62
3300pF

C63
3300pF

C64
3300pF

C65
3300pF

C200
3300pF

C201
3300pF

C202
3300pF

C203
3300pF

C204
3300pF

C205
3300pF

C206
3300pF

C207
3300pF

75x4
8
6
4
2
75x4
8
6
4
2

75x4
1
3
5
7
75x4
1
3
5
7

D1V25

75x4
2
4
6
8

CE7

+ CE6
220uF/16v

C270UF16V/D10H12

75x4
2
4
6
8

RN15
7
5
3
1

8
6
4
2

SDV25

75x4

R69

F_A20
F_A21
IOCE#
F_OE#

25
24
23
22
21
20
19
18
8
7
6
5
4
3
2
1
48
17
15
9
10
26
28
11

75x4

M13S128168 8Mx16-6

D_CS#
D_RAS#
D_CAS#
D_WE#

22

D_DQ4
D_DQ5
D_DQ6
D_DQ7

RN8
7
5
3
1

RN25
D_DQ16 2
D_DQ17 4
D_DQ18 6
D_DQ19 8

D_DQ28
D_DQ27

RN16
A_CS#
A_RAS#
A_CAS#
A_WE#

D_DQ0
D_DQ1
D_DQ2
D_DQ3

RN6
7
5
3
1

RN12
D_DQ12 7
D_DQ13 5
D_DQ14 3
D_DQ15 1

D_DQ31

U3
F_A1
F_A2
F_A3
F_A4
F_A5
F_A6
F_A7
F_A8
F_A9
F_A10
F_A11
F_A12
F_A13
F_A14
F_A15
F_A16
F_A17
F_A18

75x4

D_RA10 R64

C66

D_DQM0
D_CLK#
D_CLK
D_CKE

SDV25

47x4

8
6
4
2

RN10
D_DQ8
7
D_DQ9
5
D_DQ10 3
D_DQ11 1

D_DQ16
D_DQ17
D_DQ18
D_DQ19

D_DQ20
D_DQ21
D_DQ22
D_DQ23

RN2
8
6
4
2

U16

8
6
4
2

D_RA4
D_RA5
D_RA6
D_RA7

VREF

SDV25
8
6
4
2

RN1
7
5
3
1

RN3
2
D_RA11
4
D_RA9
6
D_RA8

D_DQ12
D_DQ13
D_DQ14
D_DQ15

8
6
4
2

D_RA0
D_RA1
D_RA2
D_RA3

M13S128168 8Mx16-6

47x4

D1V25

A_RA3
A_RA2
A_RA1
A_RA0

A_DQ0
A_DQ1
A_DQ2
A_DQ3

CE8
47uF/16v

CE9
220uF/16v

D_DQS2

R203

75

D_DQS3

R204

75

D_CAS#

R70

75

D_WE#

R72

75

D_DQM1

R205

75

D_DQS1

R74

75

D_DQS0

R76

75

D_DQM0

R78

75

SDV25

SDV25

C67
0.1uF

C68
0.1uF

C75
0.1uF

C69
0.1uF

C76
0.1uF

C70
0.1uF

C77
0.1uF

C71
0.1uF

C78
0.1uF

C72
0.1uF

C79
0.1uF

C74
0.1uF

C73
0.1uF

C80
0.1uF

C81
0.1uF

C82
0.1uF

SDV25

C85
3300pF

C86
3300pF

C87
3300pF

C88
3300pF

C89
3300pF

C90
3300pF

C91
3300pF

C92
3300pF

SDV25
SDV25

Modified by BIN_WANG.

VREF

C93

C94

C95

C96

C97

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

VCC

C209
0.1uF

VREF

U6
3

VREF DECOUPLING

IN

VREF

ADJ/GND

VREF

C100

C217

C218

0.1uF

3300pF

3300pF

0.1uF

0.1uF

SOT223

+ CE12

C212
0.1uF

C213
0.1uF

220uF/16v

C216
0.1uF

+ CE10
220uF/16v

220uF/16v

MiCO Confidential

Size
C
Date:
B

C215
0.1uF

Title

C214
0.1uF

SDV25

2
4

1
C99

C211
0.1uF

SDV25
OUT
OUT

+ CE11
C98

C210
0.1uF

CM1117-2.5V

MiCO LCD TV - MediaTek MT8203 Solution

Doc Number

Rev
V0.1

DDR MEMORY & FLASH

Thursday, September 15, 2005

E

Sheet

of

10

MT8203 ANALOG&DIGITAL DECOUPLING

DACVREF
DACFS
ADCPLLVDD1
ADCPLLVDD
APLLVDD
ANALOGVDD
VPLLVDD
LVDDA

ADCVDD
DACVDD
AVCM
VOCM
VICM
VREFP4
VREFN4
ADCVDD0
PWM2VREF
AUXTOP
AUXBOTTOM
REXTA
APLL_CAP
XTALI
XTALO
ADCVDD4

ADDED

DACVREF

DACFS
ADCPLLVDD1
ADCPLLVDD
APLLVDD

3
3
3
3

ANALOGVDD
VPLLVDD

3
3

LVDDA

ADCVDD
DACVDD
AVCM
VOCM
VICM
VREFP4
VREFN4
ADCVDD0
PWM2VREF
AUXTOP
AUXBOTTOM
REXTA
APLL_CAP

3
3
3
3
3
3
3
3
3
3
3
3
3

XTALI
XTALO

3
3

ADCVDD4

DACVREF

R79

DV18A

100k
DACFS

FB11
DV18A

Y1

C103
0.1uF/NC
C0603

R80
560

XTALI

70R

C101
4.7uF
C0603

27MHz
GND

GND

ADCPLLVDD1
0603

XTALO

C104
33pF

C102
0.1uF
C0603

GND

C105
33pF

AV33
FB12

CE13

0603

C109

70R

0.1uF

C107
0.1uF
C0603
GND

10uF/50v

ANALOGVDD
0603
C110
0.1uF

AVCM

BASE ON P1V5 COMMON BOARD BY BIN_WANG 16/7/05.

C111
4.7uF
C0603

C112
0.1uF
C0603
GND

C116
4.7uF
C0603

C117
0.1uF
C0603
GND

CE19
100uF/16v

C126
0.1uF

ADJ/GND

OUT
OUT

2
4

CE18
+
10uF/25v

0805

75R

Vout
+

CE20
220uF/16v

SOT223

CE21
10uF/50v

C125

GND

VOCM

GND

R82

VICM

C124
0.1uF
C0603

0.1uF
AV33

Adj regulator

Rup

1.25x(1+Rdown/Rup)

180 1%

110 1%

1.25x(1+180/110)=3.3V

C130
0.1uF
C0603

CE22
47uF/16v

C132
0.1uF
C0603

C136
0.1uF
C0603
DV33A

0805

C139
0.1uF
C0603
GND

GND

C145
0.1uF
C0603
GND

FB16
VPLLVDD

AV33
0603
C135
0.1uF

70R

C133
4.7uF
C0603

C134
0.1uF
C0603

CE23
47uF/16v

C137
4.7uF
C0603

GND

C149
0.01uF
C0603

C146
4.7uF
C0603

C138
0.1uF
C0603

70R

C156
4.7uF
C0603

GND

GND

3.3k

ADCVDD

ADCVDD0

C152
0.1uF
C0603
GND

70R
C153
0.1uF

ADCVDD4
0603

C143
0.1uF
C0603

FB18

ADCVDD0

FB20

GND

R83

REXTA

C147
4.7uF
C0603

VREFN4

C150
3300pF
C0603

C142
4.7uF
C0603

C144
4.7uF
C0603
GND

ADCVDD0
C148
0.1uF
C0603

GND

VPLLVDD

VPLLVDD

C141
0.1uF

0603 PUT ON NEARLY BGA

C151
0.1uF
C0603
GND

ADCVDD4

DV18A

0603 PUT ON NEARLY BGA

C154
4.7uF
C0603

C155
0.1uF
C0603

70R

C158
0.1uF
C0603

C159
0.1uF
C0603

C160
0.1uF
C0603

C161
0.1uF
C0603

R84

AUXTOP
TP2

50
R85

C162
0.1uF
C0603
GND

FB19

PWM2VREF

GND

VFEVDD1

TP1
LVDDA

GND

GND

DV18A

ADCVDD4

C157
0.1uF
C0603

CE24
47uF/16v

AUXBOTTOM

50

GND

0603 PUT ON NEARLY BGA

ADCVDD0
C163
0.1uF
C0603
GND

AV33

VREFP4
C140
0.1uF

ADCVDD0

P1-V5

GND

ADCVDD0
75R

C129
0.1uF
C0603

GND
LVDDA

ADC_VDD
ADC_VDD

C128
4.7uF
C0603

LVDDA
70R

LVDDA

FB17

C123
0.1uF
C0603

ANALOGVDD

OFF

C122
4.7uF
C0603

GND

FB15

C131
0.1uF

0 ohm

CE17
22uF/25v

GND

0603

Fix regulator

APLLVDD

AV33

Rdown

C119
0.1uF
C0603

GND

GND

GND

AZ1117

C118
4.7uF
C0603

CE16
47uF/16v

+
C120
1500pF
C0603

C127

0.1uF

C115
0.1uF
C0603

ANALOGVDD

IN

C114
4.7uF
C0603

APLL_CAP

ADC_VDD

FB14

CE15
22uF/25v

GND

C121
0.1uF
C0603

CM1117-3.3V

GND
ADCPLLVDD

C113
4.7uF
C0603

Note for Fix or Adj Regulator

3

C108
4.7uF
C0603
R81

FOR ADCVDD

U7

70R

DACVDD

DACVDD

VCC

FB13

GND

DACVDD

C106
4.7uF
C0603

CE14
+

10uF/50v

DV33A

FOR DACVDD

AV33

C164
3300pF
C0603

C165
3300pF
C0603

C166
3300pF
C0603

C167
3300pF
C0603

MiCO Confidential
Title

Size
C
Date:

MiCO LCD TV - MediaTek MT8203 Solution

Doc Number

MT8203 ANALOG&DIGIT DECOUPLE

Thursday, September 15, 2005

E

Sheet

of

Rev
V0.1
10

ADCPLLVDD1
ADCPLLVDD
AUXTOP
AUXBOTTOM
REXTA
APLL_CAP
PWM2VREF
ADCVDD0
AVCM
VOCM
VICM
VREFP4
VREFN4
DACFS
DACVREF
DACVDD
LVDDA
IR

ADCVDD4

4
4
4
4
4
4

ADCPLLVDD1
ADCPLLVDD
AUXTOP
AUXBOTTOM

4
4
4
4

REXTA
APLL_CAP
PWM2VREF

4
4
4

ADCVDD0

AVCM

VOCM
VICM

4
4

VREFP4
VREFN4

4
4

DACFS
DACVREF
DACVDD
LVDDA

4
4
4
4

IR

7,10

ADCVDD4

ADCVDD4
ADCVDD4
MPX1
MPX2
GND
VREFP4
VREFN4
GND
ADIN4
ADIN3
ADIN2
ADIN1
ADIN0
ADCVDD
PWM2VREF
AUXTOP
AUXBOTTOM
GND
VPLLVDD
VPLLVDD
GND
GND
REXTA
VPLLVDD
LVDDA
AP7
AN7
CLK2+
CLK2GND
AP6
AN6
AP5
AN5
LVDDA
AP4
AN4
AP3
AN3
GND
CLK1+
CLK1AP2
AN2
LVDDA
AP1
AN1
AP0
AN0
GND
DACVDD
DACVREF
DACFS
GND
DACVDD
GND
DACVDD
G
GND
B
R
VSYNC
HSYNC

DV33A
2

GND

DV18A

GND

ANALOGVDD
XTALO
XTALI
GND
APLL_CAP
GND
APLLVDD
ANALOGVDD
GND
VI0
VI1
VI2
VI3
VI4
VI5
VI6
DV18A
VI7
VI8
VI9
VI10
VI11
GND
VI12
VI13
VI14
VI15
GND
VI16
VI17
VI18
VI19
VI20
VI21
VI22
VI23
DVIODCK

VGAVSYNC#
HSYNC_VGA
GND
DV18A
GND
ADCPLLVDD1
ADCPLLVDD
GND
GND
ANALOGVDD

ADCVDD0
REDRED+
GREENGREEN+
VGASOG
BLUEBLUE+
GND

ADCVDD0
VOCM
GND
VICM
ADCVDD0
CRCR+
CBCB+
YY+
SOY
GND

VFEVDD1
ADCVDD4
SIF
AF
ADCVSS4
REFP4
REFN4
ADCVSS
ADIN4
ADIN3
ADIN2
ADIN1
ADIN0
ADCVDD
PWM2VREF
AUXVTOP
AUXVBOTTOM
VPLLVSS
VPLLVDD
DLLVDD
DLLVSS
BGVSS
REXTA
BGVDD
LVDDA
A7P
A7N
CLK2P
CLK2N
LVSSA
A6P
A6N
A5P
A5N
LVDDB
A4P
A4N
A3P
A3N
LVSSB
CLK1P
CLK1N
A2P
A2N
LVDDC
A1P
A1N
A0P
A0N
LVSSC
DACVDDC
VREF
FS
DACVSSC
SVM
DACVDDB
DACVSSB
DACVDDA
G
DACVSSA
B
R
DE
VSYNCO
HSYNCO
VCLK
EBO7
EBO6
EBO5
EBO4
DVDD3I
EBO3
EBO2
EBO1
EBO0
EGO7
DVSS18
EGO6
EGO5
EGO4
EGO3
EGO2
EGO1
EGO0
ERO7
ERO6
ERO5
DVDD18
ERO4
ERO3
ERO2
DVSS3
ERO1
ERO0
OBO7
OBO6
OBO5

2
1

DE_DVI
VSYNC_DVI
HSYNC_DVI
DVDD18
AOSDATA0
AOSDATA1
AOSDATA2
DVDD3I
AOSDATA3
LIN
AOBCK
AOLRCK
AOMCLK
DVSS3
DQ24
DQ25
DQ26
DVDD2
DQ27
DQ28
DVSS2
DQ29
DVDD2
DQ30
DQ31
DQS3
DQM1
DVSS18
DQS2
DQ23
DQ22
DVSS2
DQ21
DQ20
DVDD18
DQ19
DVDD2
DQ18
DQ17
DQ16
RA4
DVSS2
RA5
RA6
RA7
RA8
DVSS18
RA9
RA11
CKE
DVDD2
RCLK
RCLKB
DVSS2
RA3
RA2
RA1
RA0
RA10
BA1
DVDD2I
DVDD18
BA0
RCS#
RAS#
DVSS2
CAS#
RWE#
DQ8
DQ9
DQ10
DVDD2
DQ11
DVSS18
DQ12
DQ13
DVSS2
DQ14
DQ15
DQS1
AVSS18
AVDD18
RVREF
DVSS18
DQM0
DQS0
DQ7
DVDD2
DQ6
DQ5
DVSS2
DQ4
DQ3
DVDD2
DQ2
DQ1
DQ0

MT8205

4
3

CE25
10uF/50v

SW4P/DIP/FLAT

DE_DVI
VSYNC_DVI
HSYNC_DVI
DV18A

C24
D24
A24
Y24
A25
A26
B26
F23
B25
B24
C26
C25
E24
N15
G26
G25
F26
F24
F25
E26
N16
E25
G24
D26
D25
H25
H26
P14
J25
J26
K25
P16
K26
L25
AA24
L26
H24
M25
M26
N25
J23
R16
J24
K23
K24
L23
R14
L24
M23
N26
H23
P26
P25
P15
M24
N23
N24
R26
P24
P23
U23
AA23
R24
R23
T24
R15
T23
U24
W26
V25
V26
V23
U25
T13
U26
T25
T15
T26
R25
W25
W23
Y23
G23
T16
Y26
Y25
AA26
V24
AA25
AB26
T14
AB25
AC26
W24
AC25
AD26
AD25

AOSDATA1

GND

DV33A

R87
47k

DACBCLK

10Kx4
8
6
4
2

VI0
VI2
VI5
VI6

RN18
7
5
3
1

10Kx4
8
6
4
2

VI9
VI10
VI13
VI14

RN19
7
5
3
1

10Kx4
8
6
4
2

VI17
VI18
VI21
VI22

RN20
7
5
3
1

10Kx4
8
6
4
2

VI7
VI4
VI3
VI1

RN21
7
5
3
1

10Kx4
8
6
4
2

VI15
VI12
VI11
VI8

RN22
7
5
3
1

10Kx4
8
6
4
2

VI23
VI20
VI19
VI16

RN23
7
5
3
1

10Kx4
8
6
4
2

5
5

F_OE#

R92
10k

TP3

TP4

DV33A

DV18A

DV33A

VSYNC
HSYNC

VSYNC
HSYNC

9
9

VGASDA
VGASCL

VGASDA
VGASCL

6
6

RED+
REDGREEN+
GREENBLUE+
BLUE-

RED+
REDGREEN+
GREENBLUE+
BLUE-

8
8
8
8
8
8

VGASOG

VGAVSYNC#

HWSCL
HWSDA
VGASCL
VGASDA

8
6

VGAVSYNC#

CVBS0+
CVBS0SY+
SYSC+
SCY+
YCB+
CBCR+
CR-

8
8
8
8
8
8
8
8
8
8
8
8

AP[0..7]
AN[0..7]

AP[0..7]
AN[0..7]

9
9

CLK1+
CLK1CLK2+
CLK2-

CLK1+
CLK1CLK2+
CLK2-

9
9
9
9

SCL
SDA

SCL
SDA

10
10

DACBCLK
DACMCLK
DACLRC

10
10
10

DOUT

DOUT

10

SOY

SOY

CVBS1+
CVBS1-

CVBS1+
CVBS1-

TXD
RXD
MUTE

R94
R95

R/NC
R/NC

R
G
B
PWM0
PWM1

8
8
9
9
9
9
10

AOSDATA1
TXD
RXD
MUTE

SDA
SCL

10
6
6
10

MiCO Confidential

DV18A

VGASOG
HSYNC_VGA

CVBS0+
CVBS0SY+
SYSC+
SCY+
YCB+
CBCR+
CR-

R
G
B
PWM0
PWM1

R96
R97

0
0

Size
C
Date:

9
10
8
8

UP3_5 FOR S/W SDA

HWSDA
HWSCL

UP3_5
UP3_4
A

ORO1
ORO0
MPX1
MPX2

7
10

DACBCLK
DACMCLK
DACLRC

Title

C169
0.1uF

7
1
7
7
9
7

UP3_4 FOR S/W SCL

R93
1k

TP5

C168
0.1uF

PWM0
PWM1
IR
RxD
TxD
GND

GND
URST#
UP3_4
UP3_5

DV18A

DV33A

F_OE#
IOWR#
IOCE#

OGO1
DV33A
OGO0
ORO7
ORO6
ORO5
ORO4
DV18A
ORO3
ORO2
ORO1
ORO0
F_A15
GND
F_A14
F_A13
F_A12
F_A11
F_A10
F_A9
F_A8
F_D0
F_D1
DV18A
F_D2
F_D3
F_D4
GND
F_D5
F_D6
F_D7
F_A0
F_A1
F_A2
F_A3
F_A4
F_A5
F_A6
F_A7
F_A16
DV33A
F_A17
F_A18
F_A19
F_A20
GND
F_A21

GND

OBO4
OBO3
OBO2
OBO1
OBO0
MUTE

ADIN4
R91
10k

CVBS2+

R90
10k

CVBS2-

R89
10k

ADIN3

ADIN2

ADIN0

ADIN1
R88
10k

ORO6
ORO7
ORO5
ORO4
ORO3
ORO2

OGO[0..1]
OBO[0..7]

HSYNC_VGA

5
5

F_A[0..21]
F_D[0..7]

AOSDATA1

IOWR#
IOCE#

5
5
5
5
5
5
5
5
5
5
5
5
5
5

F_OE#
ORO6
ORO7
ORO5
ORO4
ORO3
ORO2

OGO[0..1]
OBO[0..7]

BGA388/
MT8203

URST#
A_DQS[0..3]
A_RA[0..11]
A_BA[0..1]
A_DQM[0..1]
A_DQ[0..31]
A_CLK
A_CLK#
A_CKE
A_CS#
A_RAS#
A_CAS#
A_WE#
SDV25
VREF

F_A[0..21]
F_D[0..7]

ORO1
ORO0
MPX1
MPX2

RN17
7
5
3
1

DVIODCK
HSYNC_DVI
DE_DVI
VSYNC_DVI

URST#
A_DQS[0..3]
A_RA[0..11]
A_BA[0..1]
A_DQM[0..1]
A_DQ[0..31]
A_CLK
A_CLK#
A_CKE
A_CS#
A_RAS#
A_CAS#
A_WE#
SDV25
VREF
IOWR#
IOCE#

DV33A
DOUT
DACBCLK
DACLRC
DACMCLK
GND
A_DQ24
A_DQ25
A_DQ26
SDV25
A_DQ27
A_DQ28
GND
A_DQ29
SDV25
A_DQ30
A_DQ31
A_DQS3
A_DQM1
GND
A_DQS2
A_DQ23
A_DQ22
GND
A_DQ21
A_DQ20
DV18A
A_DQ19
SDV25
A_DQ18
A_DQ17
A_DQ16
A_RA4
GND
A_RA5
A_RA6
A_RA7
A_RA8
GND
A_RA9
A_RA11
A_CKE
SDV25
A_CLK
A_CLK#
GND
A_RA3
A_RA2
A_RA1
A_RA0
A_RA10
A_BA1
SDV25
DV18A
A_BA0
A_CS#
A_RAS#
GND
A_CAS#
A_WE#
A_DQ8
A_DQ9
A_DQ10
SDV25
A_DQ11
GND
A_DQ12
A_DQ13
GND
A_DQ14
A_DQ15
A_DQS1
GND
DV18A
VREF
GND
A_DQM0
A_DQS0
A_DQ7
SDV25
A_DQ6
A_DQ5
GND
A_DQ4
A_DQ3
SDV25
A_DQ2
A_DQ1
A_DQ0

AE2 OBO4
AF1 OBO3
AF2 OBO2
AE3 OBO1
AF3 OBO0
AE4 OGO7
AF4 OGO6
AC5 OGO5
T11 DVSS18
AD5 OGO4
AE5 OGO3
AF5 OGO2
AC6 OGO1
AD9 DVDD3
AD6 OGO0
AE6 ORO7
AF6 ORO6
AC7 ORO5
AD7 ORO4
AD18DVDD18
AE7 ORO3
AF7 ORO2
AC8 ORO1
AD8 ORO0
AF8 HIGHA7
P12 DVSS18
AE9 HIGHA6
AF9 HIGHA5
AE10 HIGHA4
AF10 HIGHA3
AC11HIGHA2
AD11HIGHA1
AF12 HIGHA0
AE15 AD0
AD15AD1
AC19DVDD18
AC15AD2
AF16 AD3
AE16 AD4
R12 DVSS3
AD16AD5
AC16AD6
AF17 AD7
AD17IOA0
AD14IOA1
AE14 IOA2
AF14 IOA3
AF13 IOA4
AE13 IOA5
AD13IOA6
AC13IOA7
AE8 A16
AC10DVDD3I
AC17A17
AE12 IOA18
AD12IOA19
AE11 IOA20
T12 DVSS18
AF11 IOA21
AE17 IOALE
AF15 IOOE#
AC12IOWR#
AC14IOCS#
AF18 WR#
AE18 RD#
AD10DVDD3
AF19 INT0#
AE19 UP12
AF20 UP13
AE20 UP14
AD19DVDD18
AD20UP15
AC20UP16
AF21 UP17
AE21 UP30
AD21UP31
P13 DVSS18
AC21PRST#
AD22UP34
AC22UP35
AF22 FCICLK
AE22 FCICMD
AF23 FCIDAT
AE23 GPIO0
AD23PWM0
AC23PWM1
AF24 IR
AE24 RXD
AD24TXD
R13 DVSS3
AC24ICE
AF25 SCL
AE25 SDA
AF26 SCL0
AE26 SDA0
AB23 SCL1
AB24 SDA1

OBO7
OBO6
OBO5

C3
D3
C1
C2
L11
D1
D2
F2
D4
E1
E2
E3
E4
F1
F4
F3
G3
J3
G4
H3
K3
K4
J4
H4
L3
G2
G1
H2
H1
M12
J2
J1
K2
K1
L4
L2
L1
M2
M1
M11
N2
N1
P2
P1
M3
R2
R1
T2
T1
N12
N3
M4
N4
N11
T4
P3
R3
P4
U4
R4
U3
V4
T3
U1
U2
V1
V2
V3
W1
W2
AC9
W3
W4
Y1
Y2
Y3
P11
Y4
AA1
AA2
AA3
AA4
AB1
AB2
AB3
AB4
AC1
AC18
AC2
AC3
AC4
R11
AD1
AD2
AD3
AD4
AE1

2=4

XTALI
XTALO
ANALOGVDD
ADCVDD
APLLVDD
VPLLVDD

SW1

1=3

XTALI
XTALO
ANALOGVDD
ADCVDD
APLLVDD
VPLLVDD

R86
10k

URST#

VFEVSS1
AVCM
ADCVDD0
CVBS2N
CVBS2P
CVBS1N
CVBS1P
CVBS0N
CVBS0P
ADCVSS0
REFP0
REFN0
ADCVDD1
SCN
SCP
SYN
SYP
ADCVSS1
REFP1
REFN1
VFEVDD0
VOCM
VFEVSS0
VICM
ADCVDD2
CRN
CRP
CBN
CBP
YN
YP
SOY
ADCVSS2
REFP2
REFN2
MON0
MON1
ADCVDD3
RN
RP
GN
GP
SOG
BN
BP
ADCVSS3
REFP3
REFN3
VSYNC
HSYNC
DVSS
DVDD
ADCPLLVSS1
ADCPLLVDD1
ADCPLLVDD
ADCPLLVSS
SYSPLLVSS
SYSPLLVDD
TESTP
TESTN
XTALVDD
XTALO
XTALI
XTALVSS
APLL_CAP
APLLVSS
APLLVDD
DMPLLVDD
DMPLLVSS
VI0
VI1
VI2
VI3
VI4
VI5
VI6
DVDD18
VI7
VI8
VI9
VI10
VI11
DVSS3
VI12
VI13
VI14
VI15
DVSS18
VI16
VI17
VI18
VI19
VI20
VI21
VI22
VI23
VCLK_DVI

D3
1N4148/SMD

L12
D5
C4
B1
A1
B2
A2
B3
A3
L13
B4
A4
C5
B5
A5
B6
A6
M13
D6
C6
D7
B7
N13
A7
C7
B8
A8
B9
A9
B10
A10
C8
D10
D9
C9
D11
C11
D8
B11
A11
B12
A12
D13
B13
A13
C10
D12
C12
C13
C14
N14
D14
L14
D15
C15
M14
L15
D16
B14
A14
C16
B15
A15
M15
A16
D18
D17
C17
C18
B16
A17
B17
A18
B18
C19
D19
E23
A19
B19
C20
D20
A20
L16
B20
C21
D21
A21
M16
B21
C22
D22
A22
B22
C23
D23
A23
B23

U8

ADCVDD0
SCSC+
SYSY+
GND

GND
AVCM
ADCVDD0
CVBS2CVBS2+
CVBS1CVBS1+
CVBS0CVBS0+
GND

DV33A

MiCO LCD TV - MediaTek MT8203 Solution

Doc Number

Rev
V0.1

MT8205 PBGA 388

Thursday, September 15, 2005

E

Sheet

of

10

Power ON alive source

CE27
220uF/16v

FB21
OUT
OUT

2
4
0805

U10 M1117-3.3V
FB22

DV33

75R
+

C171
0.1uF

+5V

DV33

Vout

CE28
220uF/16v

SOT223

0805

75R

ADJ/GND

CM1117-3.3V

IN

ADJ/GND

U9
3

IN

CE26
+

C172
0.1uF

C170
0.1uF

220uF/16v

OUT
OUT

2
4
+

VCC

CE29
220uF/16v

SOT223

C173
0.1uF

DV33A
DV33A

IN

OUT
OUT

AV33

2
4

0805

75R
+

75R

CE32
220uF/16v

C176
10uF/10v

C177
0.1uF

CE30
100uF/16v

IN

OUT
OUT

+
C174
0.1uF

DV18A

Vout

2
4

3
0805

ADJ/GND

FB24

FB23

AV33

ADJ/GND

U11 CM1117-1.8V
U12 CM1117-3.3V

SOT223

CE31
220uF/16v

C175
0.1uF

SOT223

1.25x(1+300/680)=1.8V

1.25x(1+180/110)=3.3V

MiCO Confidential
Title
Size
C
Date:
A

MiCO LCD TV - MediaTek MT8203 Solution

Doc Number

Rev
V0.1

LDO

Thursday, September 15, 2005

E

Sheet

of

10

MT8203E (PBGA388) LCDTV BOARD 4 LAYERS

TXD
RXD

01.INDEX & POWER CONNECTOR

02. LDO
03.MT8203 PBGA 388
04.MT8203 ANALOG&DIGIT DECOUPLE
05.DDR MEMORY & FLASH
06.VGA IN & PC AUDIO IN
07.VIDEO IN & TUNER IO
08. AV IN
09.LVDS/CRT/BACK LIGHT CONTROL
10.AUDIO WM8776/ KEYPAD

+12V
TUNER_12V
ORO7

VCC

+12V

R98
10k

J4
5
4
3
2
1

DIP8/P2.0

SYS_PWR

+5V

7,10
7,10

+12V
TUNER_12V
ORO7

9
7
3

ORO7 High :POWER OFF

ORO7 LOW :POWER ON

Q3
R99

1
2
3
4
5
6
7
8

3,6
3,6

SCL_5V
SDA_5V

+5V

J3

ORO7

5x1 W/HOUSING
SIP5\2

TXD
RXD

SCL_5V
SDA_5V

SOT23
2N3904

4.7k

TO Power BD
+5V

CE33
220uF/16v
C220UF16V/D6H11

HOLE/GND

H1
9
8
7
6

2
3
4
5

2
3
4
5

FB25
120R

FB26
TUNER_12V
+

HOLE/GND

H2
9
8
7
6

2
3
4
5

CE34
220uF/16v
C220UF16V/D6H11

75R
0805

CE35
47uF/16v

FOR Tuner

C178
0.1uF

2
3
4
5

9
8
7
6

For Tuner

+12V

9
8
7
6

FB27
120R

+5V
+5V

SYSTEM EEPROM

HOLE/GND

H3
9
8
7
6

2
3
4
5

2
3
4
5

0.1uF

FB30
120R

R100
4.7k

U13

C179

9
8
7
6

1
2
3
4

NC
NC
NC
GND

VCC
WP
SCL
SDA

8
7
6
5

R101
4.7k

AUIO IN/OUT GND

DIGITAL GND

ANALOG INPUT GND

SCL_5V
SDA_5V

EEPROM 24C16
SOP8

HOLE/GND

H4
9
8
7
6

2
3
4
5

2
3
4
5

9
8
7
6

FB31
120R

MiCO Confidential
Title
Size
C
Date:
A

MiCO LCD TV - MediaTek MT8203 Solution

Doc Number

Rev
V0.1

INDEX & POWER CONNECTOR

Thursday, September 15, 2005

E

Sheet

of

10

Modify I2C by Zheng.Guo. 16/8

DV33A

QF1
2N7002

MODIFIED FROM 10K-->100K BY BIN_WANG .16/7/05.AVOID AUDIO BOMB

VCC

Del Parts
YPBPR2_R

CE36

YPBPR2_L

CE37

10uF/25v

R102

100k

10uF/25v

R104

100k

SCL_5V

WHEN OPEN THE POWER

FB32

R190
4.7k

SCL

DV33A
HPVDD

VGA_IN_R

CE39

VGA_IN_L

CE40

0603 120R

CE38

10uF/25v

R106

100k

10uF/25v

R107

100k

R192
4.7k

C180
0.1uF

3
3
1,7
1,7

PWM1
MUTE
SCL_5V
SDA_5V

7
7
6
6
7
7
7
7
3
3
3
3
3
3
3

S1_AV1_L
S1_AV1_R
VGA_IN_L
VGA_IN_R
YPBPR1_L
YPBPR1_R
YPBPR2_L
YPBPR2_R
SCL
SDA
DACBCLK
DACMCLK
DACLRC
DOUT
AOSDATA1

S1_AV1_L
S1_AV1_R
VGA_IN_L
VGA_IN_R
YPBPR1_L
YPBPR1_R
YPBPR2_L
YPBPR2_R
SCL
SDA
DACBCLK
DACMCLK
DACLRC
DOUT
AOSDATA1
PWM1
MUTE
SCL_5V
SDA_5V

QF2
2N7002

10uF/25v

SDA_5V

CE43

100k

10uF/25v

R111

100k

10uF/25v

R112

100k

R113

100k

SDA

DV33A
C182
10pF

R108

WHEN OPEN THE POWER

50k

CE42

10uF/25v

S1_AV1_L

CE41

50k

MODIFIED FROM 10K-->100K BY BIN_WANG .16/7/05.AVOID AUDIO BOMB

S1_AV1_R

C181
10pF

R110

48
47
46
45
44
43
42
41
40
39
38
37

+
HPVDD

AIN2R
AIN3L
AIN3R
AIN4L
AIN4R
AIN5L
AIN5R
AINOPL
AINVGL
AINOPR
AINVGR
AGND

U14

DACBCLK
DACMCLK
AOSDATA1
DACLRC

36
35
34
33
32
31
30
29
28
27
26
25

0603 120R
+

CE53
47uF/16v

VMIDADC
AUXL
AUXR
HPVDD_A

TP6

10uF/25v

TP7

CE49
10uF/25v

VMIDDAC
+

AUSPR
AUSPL

VMIDADC

10uF/25v

CE48

CE50
10uF/25v

CE47
10uF/25v

1
2
3
4

MUTE

C184
0.1uF

C185
0.1uF

4x1 W/HOUSING
SIP4\2
MUST USE SHIELD CABLE

C186
0.1uF

WM8776

CE51

CODHPOUTR

CODHPOUTR

R115

10uF/25V

220uF/16v

10k

HPOUTR
R116
47k

CE54
CODHPOUTL

FB28

TP9

CE55
AUSPL

COD_VOUTL

TP8

CE52
AUSPR

COD_VOUTR

CODHPOUTL

C187
0.1uF

SDA14

ADCREFP

CE46

COD_VOUTR
COD_VOUTL

HPVDD

SDA14
SCL14

DVDD

DVDD

DVDD

DACLRC

FB33
DV33

R114
1k

SCL14

R208
33
R/SMD/0603

TO AUDIO BD

13
14
15
16
17
18
19
20
21
22
23
24

DACLRC
DV33

R207
33
R/SMD/0603

SDA

J5

ADCREFP

ADCLRC
DGND
DVDD
MODE
CE
DI
CL
HPOUTL
HPGND
HPVDD
HPOUTR
NC

GND

SCL

33R

DACBCLK
DACMCLK
DOUT

R193

AVDD
ADCREFP
ADCREFGND
VMIDADC
AUXL
AUXR
DACREFP
DACREFN
VMIDDAC
VOUTR
VOUTL
NC

AIN2L
AIN1R
AIN1L
DACBCLK
DACMCLK
DIN
DACLRC
ZFLAGR
ZFLAGL
ADCBCLK
ADCMCLK
DOUT

C183
0.1uF

1
2
3
4
5
6
7
8
9
10
11
12

CE45
10uF/25v

10uF/25v

HPOUTL

CE44

YPBPR1_L

R109

YPBPR1_R

HPVDD

0603 120R

TWO WIRE SERIAL CONTROL DEVICE ADDRESS 0x34h

R117

10uF/25v
TP10

220uF/16v

10k

R118
47k

PWM1

ORO0
URST#
IR

OBO[0..7]

ORO0
URST#
IR

OBO[0..7]

3
3
3,7

R119
R122

R121
10K
R0603
R124

4.7K

OBO7

Q4
2N3906

4.7K

R199

R198

R200

TV/AV
MENU
VOLVOL+
CHCH+
IR

1
2
3
4
5
6
7
8
9
10
11
12
13
13x1 W/HOUSING
SIP13\2

Q5
2N3906

FB
FB
FB
FB
FB
FB

+5V

R126

R125

POWER ON/OFF
R123
NC/0

OBO6

10k 10k 10k 10k 10k 10k 10k

FB34
FB35
FB36
FB37
FB38
FB39

510 LED_RED
510 LED_GRN
ORO0
DV33A

R120
10K

R197

J6
OBO0
OBO1
OBO2
OBO3
OBO4
OBO5

DV33A

R0603

R196

R194

ORO0 High :SYSTEM POWER OFF

ORO0 LOW :SYSTEM POWER ON

R195

+5V

KEYPAD - MAX 8-KEYS

IR & POWER ON LED

DV33A

MiCO Confidential
Title
Size
C
Date:
A

MiCO LCD TV - MediaTek MT8203 Solution

Doc Number

Rev
V0.1

AUDIO WM8776/ KEYPAD

Wednesday, September 28, 2005

E

Sheet

of

10

CVBS0---TUNER1
CVBS1---FRONT BD AV_IN
TU_VCC

AV , TUNER I/O

J7

TU_12V

1
2
3
4
5
6
7
8
9
10
11
12

SDA_5V
SCL_5V
SIF1_OUT
AF1_OUT
TV_GND
CVBS0
4

OGO[0..1]

S1_AV1_R

+12V

10

YPBPR1_L
YPBPR1_R
YPBPR2_L
YPBPR2_R

10
10
10
10

+12V

IR

IR

Y2_INDVD

R158

VCC

Y2B

Y2_GNDB

DVD Connector
VCC
8/18 modify by steven R146
10k
R149
10k

1,9
ORO4

3,10

ORO5

3
1

SOT23
2N3904
Q8

S1
G1
S2
G2

D1
D1
D2
D2

VDVD

8
7
6
5

IR7314
SOP8
CE63
470uF/16v
C470UF16V/D8H14

4.7k

1
2
3
4

1
2
3
4
5

R141
CB

CB1SWB
VCC

0/NC
3

R144
10K

10K
CE60

CR1_INB

R167
75

R140
10K

R143

R147
CR1SWB

22uF/10V

CR

R148

CR1_GNDB
CB2_GNDB

10K

0/NC
VCC
R151
10K

R168

CR2_GNDB

J10

0/NC

22uF/10V

CB2B

CR2B

D9
BAV99
Q7

CE59

CB1_INB

VCC
CR2_INDVD

VCC

Y2B

CE61

R153
Y

Y2SWB

22uF/10V
R154

Y2_GNDB

R170
75

VCC

0/NC
R155
10K

10K
CR2_GNDB

CB2B

CE62

R159

22uF/10V

CB

CB2SWB

R162

CB2_GNDB

Y1_GNDB

CB1_GNDB

D8
BAV99

VCC
10k
R156

R157
4.7k

SOT23
2N3904
Q6

1
2
3
4
5
6
7
8
9
10
CON10

VCC

Y2_GNDB

R165

J9

R139

VCC

IR_DVD
CB2_GNDB
CB2_INDVD
Y2_GNDB
Y2_INDVD
CR2_GNDB
CR2_INDVD

IR_DVD

IR

CB2_INDVD
YPBPR2/R
YPBPR2/L

R138
Y1SWB

22uF/10V

10K

VCC

VCC

CE58

R160
75

D7
BAV99
2

S1_AV1_R

Y1_INB

C189
0.1uF

YPBPR1_L
YPBPR1_R
YPBPR2_L
YPBPR2_R

TU_12V
+ CE57
1000uF/16v

70R

Optional for one component.Added by Bin_wang 14/7/05

R137
10K

TUNER_12V

10

VCC
FB43

Added by Zheng_guo 21/7/05

TUNER_12V

1,10

S1_AV1_L

C188
0.1uF

1000uF/16v

1,10

3
3
3
3

CE56
+

S1_AV1_L

70R

SDA_5V

ORO6
ORO4
ORO5
ORO2

FB41
TU_VCC

SCL_5V

OGO[0..1]
ORO6
ORO4
ORO5
ORO2

J9
VCC

AV_L
AV_R
SY_GND

AF1_OUT

YPBPR1/L
YPBPR1/R

SDA_5V
TUNER_12V

SIF1_OUT

CB1_INB
CB1_GNDB

SCL_5V

8
8
8
8
8
8

21
19
17
15
13
11
9
7
5
3
1

AF1_OUT

SC
SC_GND
CVBS0
CVBS0_GND
CVBS1
CVBS1_GND

22
20
18
16
14
12
10
8
6
4
2

SIF1_OUT

8
8
8
8
8
8
3
8
8

CVBS1
CVBS1_GND
SC
SC_GND
SY

DIP11X2/P2.54/R2
VIDEO CONNECTOR

SC
SC_GND
CVBS0
TV_GND
CVBS1
CVBS1_GND

Y
Y_GND
CB
CB_GND
CR
CR_GND
SOY
SY
SY_GND

Y1_INB
Y1_GNDB
CR1_INB
CR1_GNDB

CON12
SIP12\2

Y
Y_GND
CB
CB_GND
CR
CR_GND
SOY
SY
SY_GND

VCC

VCC

R161

CB2_GNDB

VCC

0/NC
R163
10K

10K

CON5

R164

+
CR2B

CE64

CR2SWB

22uF/10V

CR

C190
0.1uF

CR2_GNDB

0/NC

R166
10K

OGO0

COMPONENTS SWITCH.

OGO1

NEARLY YPBPR1-CON.
OGO0

ORO6
HP_SENSE

R169
0

OGO1

ORO6

DV33

Y1_GNDB
DV33

CB1_GNDB

FB46
70R

CR1_GNDB
R171
10K

NEARLY YPBPR2-CON.

TP11

ORO2
CB1SWB
CB2SWB
CB
Y1SWB
Y2SWB
Y
GNDS

Y2_GNDB
CB2_GNDB
CR2_GNDB

AV_L R176
AV_R

YPBPR1/L

15K
15K

YPBPR1_L

YPBPR2/R

15K

15K S1_AV1_R

YPBPR2_L

VCC
E#
I0D
I1D
YD
I0C
I1C
YC

16
15
14
13
12
11
10
9

GNDS

CR1SWB
CR2SWB
CR

C191

YPBPR2_R
YPBPR2_L
S1_AV1_R
S1_AV1_L
YPBPR1_R
YPBPR1_L

R180

R188

R178

SOY
0

MODIFIED BY BIN_WANG.16/7/05

YPBPR1_R
15K

R177

S
I0A
I1A
YA
I0B
I1B
YB
GND

IDTQS3VH257
TSSOP16/SMD

S1_AV1_L

R179

YPBPR1/R

YPBPR2/L

15K

U15
1
2
3
4
5
6
7
8

4.7nF

CR_GND
CB_GND

R187
YPBPR2_R

R181 R182 R183 R184

75K
75K
75K
75K

Y_GND

R185 R186
75K
75K

MiCO Confidential

MODIFIED FROM 15k-->0 BY BIN_WANG 16/7/05.

Title
Size
C
Date:
A

MiCO LCD TV - MediaTek MT8203 Solution

Doc Number

Rev
V0.1

VIDEO IN & TUNER IO

Thursday, September 15, 2005

E

Sheet

10

of

10

C1

1
22pF

NPO

5%
R1

10K 5%

10K

1
2

NIN

3
4

C55
1n

MUTEC

C24

C15
2.2UF

47K

R6

R8

R9
10K

10

D1

C11

MBRS130LTR

470NF

5%

R15

X5R

5%

10K

2
1UF
10

22pF

BS

5%

2
1000UF/25V

5%

C9

ATA-120

100K

VPP

EN

R7

AGND

SW

AGND

5%

C38

10uH

22

L5

D2

C17

6.2V

390PF

C16

C
100NF
1

2
X5R

PGND

RC4558

PIN

FILM

X7R

1
1

1UF

C4
100UF/25V

22

X7R

R12

R3

100NF

11

4K7
5%

C3

U1

1UF

C54
1n

R4

5%

R67

21

4K7
5%

C8

C6

21

R66

21

1K8
5%

X5R

R47

+
C7

4.7uF
NPO

+
OUT

C20 2

C5

100K
4.7nF

10UF

5%

100K
R5

U2A

AUSPL

1
C10
100UF/25V

100NF

22UF/16V

+
C12

10K

10K

5%

5%

1
5%

R11
R10
C14

+24V
R2

+24V

82K

NPO

X7R

5%

C21

1
22pF

NPO

5%
R14
82K

+24V
R16

+24V

R39

26

22
1UF

RC4558

10K 5%

3
4

R19
C53
1n

5%

1
1
BS

7
6

2
X5R

R22

R23

D3

470NF

10

10K

MBRS130LTR

FILM

5%

C34
NS

R20
C33

1UF

2
1000UF/25V

C32

5%

10K
22pF
47K

EN

SW
VPP

ATA-120
MUTEC

C41

AGND

R21

AGND

5%

NIN

D4

C36

6.2V

390PF

R38
5%

10
5%

C52
1n

100K

1
2

10K

X5R

C39

10uH

22

L6

C35
100NF

4K7
5%

R46

100UF/25V

X7R

21

4K7
5%

PGND

C25

R45

PIN

X7R

21

21

1K8
5%

100NF

R33

R18

1UF

C31

U3

C28

+
OUT

C40
10UF

C30

5%

X5R

4.7nF

U2B

AUSPR

+
C29

4.7uF
NPO

5%

C27

100K

5%

5%

22UF/16V

100K

R17

10K

10K

R36
R37
C19

1
5%

X7R

NPO
A

A
Title
Size

Number

Revision

B
Date:
File:
4

2-Sep-2005
Sheet of
D:\\LCD TV\LCD TV.DdbDrawn By:
6

R24
3K

MUTEC

5%
R25

5%

C37

10K

2
Q1
2N3906

D
D6

R40
10K

X5R

Q3

Q2
2N3904

1UF

+24V

MUTE

5%

R41

5%

C42

1K

1N4148
+

D
R29

2N3904
5%

10K

100UF/25V
R42

AGND

1k

AGND

AGND

D10
NC

D8

LOUT

D7

1N4148

4.7V

AGND

R34
1K

Q5
2N3904

1
5%

R43
0R

Q4
2N3906
MUTEB

NC

AGND

D5

C18

ROUT

NC
R28
1k

AGND

R35
1K

2
5%

R30

Q6
2N3904

22k

D9

C51

AGND

220UF/25V

1N4148

5%

C22

10K

+24V

5%

C2

22U/16V

5%

5%

10UF
X5R

4K7

R51

5%

R53

5%

C45

5%

2
2

R13
1K

10U/16V

1
5%

R65

C49

1
R52

1n
22K

5%

2 AGND

22P

AGND

5%

R62

R27
NC

47K

RC4558

C46

1n

100K

1 C26

OUT

10K

MUTE

R50

4K7

R49

AUSPL

C60

1k8

Q7
NC

100N

B
R48

AGND

C13

100U/35V
U5A

R55

10K

R54

J10

LOUT

AGND

ROUT

10K

R63

5%

10K

rca2

+24V

5%

C44
U5B

5%

5%

10UF
X5R

C43

+
OUT

10K

5%

C47

5%

7
10U/16V

R26
1K

1
5%

R61
47K

RC4558

5%

C48

1n

1n

1
R64

R59

5%

R60
100K

4K7

Title

R58

4K7

R57

C59

1k8

AUSPR

R56

22U/16V

22K

C50

2 AGND

22P

AGND
Size

2
5%

Number

Revision

B
Date:
File:
5

2-Sep-2005
Sheet of
D:\\LCD TV\LCD TV.DdbDrawn By:
6

200R

R131B
R131A

L11

A24V

471/1KV

R132

3.3UH 3*20

A2

2K/2W

D21 HER303

D19

C38

Y2010D

102/1KV

EC12

B2

EC21

EC22

470U/35V 105 KF10*20

L4

T3E
MLT066-T2

6A

471/1KV

C6

L6

NC

24V

12V

EC11

FCH20A150

C8

R84

NC

3.3K

1000U/25V KM10*20

R103

1.5UH 4*20

D18

EC15
470U/16V KM8*11

NC

C53
471/1KV

L7

1000U/25V KM10*20 3UH 4*20

8A
36A

R104 100R

C54

470U/35V 105 KM 10*16

C37

3.5*1.5*5

NC

C52

200R

C7

R111

Y2045

10

D20

EC18 EC19
C39 102/1KV

T2D

R106 100R

470U/35V 105 KM 10*16

R110

C40

1K/1W

224/25V

1000U/16V KF10*16
EC20
1000U/16V KF10*16
1000U/16V KF10*16

R96
24V

2.2K

SGND

R60
1K

C30

R98

104/25V

C23

R100 R101

P1

4.7M

1K

1
2
3
4
5
6
7
8

4.7M

103/50V

PC817B

R99
IC6

5.7V

R102

4.7M

68K

+5V
C51
224/25V

C50

4.7M

224/25V
D30

R89 R112

TL431A

CY3

3.3K1%

LBD914

SGND

28A
R130
68K

18A

5.0V

102/400V Y1

FG3

R24

R25

300R

300R

8A

R94

R26
300R

200R

12V

R27

C44

470R

R86
3.3K

PC817B
1

B
C

SWB

R85

3.3K
2

4401

Q200
4401

470R
IC30
TL431

Z8

IC5

27V

TL431A

CON3
XH8PIN

R120

224/25V

B
3.3K1%

R87
3.3K

6.2V

C47

D17B

D17A

LBAV70

104

P3
PC817B

R119
3.3K1%

LBAV70

B2
R52 B2
A24V
150K1%
A24V

1
2
3
4

CON4
PH4PIN

30A

R62

R118
3.3K1%

1K

C42

10K

R20

R117
13K1%

R116
R115
10K

STB
3.3K

Q202
4403

R114

Q20

Z6

Q209
4401

28A

C41

36A

24V

5.7V

18V

224/25V

Q205
TIP32

R113
1K/1W

P4

5.7V

FG4

PS-ON

24V
24V
24V
24V
SGND
SGND
SGND
SGND

CON1
PH11PIN

FG2
IC7
8 HEADER

27K+-1%

R61

PH5

1
2
3
4
5
6
7
8

1
2
3
4
5
6
7
8
9
10
11
12

CON2

L5
1.5UH 4*20

EC14

1000U/35V 105 KF13*20 1000U/35V 105 KF13*20

12V
12V
12V
SGND
SGND
SGND
+5V
+5V
+5V
+5V
+5V

1K/1W

5.0V

EC10

1
2
3
4
5
6
7
8

T2C

2K/2W

EC9

STB
SGND
SGND
5.0V
5.0V

16A 17A

224/25V

A
Title
Size
B

Date:
File:
4

Number

MLT166A-SCH3

23-Jan-2006
F:\\MLT166A.DDB

Sheet of
Drawn By:
6

Revision

Z3
10R

Q9

27V/1W

MLT066-T3

4401

18V

13A

R65B
10R

VCC

R11
R123

R29

LBD914

20K

D13

R63

C17

100R

222/1KV B
27V

240K

EC5

C
11A

R55

Q10

22UF/50V

D8

LBD914

35A

11A
16A

C13

Q3

R23

331/50V

17A

1K

R19

10K

LD7550A IL

R77
Q12
4401

C25
104/25V

R74

D10

R80

33K

30A
1

OVP

P2

LBD914

4A

Q5

20K

4403

20K

31A

7NK80

Q11

LBD914

Q4

R22

4403

R30

R70 R18
10K
25A

C33

10R

1A

470R

R71
R82
3.3K

101/1KV

2.2R

T3B
MLT066-T2

18V

R90

R91 R92 R93

R45 R46 R41 R42
2.2R 2.2R 1R

1R

200R

200R

200R

R17
5.1K

Q6
R50

4403

C27

VREF

C28
104/25V

Q15
4403

D9 R58

EC8

R88
68K
25A

470R

R78

4401

3.3K

RTC1
2K

104/25V

Q14

R124

1K
LBD914

22UF/50V

C29

4A
33K

104/25V

C35

C26

224/25V

104/25V

Title

Size
A4
Date:
File:
1

9.1V/1W

0.62R/2W
Q13
4401

47R

R72 D3
47R

20K

R81

3.3K

R75

K
PC817B

R49

EC7
4.7UF/50V
20K

R13

9.1V/1W

LBD914

26A

32A

331/50V

Z5

D15

33K

104/25V

C15

18A

R76

47R

Z4

R79 331/50V

82K1%

9A
10R

R57

C14

R12

C34
222/16V NPO

R125
10K

R31

470R

HER207

C24

12K 1%
IC3

3843

103/50V

4403

R69

C22

47R

MLT066-T2

VREF

10A

R73
IC2

68K/2W

470R

3.5*1.5*5

5N80

240K

18A

L10

C18 222/1KV B

R68

HER207

Z7
R54

R48

240K

T2B

68K/2W

SWB

D14

10U/50V
VREF

R67

15V

R53

10R

EC4
100U/35V

1K

Z2

R56

13A

47R

R65A

100U/35V

D7

T3A

13A

EC6

32A

VCC

47R

EC3

T2A

D12
HER103

A
Number

MLT166A-SCH2

23-Jan-2006
F:\\MLT166A.DDB

Sheet of
Drawn By:
4

Revision

82.8

2.7W

1W

D
2A

102/500V

C2
CON0

L1

F1

R4510K

1
2

MLT066A-L1

NTC1

5A

5D-13

R3 510K

3
VH3.69-5-3

D4

34A
1

T5AH/250V 5*20

L2

MLT066A-L1

MLT070A-L101
C

R2

MLT042-L3

2A
2

21A
4

CX2
510K

CX1

0.47U/275V 14D681
471/400V Y1

PL1A

CY1
0.1U/275V
CY2 471/400V Y1

Q8

C11

1U/450V

1U/450V

22A FUS05B60
2

C16
223/630V 102/500V
13A
13A
C1

13A

L8

MLT066-T1

C10

7A

R1

HL1

D5

L3

D3SBA60
4

GND

1N5406

BG1

R36
470K+-1%

18N50

3.5*5

19A

GND

EC2B
2A

FG1

D2

R21
R9

R5
510K

Z1

LBD914

470R

R35
EC2

19A

68U/450V KM 18*30

470K+-1%

9.1V/1W

Q2
4403

47R

R14
10K

R37

R28

R32

10R

300R

22U/450V KM 13*25

R33

19A

GND

R43

470K+-1%
19A

R6
R8
C5
R7
510K

R47
20K

0.39R/2W
GND

C12

510K

1R

C3

331/50V

IC1

103/50V

R34

100K+-1%

R122

NC

10R VCC

NC

474/25V

C21

20A

EC1

R51

10U/50V

10K1%
6

R15

R16

10K

10K

PL1B

L6562D
Title

Size

A
Number

Revision

A4
Date:
File:
1

23-Jan-2006
F:\\MLT166A.DDB

Sheet of
Drawn By:
4

Basic Operations & Circuit Description

Main Electric Components
(1). MODULE:

There are 1 pc. panel and 2 pcs. PCB including 1 pc. INVERTER
board(L), 1 pc. T-CONTROL board,

(2).SIGNAL PROCESS

There are 5 pcs. PCBs including

1 pc. Audio&Tuner board,
1 pc. Main digital board,
1 pc. Keypad board,
1 pc. Remote Control Receiver board,
1 pc. DVD decoder board

(3).POWER

There are 1 pc. PCB for power.

PCB function
1. Power:

(1). Input voltage: AC 100V~240V, 47Hz~63Hz.

Input range: AC 90V(Min)~264V(Max) auto regulation.
(2). To provide power for PCBs.
a). +24V for Inverter.
b). +5Vsb for standby,
c). +5V for signal power,
d). +24V for Audio Amp power and converter to
e). +12V for Tuner power.

2. Main (Video InterFace) board:

(1).Decoder the video signal (TV,CVBS,S-VIDEO) from analog to digital

signal.
(2).Converter the Video signals( TV,CVBS,S-VIDEO ) and graphics signal
(VGA,YPbPr) from interface to progressive,
(3). Converter the Digital to fit the panel display mode and output the LVDS
signal to Panel.

3. Tuner & Audio Board:

(1)Convert TV RF signal to video and audio signal to Main board.

(2 ). Decoder the TV SIF signal to audio signal,

(3 ). Converter the audio to audio Amplifier and output to the speaker.

4. KEYBOARD

To get the main button control on LCD_TV as SOURCE,MENU,

CHANEL +,CHANEL -, VOL +,VOL-, STANDBY functions.

5. Remote control board

Receive the remote signal and active for the control.

6. T-CONTROL board
Converter the LVDS signal to the digital signal for fitting the PANEL.

7. INVERTER board
Converter the low DC voltage +24V to high AC voltage to drive the backlight.

PCB failure analysis

1. CONTROL:

a. Abnormal noise on screen.

b. No picture.

2. MAIN (VIDEO):

a. Lacking color, Bad color scale.

b. No voice.
c. No picture but with signals output, OSD and back light.
d. Abnormal noise on screen.

3. POWER:

No picture, no power output.

Basic operation of LCD-TV

1. After turning on power switch, power board sends 5Vst-by Volt to Micro
Processor IC waiting for ON signals from Key Switch or Remote Receiver.
2. When the ON signal from Key Switch or Remote Receiver is detected, Micro
Processor will send ON Control signals to Power. Then Power sends (5Vsc,
12Vsc, 24V and RLY ON, Vs ON) to PCBs working. This time VIF will send
signals to display back light, OSD on the panel and start to search available
signal sources. If the audio signals input, them will be amplified by Audio AMP
and transmitted to Speakers.
3. If some abnormal signals are detected (for example: over volts, over current,
over temperature and under volts), the system will be shut down by Power off.

LCD basic display theory.

When an electrical field is applied to the LC planes, the LC molecules re-align
themselves so that they are parallel to the electrical field. This electrical process
is known as twisted nematic field effect or TNFE. In this alignment, polarized
light is not twisted as it passes through the LC material (see Diagram 3A and
3B). If the front polarizer is oriented perpendicular to the rear polarizer, light will
pass through the energized display but will be blocked by the rear polarizer. An
LCD in this form is acting as a light shutter.
Displays with variable characters are created by selectively etching away the
conductive surface that was originally deposited on the glass. Etched areas
become the displays background; unetched areas become the displays
characters.

Diagram 3A. The off state of a TN LCD-the LC molecules form a twist and therefore
cause polarized light to twist as it passes through.

Diagram 3B. The on state-the electrical field re-aligns the LC molecules so they do
not twist the polarized light.

LCD Panel

Power

DVD
Loader

Speaker

Terminal
Connect Board

Remote Receiver

Main Board

Tuner Board

IC DESCRIPTION

-MT8205G
-AT24C02
-MX29LV160BBTC
-LP2996
-AZ1117/H
-WM8776
-MX232A
-ISAV330

OBO4
OBO3
OBO2
OBO1
OBO0
OGO7
OGO6
OGO5
DVSS18
OGO4
OGO3
OGO2
OGO1
DVDD3
OGO0
ORO7
ORO6
ORO5
ORO4
DVDD18
ORO3
ORO2
ORO1
ORO0
HIGHA7
DVSS18
HIGHA6
HIGHA5
HIGHA4
HIGHA3
HIGHA2
HIGHA1
HIGHA0
AD0
AD1
DVDD18
AD2
AD3
AD4
DVSS3
AD5
AD6
AD7
IOA0
IOA1
IOA2
IOA3
IOA4
IOA5
IOA6
IOA7
A16
DVDD3I
A17
IOA18
IOA19
IOA20
DVSS18
IOA21
IOALE
IOOE#
IOWR#
IOCS#
WR#
RD#
DVDD3
INT0#
UP12
UP13
UP14
DVDD18
UP15
UP16
UP17
UP30
UP31
DVSS18
PRST#
UP34
UP35
FCICLK
FCICMD
FCIDAT
GPIO0
PWM0
PWM1
IR
RXD
TXD
DVSS3
ICE
SCL
SDA
SCL0
SDA0
SCL1
SDA1

C3
D3
C1
C2
L11
D1
D2
F2
D4
E1
E2
E3
E4
F1
F4
F3
G3
J3
G4
H3
K3
K4
J4
H4
L3
G2
G1
H2
H1
M12
J2
J1
K2
K1
L4
L2
L1
M2
M1
M11
N2
N1
P2
P1
M3
R2
R1
T2
T1
N12
N3
M4
N4
N11
T4
P3
R3
P4
U4
R4
U3
V4
T3
U1
U2
V1
V2
V3
W1
W2
AC9
W3
W4
Y1
Y2
Y3
P11
Y4
AA1
AA2
AA3
AA4
AB1
AB2
AB3
AB4
AC1
AC18
AC2
AC3
AC4
R11
AD1
AD2
AD3
AD4
AE1

AE2
AF1
AF2
AE3
AF3
AE4
AF4
AC5
T11
AD5
AE5
AF5
AC6
AD9
AD6
AE6
AF6
AC7
AD7
AD18
AE7
AF7
AC8
AD8
AF8
P12
AE9
AF9
AE10
AF10
AC11
AD11
AF12
AE15
AD15
AC19
AC15
AF16
AE16
R12
AD16
AC16
AF17
AD17
AD14
AE14
AF14
AF13
AE13
AD13
AC13
AE8
AC10
AC17
AE12
AD12
AE11
T12
AF11
AE17
AF15
AC12
AC14
AF18
AE18
AD10
AF19
AE19
AF20
AE20
AD19
AD20
AC20
AF21
AE21
AD21
P13
AC21
AD22
AC22
AF22
AE22
AF23
AE23
AD23
AC23
AF24
AE24
AD24
R13
AC24
AF25
AE25
AF26
AE26
AB23
AB24

VFEVDD1
ADCVDD4
SIF
AF
ADCVSS4
REFP4
REFN4
ADCVSS
ADIN4
ADIN3
ADIN2
ADIN1
ADIN0
ADCVDD
PWM2VREF
AUXVTOP
AUXVBOTTOM
VPLLVSS
VPLLVDD
DLLVDD
DLLVSS
BGVSS
REXTA
BGVDD
LVDDA
A7P
A7N
CLK2P
U?
CLK2N
LVSSA
A6P
A6N
A5P
A5N
LVDDB
A4P
A4N
A3P
A3N
LVSSB
CLK1P
CLK1N
A2P
A2N
LVDDC
A1P
A1N
A0P
A0N
LVSSC
DACVDDC
VREF
FS
DACVSSC
SVM
DACVDDB
DACVSSB
DACVDDA
G
DACVSSA
B
R
DE
VSY NCO
HSYNCO
VCLK
EBO7
EBO6
EBO5
EBO4
DVDD3I
EBO3
EBO2
EBO1
EBO0
EGO7
DVSS18
EGO6
EGO5
EGO4
EGO3
EGO2
EGO1
EGO0
ERO7
ERO6
ERO5
DVDD18
ERO4
ERO3
ERO2
DVSS3
ERO1
ERO0
OBO7
OBO6
OBO5
VFEVSS1
AVCM
ADCVDD0
CVBS2N
CVBS2P
CVBS1N
CVBS1P
CVBS0N
CVBS0P
ADCVSS0
REFP0
REFN0
ADCVDD1
SCN
SCP
SYN
SYP
ADCVSS1
REFP1
REFN1
VFEVDD0
VOCM
VFEVSS0
VICM
ADCVDD2
CRN
CRP
CBN
CBP
YN
YP
SOY
ADCVSS2
REFP2
REFN2
MON0
MON1
ADCVDD3
RN
RP
GN
GP
SOG
BN
BP
ADCVSS3
REFP3
REFN3
VSYNC
HSYNC
DVSS
DVDD
ADCPLLVSS1
ADCPLLVDD1
ADCPLLVDD
ADCPLLVSS
SYSPLLVSS
SYSPLLVDD
TESTP
TESTN
XTALVDD
XTALO
XTALI
XTALVSS
APLL_CAP
APLLVSS
APLLVDD
DMPLLVDD
DMPLLVSS
VI0
VI1
VI2
VI3
VI4
VI5
VI6
DVDD18
VI7
VI8
VI9
VI10
VI11
DVSS3
VI12
VI13
VI14
VI15
DVSS18
VI16
VI17
VI18
VI19
VI20
VI21
VI22
VI23
VCLK_DVI

L12
D5
C4
B1
A1
B2
A2
B3
A3
L13
B4
A4
C5
B5
A5
B6
A6
M13
D6
C6
D7
B7
N13
A7
C7
B8
A8
B9
A9
B10
A10
C8
D10
D9
C9
D11
C11
D8
B11
A11
B12
A12
D13
B13
A13
C10
D12
C12
C13
C14
N14
D14
L14
D15
C15
M14
L15
D16
B14
A14
C16
B15
A15
M15
A16
D18
D17
C17
C18
B16
A17
B17
A18
B18
C19
D19
E23
A19
B19
C20
D20
A20
L16
B20
C21
D21
A21
M16
B21
C22
D22
A22
B22
C23
D23
A23
B23

Pinout information

MT8205

DE_DVI
VSYNC_DVI
HSYNC_DVI
DVDD18
AOSDATA0
AOSDATA1
AOSDATA2
DVDD3I
AOSDATA3
LIN
AOBCK
AOLRCK
AOMCLK
DVSS3
DQ24
DQ25
DQ26
DVDD2
DQ27
DQ28
DVSS2
DQ29
DVDD2
DQ30
DQ31
DQS3
DQM1
DVSS18
DQS2
DQ23
DQ22
DVSS2
DQ21
DQ20
DVDD18
DQ19
DVDD2
DQ18
DQ17
DQ16
RA4
DVSS2
RA5
RA6
RA7
RA8
DVSS18
RA9
RA11
CKE
DVDD2
RCLK
RCLKB
DVSS2
RA3
RA2
RA1
RA0
RA10
BA1
DVDD2I
DVDD18
BA0
RCS#
RAS#
DVSS2
CAS#
RWE#
DQ8
DQ9
DQ10
DVDD2
DQ11
DVSS18
DQ12
DQ13
DVSS2
DQ14
DQ15
DQS1
AVSS18
AVDD18
RVREF
DVSS18
DQM0
DQS0
DQ7
DVDD2
DQ6
DQ5
DVSS2
DQ4
DQ3
DVDD2
DQ2
DQ1
DQ0

C24
D24
A24
Y24
A25
A26
B26
F23
B25
B24
C26
C25
E24
N15
G26
G25
F26
F24
F25
E26
N16
E25
G24
D26
D25
H25
H26
P14
J25
J26
K25
P16
K26
L25
AA24
L26
H24
M25
M26
N25
J23
R16
J24
K23
K24
L23
R14
L24
M23
N26
H23
P26
P25
P15
M24
N23
N24
R26
P24
P23
U23
AA23
R24
R23
T24
R15
T23
U24
W26
V25
V26
V23
U25
T13
U26
T25
T15
T26
R25
W25
W23
Y23
G23
T16
Y26
Y25
AA26
V24
AA25
AB26
T14
AB25
AC26
W24
AC25
AD26
AD25

BGA388/SOCKET
MT8205

Pin Descriptions
2.3 Pin Descriptions
Table 2-1 provides detail video/audio port pin descriptions.
Table 2-1 video/audio port pin descriptions.
Pin
E24
C25
C26
A25
A26
B26
B25
B24
A3
A2
A1
C1
C2

Symbol
AOMCLK
AOLRCK
AOBCK
AOSDATA0
AOSDATA1
AOSDATA2
AOSDATA3
LIN
CVBS0P
CVBS1P
CVBS2P
SIF
AF

Type

Description

Audio out master clock

Audio out left-right clock

Audio out bit clock

Audio out data line 0

Audio out data line 1

Audio out data line 2

Audio out data line 3

Audio line in

Composite Video input 0

Composite Video input 1

Composite Video input 2

Tuner Sound

SIF

Tuner Sound

AF

AT24C01A/02/04/08/16
Features

Low Voltage and Standard Voltage Operation

5.0 (VCC = 4.5V to 5.5V)
2.7 (VCC = 2.7V to 5.5V)
2.5 (VCC = 2.5V to 5.5V)
1.8 (VCC = 1.8V to 5.5V)
Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),
1024 x 8 (8K) or 2048 x 8 (16K)
2-Wire Serial Interface
Bidirectional Data Transfer Protocol
100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Compatibility
Write Protect Pin for Hardware Data Protection
8-Byte Page (1K, 2K), 16-Byte Page (4K, 8K, 16K) Write Modes
Partial Page Writes Are Allowed
Self-Timed Write Cycle (10 ms max)
High Reliability
Endurance: 1 Million Cycles
Data Retention: 100 Years
Automotive Grade and Extended Temperature Devices Available
8-Pin and 14-Pin JEDEC SOIC and 8-Pin PDIP Packages

2-Wire
Serial CMOS
E2PROM
1K (128 x 8)
2K (256 x 8)
4K (512 x 8)

Description
The AT24C01A/02/04/08/16 provides 1024/2048/4096/8192/16384 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as
128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low power and low voltage operation are
essential. The AT24C01A/02/04/08/16 is available in space saving 8-pin PDIP, 8-pin
and 14-pin SOIC packages and is accessed via a 2-wire serial interface. In addition,
the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V), 2.5V (2.5V to
5.5V) and 1.8V (1.8V to 5.5V) versions.

8K (1024 x 8)
16K (2048 x 8)

AT24C01A/2/4/8/16

Pin Configurations
Pin Name

Function

A0 to A2

Address Inputs

SDA

Serial Data

SCL

Serial Clock Input

WP

Write Protect

NC

No Connect

8-Pin PDIP

14-Pin SOIC
8-Pin SOIC

0180C

38/100
3275

Absolute Maximum Ratings*

*NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

Operating Temperature................... -55C to +125C

Storage Temperature...................... -65C to +150C
Voltage on Any Pin
with Respect to Ground ..................... -0.1V to +7.0V
Maximum Operating Voltage ........................... 6.25V
DC Output Current ......................................... 5.0 mA

Block Diagram

Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive
edge clock data into each E2PROM device and negative
edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be
wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1
and A0 pins are device address inputs that are hard wired
for the AT24C01A and the AT24C02. As many as eight
1K/2K devices may be addressed on a single bus system
(device addressing is discussed in detail under the Device
Addressing section).

The AT24C04 uses the A2 and A1 inputs for hard wire

addressing and a total of four 4K devices may be addressed on a single bus system. The A0 pin is a no connect.
The AT24C08 only uses the A2 input for hardwire addressing and a total of two 8K devices may be addressed
on a single bus system. The A0 and A1 pins are no connects.
The AT24C16 does not use the device address pins which
limits the number of devices on a single bus to one. The
A0, A1 and A2 pins are no connects.
(continued)

AT24C01A/02/04/08/16
39/100
3375

MX29LV160BT/BB

16M-BIT [2Mx8/1Mx16] CMOS SINGLE VOLTAGE

3V ONLY FLASH MEMORY
FEATURES
Extended single - supply voltage range 2.7V to 3.6V
2,097,152 x 8/1,048,576 x 16 switchable
Single power supply operation
- 3.0V only operation for read, erase and program
operation
Fully compatible with MX29LV160A device
Fast access time: 70/90ns
Low power consumption
- 30mA maximum active current
- 0.2uA typical standby current
Command register architecture
- Byte/word Programming (9us/11us typical)
- Sector Erase (Sector structure 16K-Bytex1,
8K-Bytex2, 32K-Bytex1, and 64K-Byte x31)
Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors with
Erase Suspend capability.
- Automatically program and verify data at specified
address
Erase Suspend/Erase Resume
- Suspends sector erase operation to read data from,
or program data to, any sector that is not being erased,
then resumes the erase.
Status Reply
- Data polling & Toggle bit for detection of program and

erase operation completion.

Ready/Busy pin (RY/BY)
- Provides a hardware method of detecting program or
erase operation completion.
Sector protection
- Hardware method to disable any combination of
sectors from program or erase operations
- Temporary sector unprotect allows code changes in
previously locked sectors.
CFI (Common Flash Interface) compliant
- Flash device parameters stored on the device and
provide the host system to access
100,000 minimum erase/program cycles
Latch-up protected to 100mA from -1V to VCC+1V
Boot Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
Low VCC write inhibit is equal to or less than 1.4V
Package type:
- 44-pin SOP
- 48-pin TSOP
- 48-ball CSP
Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
10 years data retention

GENERAL DESCRIPTION
The MX29LV160BT/BB is a 16-mega bit Flash memory
organized as 2M bytes of 8 bits or 1M words of 16 bits.
MXIC's Flash memories offer the most cost-effective
and reliable read/write non-volatile random access
memory. The MX29LV160BT/BB is packaged in 44-pin
SOP, 48-pin TSOP and 48-ball CSP. It is designed to be
reprogrammed and erased in system or in standard
EPROM programmers.
The standard MX29LV160BT/BB offers access time as
fast as 70ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX29LV160BT/BB has separate chip enable
(CE) and output enable (OE) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29LV160BT/BB uses a command register to manage this functionality. The command register allows for

100% TTL level control inputs and fixed power supply

levels during erase and programming, while maintaining
maximum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cycling. The MX29LV160BT/BB uses a 2.7V~3.6V VCC
supply to perform the High Reliability Erase and auto
Program/Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.

LP2996
DDR Termination Regulator
General Description

Features

The LP2996 linear regulator is designed to meet the JEDEC

SSTL-2 specifications for termination of DDR-SDRAM. The
device contains a high-speed operational amplifier to provide
excellent response to load transients. The output stage prevents shoot through while delivering 1.5A continuous current
and transient peaks up to 3A in the application as required
for DDR-SDRAM termination. The LP2996 also incorporates
a VSENSE pin to provide superior load regulation and a VREF
output as a reference for the chipset and DIMMs.

n
n
n
n
n
n
n
n

An additional feature found on the LP2996 is an active low

shutdown (SD) pin that provides Suspend To RAM (STR)
functionality. When SD is pulled low the VTT output will
tri-state providing a high impedance output, but, VREF will
remain active. A power savings advantage can be obtained
in this mode through lower quiescent current.

Source and sink current

Low output voltage offset
No external resistors required
Linear topology
Suspend to Ram (STR) functionality
Low external component count
Thermal Shutdown
Available in SO-8, PSOP-8 or LLP-16 packages

Applications
n DDR-I and DDR-II Termination Voltage
n SSTL-2 and SSTL-3 Termination
n HSTL Termination

Typical Application Circuit

20057518

LP2996 DDR Termination Regulator

November 2003







 


 
 


  

  

SCDS164A MAY 2004 REVISED MAY 2004

D Low Differential Gain and Phase

D
D
D

15

14

13

12

11

10

VCC
EN
S1D
S2D
DD
S1C
S2C
DC

RGY PACKAGE
(TOP VIEW)

S1A
S2A
DA
S1B
S2B
DB

VCC

16

16
15 EN
14 S2D

2
3

13 S2D
12 DD

4
5
6
7
8

11 S1C
10 S2C

DC

D
D
D

IN

IN
S1A
S2A
DA
S1B
S2B
DB
GND

GND

D
D
D

D, DBQ, OR PW PACKAGE
(TOP VIEW)

(DG = 0.64%, DP = 0.1 Degrees Typ)

Wide Bandwidth (BW = 300 MHz Min)
Low Crosstalk (XTALK = 63 dB Typ)
Low Power Consumption
(ICC = 3 A Max)
Bidirectional Data Flow, With Near-Zero
Propagation Delay
Low ON-State Resistance (ron = 3 Typ)
VCC Operating Range From 4.5 V to 5.5 V
Ioff Supports Partial-Power-Down Mode
Operation
Data and Control Inputs Provide
Undershoot Clamp Diode
Control Inputs Can Be Driven by TTL or
5-V/3.3-V CMOS Outputs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
2000-V Human-Body Model
(A114-B, Class II)
1000-V Charged-Device Model (C101)
Suitable for Both RGB and
Composite-Video Switching

description/ordering information
The TI TS5V330 video switch is a 4-bit 1-of-2 multiplexer/demultiplexer with a single switch-enable (EN) input.
When EN is low, the switch is enabled and the D port is connected to the S port. When EN is high, the switch
is disabled and the high-impedance state exists between the D and S ports. The select (IN) input controls the
data path of the multiplexer/demultiplexer.
ORDERING INFORMATION

QFN RGY
SOIC D
40C to 85C

ORDERABLE
PART NUMBER

PACKAGE

TA

SSOP (QSOP) DBQ

TSSOP PW

Tape and reel

TS5V330RGYR

Tube

TS5V330D

Tape and reel

TS5V330DR

Tape and reel

TS5V330DBQR

Tube

TS5V330PW

Tape and reel

TS5V330PWR

TOP-SIDE
MARKING
TE330
TS5V330
TE330
TE330

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated





  !"#   $"%&! '#(
'"! !  $#!! $# )# # 
#* "#
'' +,( '"! $!#- '#  #!#&, !&"'#
#-  && $##(

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

42/100
3675

19-0175; Rev 3; 5/96

15kV ESD-Protected, +5V RS-232 Transceivers

____________________________Features
ESD Protection for RS-232 I/O Pins:
15kVHuman Body Model
8kVIEC1000-4-2, Contact Discharge
15kVIEC1000-4-2, Air-Gap Discharge
Latchup Free (unlike bipolar equivalents)
Guaranteed 120kbps Data RateLapLink
Compatible
Guaranteed 3V/s Min Slew Rate
Operate from a Single +5V Power Supply

_________________Pin Configurations
TOP VIEW
C1+ 1

16 VCC

V+ 2

15 GND

C1- 3
C2+ 4
C2- 5

________________________Applications

14 T1OUT

MAX202E
MAX232E

12 R1OUT

V- 6

11 T1IN

T2OUT 7

10 T2IN
9

R2IN 8

Notebook, Subnotebook, and Palmtop Computers

Battery-Powered Equipment
Hand-Held Equipment

13 R1IN

R2OUT

DIP/SO
Pin Configurations and Typical Operating Circuits continued at
end of data sheet.

Ordering Information appears at end of data sheet.

_____________________________________________________________Selection Guide
PART

No. of RS-232
DRIVERS

No. of RS-232
RECEIVERS

RECEIVERS
ACTIVE IN
SHUTDOWN

No. of
EXTERNAL
CAPACITORS

LOW-POWER
SHUTDOWN

TTL THREESTATE

MAX202E

4 (0.1F)

No

No

MAX203E

None

No

No

MAX205E

None

Yes

Yes

MAX206E

4 (0.1F)

Yes

Yes

MAX207E

4 (0.1F)

No

No

MAX208E

4 (0.1F)

No

No

MAX211E

4 (0.1F)

Yes

Yes

MAX213E

4 (0.1F)

Yes

Yes

MAX232E

4 (1F)

No

No

MAX241E

4 (1F)

Yes

Yes

LapLink is a registered trademark of Traveling Software, Inc.

________________________________________________________________ Maxim Integrated Products

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800

MAX202EMAX213E, MAX232E/MAX241E

_______________General Description
The MAX202EMAX213E, MAX232E/MAX241E line
drivers/receivers are designed for RS-232 and V.28
communications in harsh environments. Each
transmitter output and receiver input is protected
against 15kV electrostatic discharge (ESD) shocks,
without latchup. The various combinations of features
are outlined in the Selection Guide. The drivers and
receivers for all ten devices meet all EIA/TIA-232E and
CCITT V.28 specifications at data rates up to 120kbps,
when loaded in accordance with the EIA/TIA-232E
specification.
The MAX211E/MAX213E/MAX241E are available in 28pin SO packages, as well as a 28-pin SSOP that uses
60% less board space. The MAX202E/MAX232E come
in 16-pin narrow SO, wide SO, and DIP packages. The
MAX203E comes in a 20-pin DIP/SO package, and
needs no external charge-pump capacitors. The
MAX205E comes in a 24-pin wide DIP package, and
also eliminates external charge-pump capacitors. The
MAX206E/MAX207E/MAX208E come in 24-pin SO,
SSOP, and narrow DIP packages. The MAX232E/
MAX241E operate with four 1F capacitors, while the
MAX202E/MAX206E/MAX207E/MAX208E/MAX211E/
MAX213E operate with four 0.1F capacitors, further
reducing cost and board space.

MAX202EMAX213E, MAX232E/MAX241E

15kV ESD-Protected, +5V RS-232 Transceivers

Table 3. DB9 Cable Connections
Commonly Used for EIA/TIAE-232E and
V.24 Asynchronous Interfaces
PIN

CONNECTION

Received Line Signal

Detector (sometimes
called Carrier Detect,
DCD)

Handshake from DCE

Receive Data (RD)

Data from DCE

Transmit Data (TD)

Data from DTE

Data Terminal Ready

Handshake from DTE

Signal Ground

Reference point for

signals

Data Set Ready (DSR)

Handshake from DCE

Request to Send (RTS)

Handshake from DTE

Clear to Send (CTS)

Handshake from DCE

Ring Indicator

Handshake from DCE

____________Pin Configurations and Typical Operating Circuits (continued)

+5V INPUT

TOP VIEW

0.1F*
6.3V

0.1F
16
1
0.1F*
6.3V

3
4

C1+ 1

16 VCC

V+ 2

15 GND

C1- 3
C2+ 4
C2- 5

0.1F*
16V

C1+

VCC

V+

+5V TO +10V
C1- VOLTAGE DOUBLER
C2+
+10V TO -10V
C2- VOLTAGE INVERTER

V-

+10V

-10V
0.1F*
16V

14 T1OUT

MAX202E
MAX232E

V- 6

11 T1IN
10 T2IN
9

T1IN

T1OUT 14

T1

TTL/CMOS
INPUTS

12 R1OUT

T2OUT 7
R2IN 8

11

13 R1IN

R2OUT

RS-232
OUTPUTS
10

T2IN

12

R1OUT

T2OUT

T2

DIP/SO

R1IN 13

R1

TTL/CMOS
OUTPUTS

5k
9

R2OUT

R2IN

R2
5k

PIN NUMBERS ON TYPICAL OPERATING CIRCUIT REFER TO DIP/SO PACKAGE, NOT LCC.
* 1.0F CAPACITORS, MAX232E ONLY.

GND
15

______________________________________________________________________________________

RS-232
INPUTS

Meet with mega satisfaction

SPECIFICATION FOR APPROVAL

Part No.
MLT166A
Description: LCD Power Supply Specification
Revision:
1.0
Customer.
Customer Approval No. :

Please return to us one original of SPECIFICATION FOR APPROVAL with your approved signatures.
APPROVED SIGNATURES

APPROVED BY

DATE

CHOP & SIGNATURES:

SHENZHEN MEGMEET ELECTRICAL TECHNOLOGY CO.,LTD

Add: 6F Tower 2, Zhongjian Industrial Building
18 Yanshan Road , Shekou, Shenzhen, P.R.China
ZIP CODE:518067
TEL: (0755)26693042 26693442
FAX: (0755)26693047
E-mail: YDP@megmeet.com

MEGMEET ELECTRICAL TECHNOLOGY CO., LTD.

DESCRIPTION:

SPECIFICATION
THESE SPECIFICATION ARE THE PROPERTY OF MEGMEET ELECTRICAL TECHNOLOGY CO., LTD
AND SHALL NOT BE REPRODUCED OR USED AS THE BASIS FOR THE MANUFACTURE OR SELL
OF APPARATUSES OR DEVICES WITHOUT PERMISSION.

DATE
11-15-2005

PREPARED
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Model No.:

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Document No.:

MLT166A-1.0

REV:
1.0

Spec.
Rev.

1.0

Sample
Rev.

1.0

Date

Description

15/11/2005

MEGMEET ELECTRICAL TECHNOLOGY CO., LTD.

Safety
by

Mechanical
by

Electrical
by

Zhangzhi

Gui

Gui

DESCRIPTION:

SPECIFICATION
THESE SPECIFICATION ARE THE PROPERTY OF MEGMEET ELECTRICAL TECHNOLOGY CO., LTD
AND SHALL NOT BE REPRODUCED OR USED AS THE BASIS FOR THE MANUFACTURE OR SELL
OF APPARATUSES OR DEVICES WITHOUT PERMISSION.

DATE
11-15-2005

PREPARED
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Model No.:

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Section
1. Power supply overview
1.1 Input Electrical Characteristics Overview
1.2 Output Electrical Characteristics Overview
1.2.1 Output Voltage ,Current & Regulation.
1.2.2 DC Output Ripple & Noise.
1.2.3 Output Transient Response.
1.2.4 DC Output Hold-Up Time.
1.2.4 DC Output Overshoot At Turn On & Turn Off.
1.2.6 DC output voltage rise time
1.3 Remote On/Off Control
1.4 Protection:
1.4.1 DC output Over Voltage Protection.
1.4.2 DC Output Over current Protection.
1.4.3 DC Output Short Circuit Protection.
1.4.4 Over Temperature Protection.
1.4.5 Reset After Shutdown.
2. Isolation
3.

Safety

4.

EMC
4.1 EMI
4.2 EMS
5. Environmental Requirement
5.1 Temperature
5.2 Humidity
5.3 Altitude
5.4 Cooling Method
5.5 Vibration
5.6 Impact
6. Dimension
7.

Weight

8.

Pin Connection

MEGMEET ELECTRICAL TECHNOLOGY CO., LTD.

DESCRIPTION:

SPECIFICATION
THESE SPECIFICATION ARE THE PROPERTY OF MEGMEET ELECTRICAL TECHNOLOGY CO., LTD
AND SHALL NOT BE REPRODUCED OR USED AS THE BASIS FOR THE MANUFACTURE OR SELL
OF APPARATUSES OR DEVICES WITHOUT PERMISSION.

DATE
11-15-2005

PREPARED
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Model No.:

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1. Power Supply Overview

1.1 Table 1

Input Electrical Characteristics Overview

Input voltage range

Normal voltage range
Frequency range
Max input ac current
Inrush current (cold start)
Efficiency(full load)
Harmonic current
Leakage Current
Standby Power Loss
Input Fuse

1.2

90Vac to 264Vac
100Vac to 240Vac
50Hz/60Hz5%
2.6Amax at full load condition
40Atyp peak, 120Vac; 60Atyp peak, 220Vac
80%min at 90Vac; 82%min at 220Vac
Meet GB17625.1-1998/IEC61000-3-2 class D
Less Than 0.75mA, 230Vac input
1W, 240Vac input
T5AH/250Vac

Output Electrical Characteristics Overview

1.2.1

Table 2

Output Voltage ,Current & Regulation.

Output Voltage

Regulation

+A24V
10%
+24V
5%
+12V
10%
+5.0V
5%
5. Vsb
5%
Note:* pulse width within 100ms

1.2.2

Table 3

Min. current

Rated current

Peak current

0.2A
0.2A
0.2A
0.1A
0.01A

1A
4A
2A
3A
0.5A

2A*
5A*
3A*
4A*
1A*

DC Output Ripple & Noise.

Output Voltage

+A24V
+24V
+12V
+5.0V

Ripple & Noise (Max.)

200mVp-p@25350mVp-p@-10
150mVp-p@25;250mVp-p@-10
100mVp-p@25; 150mVp-p@-10
50mVp-p@25; 100mVp-p@-10

50mVp-p@25; 100mVp-p@-10
5Vsb
Note: 1) Measurements shall be made with an oscilloscope with 20MHz bandwidth.

2) Outputs shall be bypassed at the connector with a 0.1uF ceramic capacitor and a
10uF electrolytic capacitor to simulate system loading.

MEGMEET ELECTRICAL TECHNOLOGY CO., LTD.

DESCRIPTION:

SPECIFICATION
THESE SPECIFICATION ARE THE PROPERTY OF MEGMEET ELECTRICAL TECHNOLOGY CO., LTD
AND SHALL NOT BE REPRODUCED OR USED AS THE BASIS FOR THE MANUFACTURE OR SELL
OF APPARATUSES OR DEVICES WITHOUT PERMISSION.

DATE
11-15-2005

PREPARED
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1.2.3 Output Transient Response.

Table 4. Test condition.
Voltage Tolerance Limit

Slew
Rate
24V5.0V5Vsb5%, A24V 0.2A/uS
12V10%
all outputs 10%
0.2A/uS

Load Change
Min. to 50% load and 50% to Max
load
Min. load to Max load

Note: Transient response measurements shall be made with a load changing repetition
rate of 50Hz to 10kHz.

1.2.4

Table 5

DC Output Hold-Up Time.

Output Voltage

120Vac input

220Vac input

+A24V+24V
+12V

10 mS
10 mS

10 mS
10 mS

+5.0V5Vsb

10 mS

10 mS

Note: All of dc output at full load.

1.2.5

Table 6

DC Output Overshoot At Turn On & Turn Off.

Output Channel

Output(V)

+24V
+A24V

+24V
+A24V

+ 12V

+ 12V

+5.0V

+5.0V

Over shoot voltage(V)

Turn on
5%
10%
10%
5%

Turn off
5%
10%
10%
5%

5Vsb
5Vsb
10%
Note: All of dc output current from Min. to Max.

1.2.6

Table 7

Output Voltage

10%

DC output voltage rise time

120Vac input &Full Load

220Vac input &Full Load

+24V
+A24V
+12V

30 mS
30 mS
20 mS

30mS
30 mS
20 mS

+5.0V

20 mS

20 mS

5Vsb

20 mS

20 mS

Note: The output voltages shall rise from10% to 90% of their output voltage.

MEGMEET ELECTRICAL TECHNOLOGY CO., LTD.

DESCRIPTION:

SPECIFICATION
THESE SPECIFICATION ARE THE PROPERTY OF MEGMEET ELECTRICAL TECHNOLOGY CO., LTD
AND SHALL NOT BE REPRODUCED OR USED AS THE BASIS FOR THE MANUFACTURE OR SELL
OF APPARATUSES OR DEVICES WITHOUT PERMISSION.

DATE
11-15-2005

PREPARED
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1.3 Remote On/Off Control

The power supply DC outputs (without +5.0Vsb) shall be enable with an active-high
TTL(2.5V/2.0mA)-compatible signal(Ps-on). The +5.0Vsb is on whenever the AC
power is present.
* When Ps-on is pulled to TTL high, the DC outputs are to be enabled.
* When Ps-on is pulled to TTL low or open circuit, the DC outputs are to be disabled.
Table 8.
Ps-on Signal

2.5V&2.0mA ( source)
1.0V
--

Ps-on- high
Ps-on- low
Ps-on-open

1.4

Outputs

Comments

Enable
X
X

Protection:

1.4.1 Table 9

DC output Over Voltage Protection.

Output Voltage

Max. Over Voltage

+24V
+5.0 V

30V
7.5Vtyp

Comments

Hiccup
Hiccup

Note: The power supply shall be test at max AC voltage (270Vac) and min load or no load.

1.4.2 Table 10

DC Output Over current Protection.

Output Voltage

Over Current

+24V
+A24V
+12V

5Atyp
2Atyp
3Atyp

Comments

Hiccup
Hiccup
Hiccup

+5.0V

4A

Hiccup

5Vsb

1A

Hiccup

1.4.3 Table 11

DC Output Short Circuit Protection.

Output Voltage

Comments

+24V/+A24V

Hiccup

+12V

Hiccup

MEGMEET ELECTRICAL TECHNOLOGY CO., LTD.

DESCRIPTION:

SPECIFICATION
THESE SPECIFICATION ARE THE PROPERTY OF MEGMEET ELECTRICAL TECHNOLOGY CO., LTD
AND SHALL NOT BE REPRODUCED OR USED AS THE BASIS FOR THE MANUFACTURE OR SELL
OF APPARATUSES OR DEVICES WITHOUT PERMISSION.

DATE
11-15-2005

PREPARED
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+5.0V

Hiccup

5VSB

Hiccup

Note:

1.4.4 Reset After Shutdown.

Recycle the ps-on signal, the power supply will restart after the fault removed.

2. Isolation
2.1

Table 12
Input To Output
Input To FG

DC500V 15Mmin (at room temperature)

DC500V 15Mmin (at room temperature)

Output To FG

Non Isolated

Note:

2.2

Table 13

Note:

Input To Output
Input To FG

3000Vac 50Hz 1minute 10mA

1500Vac 50Hz 1minute 10mA

Output To FG

Non Isolated

Open FG and Output return.

3. Safety
The power supply shall compliance with the following Criterion:
1) UL60950
2) EN60950
3) GB4943-1995/GB8898-2001

4.

EMC

4.1

EMI
The power supply shall compliance with the following Criterion:
1) Conduction Emission :
*EN55013, CLASS B
*GB13837-2003, CLASS B
*CISPR13:2001
2) Radiated Emission :
*EN55013, CLASS B
*GB13837-2003, CLASS B
*CISPR13:2001

MEGMEET ELECTRICAL TECHNOLOGY CO., LTD.

DESCRIPTION:

SPECIFICATION
THESE SPECIFICATION ARE THE PROPERTY OF MEGMEET ELECTRICAL TECHNOLOGY CO., LTD
AND SHALL NOT BE REPRODUCED OR USED AS THE BASIS FOR THE MANUFACTURE OR SELL
OF APPARATUSES OR DEVICES WITHOUT PERMISSION.

DATE
11-15-2005

PREPARED
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The power board should be assembled

the regulations

4.2

in customer product to test for passing

EMS

The power supply shall compliance with the following Criterion:

1) ESD
*GB17626.2-1998/IEC61000-4-2
2) EFT
*GB17626.4-1998/IEC61000-4-4
3) SURGE
*GB17626.5-1998/IEC61000-4-5
4 DIP
*GB17626.11-1998/IEC61000-4-11

5.

Lever 3
Lever 3
Lever 3
Class B/C

Environmental Requirement
5.1 Temperature
-10 to +50.
* Operating:
* Store:
-20 to +80.
5.2 Humidity
* Operating: From 10%to90% relative humidity (non-condensing).
* Store: From 5 to 95% relative humidity (non-condensing).
5.3 Altitude
* Operating: to10,000 ft.
* Store:
to 20,000ft.
5.4 Cooling Method
* Ventilation cooling .
5.5 Vibration
* 10-55Hz, 19.6m/s(2G), 3minutes period, 20minutes each along X, Y and Z axis.
5.6 Impact
* 49m/s(5G),11ms, once each X, Y and Z axis.

6. Dimension
* 200mm X 130mm X 26mm (L *W * H ).

7. Weight
* 550g

8. Pin Connection

MEGMEET ELECTRICAL TECHNOLOGY CO., LTD.

DESCRIPTION:

SPECIFICATION
THESE SPECIFICATION ARE THE PROPERTY OF MEGMEET ELECTRICAL TECHNOLOGY CO., LTD
AND SHALL NOT BE REPRODUCED OR USED AS THE BASIS FOR THE MANUFACTURE OR SELL
OF APPARATUSES OR DEVICES WITHOUT PERMISSION.

DATE
11-15-2005

PREPARED
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Table 15 CON1
NO.

VENTER:
Pin Connection

1.2.3

+12V

Function
+12VDC OUTPUT

4.5.6
GND
RETURN
7.8.9.10.11
+5.0V
+5.0VDC OUTPUT
Note: C0N1 -- JST VA CONNEETION, TYPE : pitch:2.0mm
Table 16 CON2
VENTER:
NO.
Pin Connection
Function
1

STB(PS-ON)

SMPS ON CONTROL(on-high)

2.3

GND

+5.0Vsb RETURN

4.5

+5.0Vsb

+5.0Vsb OUTPUT

Note: CON2 -- JST VA CONNEETION, TYPE : pitch:2.0mm

Table 17 CON3
VENTER:
NO.
Pin Connection
Function
5.6.7.8

+24VDC

+24DC OUTPUT

1.2.3.4

GND

+24VDC RETURN

Note: CON3 -- JST VA CONNEETION, TYPE : pitch:2.50mm

Table 17 CON4
VENTER:
NO.
Pin Connection
Function
3.4

+A24VDC

+A24DC OUTPUT

1.2

GND

+A24VDC RETURN

Note: CNO4 -- JST VA CONNEETION, TYPE : pitch:2.0mm

Table 18 CON0
VENTER:
NO.
Pin Connection
Function
1

AC-N

AC INPUT NATURE

2
NC
NC
3
AC-L
AC INPUT LINE
Note: CN3 -- JST VA CONNEETION, TYPE : pitch:3.96mm
Fig.8.1 Pin Connection (Top View)

MEGMEET ELECTRICAL TECHNOLOGY CO., LTD.

DESCRIPTION:

SPECIFICATION
THESE SPECIFICATION ARE THE PROPERTY OF MEGMEET ELECTRICAL TECHNOLOGY CO., LTD
AND SHALL NOT BE REPRODUCED OR USED AS THE BASIS FOR THE MANUFACTURE OR SELL
OF APPARATUSES OR DEVICES WITHOUT PERMISSION.

DATE
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PREPARED
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9. Power Supply Mounting

MEGMEET ELECTRICAL TECHNOLOGY CO., LTD.

DESCRIPTION:

SPECIFICATION
THESE SPECIFICATION ARE THE PROPERTY OF MEGMEET ELECTRICAL TECHNOLOGY CO., LTD
AND SHALL NOT BE REPRODUCED OR USED AS THE BASIS FOR THE MANUFACTURE OR SELL
OF APPARATUSES OR DEVICES WITHOUT PERMISSION.

DATE
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REV:
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Ver05

DL-06

SPECIFICATION

CUSTOMER

Slot-in DVD LOADER

DESCRIPTION

MODEL

DL-06 series(DL-06**)

2005.11.02

ISSUE DATE

CUSTOMER

Approved

Checked by
Sales Dept.

APPROVED

Checked by
Technical Dept.

Prepared

Ver05

DL-06

1.

Scope

1.1

This specification applies to Slot-in DVD mechanism for DVD player (thereafter called DVD
mechanism ). Foryou model : DL-06**.

1.2

Any query over the specification shall be expressed by R&D dept. of

Electronics Co.,Ltd.

1.3

For improving performance purpose, this specification is subject to change according to

pre-agreement established between us.

1.4

Hardware and software or manufacturing process may subject to change for improvements

Foryou Multimedia

within the rang of the specifications.

2.

Dimension of

2.1

See attachment for details of dimension of shell and installation.

3.

General specification

3.1

Mechanism

3.1.1

Disc loading:

3.1.2

Disc ejecting: Motorized ejection.

3.1.3

Play:

3.1.4

Skew adjusting: adjust two points on the base of spindle motor.

3.1.5

Pick-up feed mode: gear and rack drive.

3.1.6

Range of pick-up movement: 22.5mm ~ 59mm, from the center of

shell and

installation

Motorized loading.

Loading auto play

spindle motor.

Ver05

3.1.7

Anti vibration: two steps of dampers to reduce the vibration.

3.2

Power supply
DC12 1V600 mA&

3.3
3.3.1

DL-06

DC50.2V (660 mA) .

Pick-up
PVR-520TPVR-502WMITSUMIHOP-1200SWHITACHI
OPU-3153SANKYO
SF-HD62SANYOSF-HD65SANYO
PVR-520TPVR-502WMITSUMIHOP-1200SWHITACHI
OPU-3153SANKYOSF-HD62SANYOSF-HD65SANYOtwo laser diode and
single object lens pickup.

3.4

Motor

3.4.1

Spindle motor: DC brush motor: CCM03-030R1-26O ( (Moretech).

3.4.2

Sled motor WRF-300CA-09600.

3.4.3

Loading motor WFF-050SB-10200.

3.5

Detect switch

3.5.1

Pick-up inner position detecting SW: WI-A278DS3-A-0001

3.5.2

Disc chucking detecting SW: ESE22 (Type B)1pcs

3.5.3

Disc detecting SW: ESE22

3.6

Weight: approximate

4.

General performance

4.1

Disc specification
Diameter of disc1200.3800.3
Thickness of Disc1.2(+0.3,-0.1)
Type of disc

(Type B)2pcs (Panasonic).

476 g.

Ver05

DL-06

DVD Video;
CD-DA;
Video CD;
CD-R, CD-RW;
4.2

Prevention from the 2nd disc insertion: the second disc cant be loaded when there is a disc in
mechanism.

4.3

Noise Spec.

65 dBA

Noise level tests shall be carried out in an anechoic room with background noise 20 dBA or
less.Noise shall be measured at a position 10cm from the front of the mechanical section.

5.

Conditions of operation and storage

5.1

Operation temperature range: 0 ~ +45.

5.2

Range of storage: -20 ~ +60

5.3

Operation moisture range:

5.4

Storage moisture range:

5.5

Atmospheric pressure:

6.

Condition of performance evaluation

6.1

Installation: see attachment. Tightened on work table;

forth and
back: 10 ,
left and right: 10 .

6.2

Environment of evaluation
Temperature 252
Humidity 605RH

10% ~ 80% RH.

0% ~ 90% RH.

860mBar ~ 1060 mBar.

Installation angle:

Ver05

DL-06

If there is no problem about the environment of evaluation, may according to

the condition as below:
+15 ~ +30
Humidity: 45% ~ 75%RH
Noise: in an anechoic room with background noise 20dB (A) or less.
6.3

Test circuit and equipment

6.3.1

Refer FORYOUs standard circuit and equivalent.

7.

Reliability test

7.1

Environment test

Item

Specification

7.1.1
Test of high temperature
storage

After 24hours kept at +60, and then 16 hours at room temperature,

the mechanism shall be able to load/eject and playback within this
process.(Test disc:TCD-792 and TDV-520A)

7.1.2
Test of low temperature
storage

After 24hours kept at -20, and then 16 hours at room temperature,

the mechanism shall be able to load/eject and playback within this
process.(Test disc:TCD-792 and TDV-520A)

7.1.3
Test of high temperature
and high moisture storage

After 48hours kept at +40, 90%RH, and then 16 hours at room

temperature, the mechanism shall be able to load/eject and
playback within this process.(Test disc:TCD-792 and TDV-520A)

Ver05

DL-06

7.1.4
High and low temperature
cycling test

Applied -20(1H)60(1H)(temperature slope 80/H)

5cycles,then place at normal temperature for 16 hours, the mechanism
shall be able to load/eject and playback within this process.(Test
disc:TCD-792 and TDV-520A)

7.1.5
Test of high temperature
operation

DVD mechanism shall be kept in 45 for 4 hours, and then operate,

the mechanism shall be able to load/eject and playback within this
process.(Test disc:TCD-792 and TDV-520A)

7.1.6
Test of low temperature
operation

7.2

DVD mechanism shall be kept in 0 for 4 hours, and then operate,

the mechanism shall be able to load/eject and playback within this
process.(Test disc:TCD-792 and TDV-520A)

Life test
Item

Specification

7.2.1
Continue playback ability

When a mechanism is executed for continuous playing at room

temperature for 1,000H, the mechanism shall be able to playback
standard disc TDV-520A and TCD-792.

7.2.2
Feed motion
After conduct 200,000 times of pick-up feeding motion at room
temperature, mechanism shall be able to playback standard disc
TDV-520A and TCD-792. (One cycle: inner outer inner).
7.2.3
Loading and ejection
At normal room temperature, after 10,000 times of disc loading and
ejection circulation, mechanism shall be able to playback standard disc
TDV-520A and TCD-792. (One cycle :Disc in playback disc out)

7.3

Drop and impact

Item

test:
Specification

Ver05

DL-06

7.3.1
Shock test

(1 time ,6ms), 70G crash impact on each of 6 sides of mechanism. Mechanism

shall be able to playback standard disc TDV-520A and TCD-792.

7.3.2
Drop

test

After one time of drop test with surface, edge and corner (packing with 10sets
per carton), the mechanism shall be able to playback standard disc
TDV-520A and TCD-792.
Drop with surface: drop height 600mm, Drop sequence: bottom, front, left,
back, right. Each surface drop one time.
Drop with corner: drop height 450mm, Drop one of corners of carton bottom
one time.
Drop with edge: drop height 450mm, Each edge of drop corner (three edges)
drop one time.

7.4

Durability test of vibration

Item

Specification

7.4.1
Durability test
of vibration

Acceleration 2.5G, Frequency 10~50Hz, sweep time 5minutes, test time is

20minutes with each of 3 directions. After that test, mechanism shall be able
to playback standard disc TDV-520A and TCD-792.

7.5

The test environment is the same as item 6.2 except for special note.

8.

Ref appearance drawing

9.

Caution:

9.1

It is not allowed to disassembly and re-tune the mechanism without special training
because the mechanism is assembled and tuned using special method.

9.2

Storage: avoid storing the mechanism in high temperature, heavy wet and dusty place.

9.3

Handling: avoid extra force to the mechanism when handling.

Ver05

DL-06

9.4

Static-proof action should be taken when touch the mechanism since LD and OEIC can
be easily damaged by static.

9.5

Hand touch pickup is forbidden.

9.6

Must avoid laser beam shooting at eyes directly since the laser beam can hurt eyes.

10.

Attachment

10.1

Model Description in detail

10.2

Appearance drawing of

10.3

Mechanism schematic diagram of

10.4

customer Servo PCB of

10.5

Package specification of DL-06

10.6

Guide of Mechanism installation and cantions on assembly

10.7

installation screw

DL-06

DL-06set in PCB of customer

DL-06

Ver05

DL-06

10.1

Series
No.
1

Model
No.
DL-06L

Pick-Up

SPINDLE MOTOR

Loading motor

Sled motor

PVR-520T
(MITSUMI)

CCM03-030R1-26
O (Moretech)

WFF-050SB-102
00

WRF-300CA-09
600

DL-06LH

HOP-1200
(HITACHI)

Same as above

Same as above

Same as above

DL-06H

HOP-1200
(HITACHI)

Same as above

Same as above

Same as above

DL-06LS

SF-HD62(65)
(SANYO)

Same as above

Same as above

Same as above

DL-06LSM

SF-HD62 (65)
(SANYO)

Same as above

Same as above

Same as above

DL-06LW

PVR-502W
(MITSUMI)

Same as above

Same as above

Same as above

Issued Date: Jun. 15, 2005

Model No.: V270B1 - L01

Preliminary

TFT LCD Preliminary Specification

MODEL NO.: V270B1 - L01

LCD TV Head Division

AVP
QRA Dept.

Approval

DDIII
Approval

TVHD / PDD
DDII
Approval

DDI
Approval

LCD TV Marketing and Product Management Division

Product Manager

Version 1.0

Issued Date: Jun. 15, 2005

Model No.: V270B1 - L01

Preliminary
- CONTENTS REVISION HISTORY

-------------------------------------------------------

1. GENERAL DESCRIPTION

-------------------------------------------------------

2. ABSOLUTE MAXIMUM RATINGS

-------------------------------------------------------

------------------------------------------------------3.1 TFT LCD MODULE

3.2 BACKLIGHT INVERTER UNIT
3.2.1 CCFL(Cold Cathode Fluorescent Lamp) CHARACTERISTICS
3.2.2 INVERTER CHARACTERISTICS
3.2.3 INVERTER INTERTFACE CHARACTERISTICS

1.1 OVERVIEW
1.2 FEATURES
1.3 APPLICATION
1.4 GENERAL SPECIFICATIONS
1.5 MECHANICAL SPECIFICATIONS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
2.2 ELECTRICAL ABSOLUTE RATINGS
2.2.1 TFT LCD MODULE
2.2.2 BACKLIGHT UNIT

3. ELECTRICAL CHARACTERISTICS

4. BLOCK DIAGRAM

-------------------------------------------------------

12

5. INTERFACE PIN CONNECTION

-------------------------------------------------------

13

6. INTERFACE TIMING

-------------------------------------------------------

19

7. OPTICAL CHARACTERISTICS

-------------------------------------------------------

22

8. DEFINITION OF LABELS

-------------------------------------------------------

26

9. PACKAGING

-------------------------------------------------------

27

10. PRECAUTIONS

-------------------------------------------------------

29

11. MECHANICAL CHARACTERISTICS

-------------------------------------------------------

30

4.1 TFT LCD MODULE

5.1 TFT LCD MODULE

5.2 BACKLIGHT UNIT
5.3 INVERTER UNIT
5.4 BLOCK DIAGRAM OF INTERFACE
5.5 LVDS INTERFACE
5.6 COLOR DATA INPUT ASSIGNMENT
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
6.2 POWER ON/OFF SEQUENCE
7.1 TEST CONDITIONS
7.2 OPTICAL SPECIFICATIONS

8.1 CMO MODULE LABEL

9.1 PACKING SPECIFICATIONS

9.2 PACKING METHOD
10.1 ASSEMBLY AND HANDLING PRECAUTIONS
10.2 SAFETY PRECAUTIONS

Version 1.0

Issued Date: Jun. 15, 2005

Model No.: V270B1 - L01

Preliminary
REVISION HISTORY
Version

Date

Ver 1.0

Jun. 15,05

Page
(New)
All

Section
All

Description
Preliminary Specification was first issued.

Version 1.0

Issued Date: Jun. 15, 2005

Model No.: V270B1 - L01

Preliminary
1. GENERAL DESCRIPTION
1.1 OVERVIEW
V270B1- L01 is a TFT Liquid Crystal Display module with 14-CCFL Backlight unit and 1ch-LVDS
interface. The display diagonal is 27. This module supports 1366 x 768 WXGA format and can display true
16.7M colors(8-bits colors). The inverter module for backlight is built-in.

1.2 FEATURES
- Excellent brightness (550 nits)
- Ultra high contrast ratio (1000:1)
- Fast response time (8ms)
- High color saturation NTSC 75%
- WXGA (1366 x 768 pixels) resolution
- DE (Data Enable) only mode
- LVDS (Low Voltage Differential Signaling) interface
- Optimized response time for both 50/60 Hz frame rate
- Ultra wide viewing angle: 176(H)/176(V) (CR>20) Super MVA technology
- 180 degree rotation display option
- Low color shift function option
- Color reproduction (Nature color)

1.3 APPLICATION
- TFT LCD TVs
-

High brightness, multi-media displays

1.4 GENERAL SPECIFICATI0NS

Item
Active Area
Bezel Opening Area
Driver Element
Pixel Number
Pixel Pitch (Sub Pixel)
Pixel Arrangement
Display Colors
Display Operation Mode
Surface Treatment

Specification
596.259 (H) x 335.232 (V) (27 diagonal)
603.22 (H) x 341.98 (V)
a-si TFT active matrix
1366 x R.G.B. x 768
0.1460 (H) x 0.4365 (V)
RGB vertical stripe
16.7M
Transmissive mode / Normally black
Hardness : 3H, Haze : 40%
Anti-reflective coating < 2% reflection

Unit
mm
mm
pixel
mm
color
-

Note
(1)

1.5 MECHANICAL SPECIFICATIONS

Item
Horizontal(H)
Vertical(V)
Module Size
Depth(D)
Depth(D)
Weight

Min.
636.85
379.1
33.9
39.2
3700

Typ.
637.55
379.8
35.4
40.7
4000

Max.
638.25
380.5
36.9
42.2
4300

Unit
mm
mm
mm
mm
g

Note
To PCB cover
To inverter cover

Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.

Version 1.0

Issued Date: Jun. 15, 2005

Model No.: V270B1 - L01

Preliminary
2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item

Symbol

Storage Temperature
Operating Ambient Temperature
Shock (Non-Operating)
Vibration (Non-Operating)

Min.
-20
0
-

TST
TOP
SNOP
VNOP

Value

Max.
+60
+50
50
1.0

Unit

Note

C
C
G
G

(1)
(1), (2)
(3), (5)
(4), (5)

Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta 40 C).
(b) Wet-bulb temperature should be 39 C Max. (Ta > 40 C).
(c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
display area is less than or equal to 60 C with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 60 C. The range of operating temperature may degrade in case of improper
thermal management in final product design.
Note (3) 11 ms, half sine wave, 1 time for X, Y, Z.
Note (4) 10 ~ 500 Hz, 10 min, 1 time each X, Y, Z.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough
so that the module would not be twisted or bent by the fixture.

Relative Humidity (%RH)

100
90
80

60

Operating Range

40

20

Storage Range

10
-40

-20

20

40

60

80

Temperature (C)

Version 1.0

Issued Date: Jun. 15, 2005

Model No.: V270B1 - L01

Preliminary
2.2 ELECTRICAL ABSOLUTE RATINGS
2.2.1 TFT LCD MODULE
Item
Power Supply Voltage
Input Signal Voltage

Symbol

Min.
-0.3
-0.3

Vcc
VIN

Value

Max.
6.0
3.6

Unit

Note

V
V

(1)

2.2.2 BACKLIGHT UNIT

Item

Symbol

Lamp Voltage
Power Supply Voltage
Control Signal Level

VW
VBL

Test
Min.
Condition
Ta = 25

-0.3

Type

Max.

Unit

Note

3000
30
7

VRMS
V
V

(1)
(1), (3)

Note (1) Permanent damage to the device may occur if maximum values are exceeded. Functional
operation should be restricted to the conditions described under normal operating conditions.
Note (2) No moisture condensation or freezing.
Note (3) The control signals includes Backlight On/Off Control, Internal PWM Control, External PWM
Control and Internal/External PWM Selection.

Version 1.0

Issued Date: Jun. 15, 2005

Model No.: V270B1 - L01

Preliminary
3. ELECTRICAL CHARACTERISTICS
Ta = 25 2 C

3.1 TFT LCD MODULE

Parameter

Min.
4.5
-

Value
Typ.
5.0
1.8
1.2
1.65

Max.
5.5
150
3.0
-

VLVTH

+100

mV

VLVTL

-100

mV

VLVC
RT
VIH
VIL

1.125

1.25
100
-

1.375

V
ohm
V
V

Symbol

Power Supply Voltage

Power Supply Ripple Voltage
Rush Current
White
Power Supply Current Black
Vertical Stripe
Differential Input High
Threshold Voltage
LVDS
Differential Input Low
Interface
Threshold Voltage
Common Input Voltage
Terminating Resistor
CMOS
Input High Threshold Voltage
interface Input Low Threshold Voltage

VCC
VRP
IRUSH
ICC

2.7
0

3.3
0.7

Unit

Note

V
mV
A
A
A
A

(1)
(2)
(3)

Note (1) The module should be always operated within above ranges.
Note (2) Measurement Conditions:
+5.0V
Q1

2SK1475
Vcc
FUSE

C3

(LCD Module Input)

1uF

R1
47K

(High to Low)
(Control Signal)

Q2

R2

2SK1470

SW
1K
+12V

VR1

47K

C1

C2

0.01uF

1uF

Vcc rising time is 470us

+5V
0.9Vcc
0.1Vcc

GND

470us

Version 1.0

Issued Date: Jun. 15, 2005

Model No.: V270B1 - L01

Preliminary
Note (3) The specified power supply current is under the conditions at Vcc = 5 V, Ta = 25 2 C, fv = 60 Hz,
whereas a power dissipation check pattern below is displayed.
b. Black Pattern

a. White Pattern

Active Area

Active Area

c. Vertical Stripe Pattern

R G B R G B
B R G B R G B R
B R G B R G B R
R G B R G B
Active Area

3.2 BACKLIGHT INVERTER UNIT

3.2.1 CCFL (Cold Cathode Fluorescent Lamp) CHARACTERISTICS (Ta = 25 2 C)
Min.

Value
Typ.

Max.

VW

1120

Lamp Current

IL

4.2

Lamp Starting Voltage

VS

Operating Frequency

FO

Lamp Life Time

LBL

Parameter

Symbol

Lamp Voltage

Unit

Note

VRMS

IL = 4.7mA

4.7

5.2

mARMS

(1)

1650

VRMS

(2), Ta = 0 C

1500

VRMS

(2), Ta = 25 C

50
50,000

60,000

70

KHz

(3)

Hrs

(4)

Version 1.0

Issued Date: Jun. 15, 2005

Model No.: V270B1 - L01

Preliminary
3.2.2 INVERTER CHARACTERISTICS (Ta = 25 2 C)

VBL

Min.
22.8

Value
Typ.
92
24

Max.
25.2

Power Supply Current

IBL

3.8

Non Dimming

Input Ripple Noise

500

mVP-P

VBL =22.8V

1790

VRMS

Ta = 0 C

1200

VRMS

Ta = 25 C

Parameter

Symbol

Power Consumption

PBL

Power Supply Voltage

Backlight Turn on
Voltage

VBS

Unit

Note

(5), IL = 4.7mA

VDC

Oscillating Frequency

FW

53

56

59

kHz

Dimming Frequency

FB

150

160

170

Hz

Minimum Duty Ratio

DMIN

10

Note (1) Lamp current is measured by utilizing high frequency current meters as shown below:

A
A
A
A
A
A
A
A
A
A
A
A
A
A

LCD
Module

HV (Pink)
HV (White)

1
2

HV (Pink)
HV (White)

1
2

HV (Pink)
HV (White)

1
2

HV (Pink)
HV (White)

1
2

HV (Pink)
HV (White)

1
2

HV (Pink)
HV (White)

1
2

HV (Pink)
HV (White)

1
2

Inverter

LV (Gray)

Note (2) The lamp starting voltage VS should be applied to the lamp for more than 1 second under starting
up duration. Otherwise the lamp could not be lighted on completed.
Note (3) The lamp frequency may produce interference with horizontal synchronous frequency from the
display, and this may cause line flow on the display. In order to avoid interference, the lamp
frequency should be detached from the horizontal synchronous frequency and its harmonics as far
as possible.

Version 1.0

Issued Date: Jun. 15, 2005

Model No.: V270B1 - L01

Preliminary
Note (4) The life time of a lamp is defined as when the brightness is larger than 50% of its original value
and the effective discharge length is longer than 80% of its original length (Effective discharge
length is defined as an area that has equal to or more than 70% brightness compared to the
brightness at the center point.) as the time in which it continues to operate under the condition Ta
= 25 2 and IL = 4.2 ~ 5.2 mARMS.
Note (5) The power supply capacity should be higher than the total inverter power consumption PBL. Since
the pulse width modulation (PWM) mode was applied for backlight dimming, the driving current
changed as PWM duty on and off. The transient response of power supply should be considered
for the changing loading when inverter dimming.

3.2.3 INVERTER INTERTFACE CHARACTERISTICS

Item

Symbol
ON

On/Off Control
Voltage

OFF
HI

Internal/External
PWM Select Voltage

LO

Internal PWM
Control Voltage

MAX

External PWM
Control Voltage

HI

VBLON
VSEL

Test

Min.

Typ.

Max.

Unit

2.0

5.0

0.8

2.0

5.0

0.8

3.0

minimum duty ratio

maximum duty ratio

2.0

5.0

duty on

0.8

duty off

Condition

VIPWM

VSEL = L

VEPWM

VSEL = H

Control Signal Rising Time

Tr

100

ms

Control Signal Falling Time

Tf

100

ms

PWM Signal Rising Time

TPWMR

50

us

PWM Signal Falling Time

TPWMF

50

us

Input impedance

RIN

BLON Delay Time

Ton

ms

BLON Off Time

Toff

ms

MIN
LO

Note

Note (1) The SEL signal should be valid before backlight turns on by BLON signal. It is inhibited to change
the internal/external PWM selection (SEL) during backlight turn on period.

Version 1.0

Issued Date: Jun. 15, 2005

Model No.: V270B1 - L01

Preliminary
Note (2) The power sequence and control signal timing are shown as the following figure.

VBL

VBLON
0

2.0V
0.8V
Tr

VSEL
0

VEPWM
0

Toff

Ton

2.0V
0.8V

2.0V
0.8V

Backlight on duration

Tf
Int. Dimming Function

Ext. Dimming Function

TPWMR

TPWMF

3.0V
VIPWM
0

VW
External
PWM
Period

External
PWM Duty
Minimun
Duty

100%

Version 1.0

Issued Date: Jun. 15, 2005

Model No.: V270B1 - L01

Preliminary
4. BLOCK DIAGRAM
4.1 TFT LCD MODULE

RX3(+/-)
RXCLK(+/-)

Vcc
GND

INPUT CONNECTOR

RX2(+/-)

(JAE,FI-X30SSL-HF)

RX1(+/-)

TIMING
CONTROLLER

SCAN DRIVER IC

FRAME BUFFER

RX0(+/-)

TFT LCD PANEL

(1366x3x768)

DATA DRIVER IC
DC/DC CONVERTER &
REFERENCE VOLTAGE

CN1
VBL
GND
CN2
VBL
GND
SEL
E_PWM
I_PWM
BLON

CN3-CN9:SM02 (8.0)B-BHS-1-TB(LF)(JST)

INVERTER CONNECTOR
CN1:S10B-PH-SM3-TB(D)(LF)(JST)
CN2: S12B-PH-SM3-TB(D)(LF)(JST)

BACKLIGHT
UNIT

CN10: S2B-ZR-SM3A-TF (D)(LF)(JST)

Version 1.0

Issued Date: Jun. 15, 2005

Model No.: V270B1 - L01

Preliminary
5. INTERFACE PIN CONNECTION
5.1 TFT LCD MODULE
CNF1 Connector Pin Assignment
Pin No.
Symbol
Description
1
GND
Ground
2
RPF
Display Rotation
3
SELLVDS
Select LVDS data format
4
NC
No Connection
5
NC
No Connection
6
ODSEL
Overdrive Lookup Table Selection
7
EN LCS
Low Color Shift
8
GND
Ground
9
RX0Negative transmission data of pixel 0
10
RX0+
Positive transmission data of pixel 0
11
RX1Negative transmission data of pixel 1
12
RX1+
Positive transmission data of pixel 1
13
RX2Negative transmission data of pixel 2
14
RX2+
Positive transmission data of pixel 2
15
RXCLKNegative of clock
16
RXCLK+
Positive of clock
17
RX3Negative transmission data of pixel 3
18
RX3+
Positive transmission data of pixel 3
19
GND
Ground
20
GND
Ground
21
GND
Ground
22
GND
Ground
23
GND
Ground
24
GND
Ground
25
GND
Ground
26
VCC
Power supply: +5V
27
VCC
Power supply: +5V
28
VCC
Power supply: +5V
29
VCC
Power supply: +5V
30
VCC
Power supply: +5V
Note (1) Connector Part No.: FI-X30SSL-HF(JAE) or compatible

Note
(3)
(5)
(2)
(4)
(6)

Note (2) Reserved for internal use. Left it open.

Note (3) Low : normal display (default), High : display with 180 degree rotation
Note (4) Overdrive lookup table selection. The Overdrive lookup table should be selected in accordance to the
frame rate to optimize image quality.
ODSEL
Note
L
Lookup table was optimized for 60 Hz frame rate.
H
Lookup table was optimized for 50 Hz frame rate.
Note (5) Please refer to 5.5 LVDS INTERFACE (Page 17)
Note (6) Enable Low color shift function.
EN LCS
L
H

Note

Low color shift off

Low color shift on

Version 1.0

Issued Date: Jun. 15, 2005

Model No.: V270B1 - L01

Preliminary
5.2 BACKLIGHT UNIT
The pin configuration for the housing and leader wire is shown in the table below.
CN3-CN9 (Housing): BHR-03VS-1 (JST)

Pin No.
1
2

Symbol

Description

HV
HV

High Voltage
High Voltage

Wire Color
Pink
White

Note (1) The backlight interface housing for high voltage side is a model BHR-03VS-1, manufactured by JST.
The mating header on inverter part number is SM02(8.0)B-BHS-1-TB(LF) or equivalent.

Pin No.
1
2

CN10 (Housing): ZHR-2 (JST) or equivalent

Symbol
Description
LV
NC

Low Voltage (+)

No Connection

Wire Color
Gray
-

Note (2) The backlight interface housing and return cable for low voltage side is a model ZHR-2 , manufactured
by JST or equivalent. The mating header on inverter part number is S2B-ZR-SM3A-TF(D)(LF) or
equivalent.

Version 1.0

Issued Date: Jun. 15, 2005

Model No.: V270B1 - L01

Preliminary
5.3 INVERTER UNIT
CN1(Header):S10B-PH-SM3-TB(D)(LF)(JST) or equivalent.
Pin
Name
Description
1
2
VBL
+24V Power input
3
4
5
6
7
GND
Ground
8
9
10
CN2(Header): S12B-PH-SM3-TB(D)(LF)(JST) or equivalent.
Pin
1
2
3
4
5
6
7
8

Name

Description

VBL

+24V Power input

GND

Ground

SEL

Internal/external PWM selection

High : external dimming
Low : internal dimming

10

E_PWM

11

I_PWM

12

BLON

External PWM control signal

E_PWM should be connected to low when internal
PWM was selected (SEL = low).
Internal PWM control signal
I_PWM should be connected to ground when
external PWM was selected (SEL = high).
Backlight on/off control

CN3-CN9(Header): SM02(8.0)B-BHS-1-TB(LF)(JST) or equivalent

Pin

Name

Description

CCFL HOT CCFL high voltage

CCFL HOT CCFL high voltage

CN10(Header): S2B-ZR-SM3A-TF(D)(LF)(JST) or equivalent

Pin
1
2

Name

Description

CCFL COLD CCFL low voltage

NC

Note (1) Floating of any control signal is not allowed.

Version 1.0

Issued Date: Jun. 15, 2005

Model No.: V270B1 - L01

Preliminary
5.4 BLOCK DIAGRAM OF INTERFACE
CNF1

Rx0+
R0-R7

Rx0-

TxIN

Rx1+

G0-G7

Rx1-

B0-B7

Rx2+

DE

Rx2Rx3+
Rx3-

Host
Graphics

PLL

Controller

CLK+
CLK-

51

RxOUT

100pF

51

R0-R7
G0-G7

51
100pF

51

B0-B7

51
100pF

DE

51
51
100pF

51
51
100pF

51

PLL

LVDS Transmitter

LVDS Receiver

THC63LVDM83A

THC63LVDF84A

DCLK
Timing
Controller

(LVDF83A)
R0~R7

: Pixel R Data ,

G0~G7

: Pixel G Data ,

B0~B7

: Pixel B Data

DE

: Data enable signal

Note (1) The system must have the transmitter to drive the module.
Note (2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it is
used differentially.

Version 1.0

Issued Date: Jun. 15, 2005

Model No.: V270B1 - L01

Preliminary
5.5 LVDS INTERFACE

SIGNAL

TRANSMITTER

INTERFACE

RECEIVER

TFT CONTROL

THC63LVDM83A

CONNECTOR

THC63LVDF84A

INPUT

SELLVDS SELLVDS

PIN

INPUT

Host

TFT-LCD

PIN

OUTPUT

=L

=H

R0

R2

51

TxIN0

27

R1

R3

52

TxIN1

R2

R4

54

TxIN2

R3

R5

55

R4

R6

R5

SELLVDS SELLVDS
=L

=H

Rx OUT0

R0

R2

29

Rx OUT1

R1

R3

30

Rx OUT2

R2

R4

TxIN3

32

Rx OUT3

R3

R5

56

TxIN4

33

Rx OUT4

R4

R6

R7

TxIN6

35

Rx OUT6

R5

R7

G0

G2

TxIN7

37

Rx OUT7

G0

G2

G1

G3

TxIN8

38

Rx OUT8

G1

G3

G2

G4

TxIN9

39

Rx OUT9

G2

G4

G3

G5

11

TxIN12

43

Rx OUT12

G3

G5

G4

G6

12

TxIN13

45

Rx OUT13

G4

G6

G5

G7

14

TxIN14

46

Rx OUT14

G5

G7

B0

B2

15

TxIN15

47

Rx OUT15

B0

B2

B1

B3

19

TxIN18

51

Rx OUT18

B1

B3

24

B2

B4

20

TxIN19

53

Rx OUT19

B2

B4

bit

B3

B5

22

TxIN20

54

Rx OUT20

B3

B5

B4

B6

23

TxIN21

55

Rx OUT21

B4

B6

B5

B7

24

TxIN22

Rx OUT22

B5

B7

DE

DE

30

TxIN26

Rx OUT26

DE

DE

R6

R0

50

TxIN27

Rx OUT27

R6

R0

R7

R1

TxIN5

34

Rx OUT5

R7

R1

G6

G0

TxIN10

41

Rx OUT10

G6

G0

G7

G1

10

TxIN11

42

Rx OUT11

G7

G1

B6

B0

16

TxIN16

49

Rx OUT16

B6

B0

B7

B1

18

TxIN17

50

Rx OUT17

B7

B1

RSVD 1

RSVD 1

25

TxIN23

Rx OUT23

NC

NC

RSVD 2

RSVD 2

27

TxIN24

Rx OUT24

NC

NC

RSVD 3

RSVD 3

28

TxIN25

Rx OUT25

NC

NC

DCLK

31

26

RxCLK OUT

TA OUT0+

TA OUT0-

TA OUT1+

TA OUT1-

TA OUT2+

TA OUT2-

TA OUT3+

TA OUT3-

Rx 0+

Rx 0-

Rx 1+

Rx 1-

Rx 2+

Rx 2-

Rx 3+

Rx 3-

TxCLK IN TxCLK OUT+ RxCLK IN+

DCLK

TxCLK OUT- RxCLK INR0~R7: Pixel R Data (7; MSB, 0; LSB)

G0~G7: Pixel G Data (7; MSB, 0; LSB)
B0~B7: Pixel B Data (7; MSB, 0; LSB)
DE: Data enable signal
Notes(1) RSVD(reserved)pins on the transmitter shall be H or L.

Version 1.0

Issued Date: Jun. 15, 2005

Model No.: V270B1 - L01

Preliminary
5.6 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 8-bit gray scale data input for
the color. The higher the binary input, the brighter the color. The table below provides the assignment of
color versus data input.
Data Signal
Color

Red

Green

Blue

R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0

Black

0 0 0 0 0

0 0

0 0 0

Red

1 0 0 0 0

0 0

0 0 0

Green

0 1 1 1 1

0 0

0 0 0

Basic Blue

0 0 0 0 0

1 1

1 1 1

Colors Cyan

0 1 1 1 1

1 1

1 1 1

Magenta

1 0 0 0 0

1 1

1 1 1

Yellow

1 1 1 1 1

0 0

0 0 0

White

1 1 1 1 1

1 1

1 1 1

Red(0) / Dark

0 0 0 0 0

0 0

0 0 0

Red(1)

1 0 0 0 0

0 0

0 0 0

Red(2)

0 0 0 0 0

0 0

0 0 0

Red(253)

1 0 0 0 0

0 0

0 0 0

Red(254)

0 0 0 0 0

0 0

0 0 0

Red(255)

1 0 0 0 0

0 0

0 0 0

Green(0) / Dark 0

0 0 0 0 0

0 0

0 0 0

Green(1)

0 0 0 0 0

0 0

0 0 0

Green(2)

0 0 0 0 0

0 0

0 0 0

Green(253)

0 1 1 1 1

0 0

0 0 0

Green(254)

0 1 1 1 1

0 0

0 0 0

Green(255)

0 1 1 1 1

0 0

0 0 0

Blue(0) / Dark

0 0 0 0 0

0 0

0 0 0

Blue(1)

0 0 0 0 0

0 0

0 0 1

Blue(2)

0 0 0 0 0

0 0

0 1 0

Blue(253)

0 0 0 0 0

1 1

1 0 1

Blue(254)

0 0 0 0 0

1 1

1 1 0

Blue(255)

0 0 0 0 0

1 1

1 1 1

Gray
Scale
Of
Red

Gray
Scale
Of
Green

Gray
Scale
Of
Blue

Note (1) 0: Low Level Voltage, 1: High Level Voltage

Version 1.0

Issued Date: Jun. 15, 2005

Model No.: V270B1 - L01

Preliminary
6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram.
Signal

Item
Frequency
Input cycle to

LVDS Receiver Clock

Symbol
1/Tc

Min.
60

Typ.
86

Max.
88

Unit
MHZ

Trcl

200

ps

cycle jitter

Note

Setup Time
Hold Time

Tlvsu
600
ps
Tlvhd
600
ps
Fr5
47
50
53
Hz
(2)
Frame Rate
57
60
63
Hz
Fr6
Vertical Active Display Term
Total
Tv
770
795
888
Th
Tv=Tvd+Tvb
Display
Tvd
768
768
768
Th
Blank
Tvb
2
27
120
Th
Total
Th
1436
1798
1936
Tc
Th=Thd+Thb
Horizontal Active Display Term Display
Thd
1366
1366
1366
Tc
Blank
Thb
70
432
570
Tc
Note (1) Since this module is operated in DE only mode, Hsync and Vsync input signals should be set to
LVDS Receiver Data

low logic level. Otherwise, this module would operate abnormally.

(2) Please refer to 5.1 for detail information.

INPUT SIGNAL TIMING DIAGRAM

Tv
Tvd

Tvb

DE
Th

DCLK
Tc
DE

Thd

Thb

DATA

Valid display data (1366 clocks)

Version 1.0

Issued Date: Jun. 15, 2005

Model No.: V270B1 - L01

Preliminary
LVDS RECEIVER INTERFACE TIMING DIAGRAM
Tc

RXCLK+/RXn+/Tlvsu
Tlvhd

1T
14

3T
14

5T
14

7T
14

9T
14

11T
14

13T
14

Version 1.0

Issued Date: Jun. 15, 2005

Model No.: V270B1 - L01

Preliminary
6.2 POWER ON/OFF SEQUENCE
To prevent a latch-up or DC operation of LCD module, the power on/off sequence should be as the
diagram below.

Power Supply

0.9 VCC

VCC
0V

0.9 VCC
0.1Vcc

0.1VCC

T1

0T110ms

T3

0T250ms
0T350ms
500ms T4

T2

T4

VALID

Signals
0V

Power Off

Power On

50%

Backlight (Recommended)
500msT5
100msT6

50%

T5

T6

Power ON/OFF Sequence

Note (1) The supply voltage of the external system for the module input should follow the definition of Vcc.
Note (2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the LCD
operation or the LCD turns off before the backlight turns off, the display may momentarily become
abnormal screen.
Note (3) In case of Vcc is in off level, please keep the level of input signals on the low or high impedance.
Note (4) T4 should be measured after the module has been fully discharged between power off and on period.
Note (5) Interface signal shall not be kept at high impedance when the power is on.

Version 1.0

Issued Date: Jun. 15, 2005

Model No.: V270B1 - L01

Preliminary
7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
Item
Ambient Temperature
Ambient Humidity
Supply Voltage
Input Signal
Lamp Current
Oscillating Frequency (Inverter)

Symbol
Value
Unit
o
Ta
C
252
Ha
%RH
5010
VCC
5.0
V
According to typical value in "3. ELECTRICAL CHARACTERISTICS"
IL
mA
4.7 0.5
FW
KHz
56 3

7.2 OPTICAL SPECIFICATIONS

The relative measurement methods of optical characteristics are shown in 7.2. The following items should
be measured under the test conditions described in 7.1 and stable environment shown in Note (6).
Item
Contrast Ratio
Response Time
Center Luminance of White
White Variation
Cross Talk
Red
Color
Chromaticity

Green
Blue
White
Color Gamut

Viewing
Angle

Horizontal
Vertical

Symbol
CR
Gray to gray
average
LC
W
CT
Rx
Ry
Gx
Gy
Bx
By
Wx
Wy
CG
x+
xY+
Y-

Condition

Min.

Typ.
(1000)

Unit
-

Note
(2)

(8)

ms

(3)

(550)

cd/m2
%
-

(4)
(7)
(5)

x=0, Y =0
Viewing Normal
Angle

CR20

(0.652)
(0.331)
(0.275)
(0.597)
(0.143)
(0.063)
(0.285)
(0.293)
(75)
(88)
(88)
(88)
(88)

Max.

(1.3)
(4)

(6)

Target

NTSC

Deg.

(1)

Version 1.0

Issued Date: Jun. 15, 2005

Model No.: V270B1 - L01

Preliminary
Note (1) Definition of Viewing Angle (x, y):
Viewing angles are measured by EZ-Contrast 160R (Eldim)
Normal
x = y = 0
y-

y+

x-

X- = 90

6 oclock
y- = 90

y+
x+

12 oclock direction
y+ = 90

y-

x+

X+ = 90

Note (2) Definition of Contrast Ratio (CR):

The contrast ratio can be calculated by the following expression.
Contrast Ratio (CR) = L255 / L0
L255: Luminance of gray level 255
L 0: Luminance of gray level 0
CR = CR (5)
CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note (7).
Note (3) Definition of Gray to Gray Switching Time :

100%
90%

Optical
Response
10%
0%

Gray to gray
switching time

Gray to gray
switching time

Time

The driving signal means the signal of gray level 0, 63, 127, 191, 255.
Gray to gray average time means the average switching time of gray level 0 ,63,127,191,255 to each
other .

Version 1.0

Issued Date: Jun. 15, 2005

Model No.: V270B1 - L01

Preliminary
Note (4) Definition of Luminance of White (LC, LAVE):
Measure the luminance of gray level 255 at center point and 5 points
LC = L (5)
LAVE = [L (1)+ L (2)+ L (3)+ L (4)+ L (5)] / 5
L (x) is corresponding to the luminance of the point X at the figure in Note (7).
Note (5) Definition of Cross Talk (CT):
CT = | YB YA | / YA 100 (%)
Where:
YA = Luminance of measured location without gray level 0 pattern (cd/m2)
YB = Luminance of measured location with gray level 0 pattern (cd/m2)
(0, 0)

Active Area

(0, 0)

YA, U (D/2,W/8)

Active Area
YB, U (D/2,W/8)

(D/4,W/4)
YA, L (D/8,W/2)

Gray 128

YA, R (7D/8,W/2)

YB, L (D/8,W/2)

Gray
Gray0 0

YB, R (7D/8,W/2)
(3D/4,3W/4)

YA, D (D/2,7W/8)

YB, D (D/2,7W/8)

Gray 128

(D,W)

(D,W)

Note (6) Measurement Setup:

The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt temperature
change during measuring. In order to stabilize the luminance, the measurement should be
executed after lighting Backlight for 1 hour in a windless room.

LCD Module
LCD Panel
Center of the Screen

Display Color Analyzer

(Minolta CA210)

Light Shield Room

(Ambient Luminance < 2 lux)

Version 1.0

Issued Date: Jun. 15, 2005

Model No.: V270B1 - L01

Preliminary
Note (7) Definition of White Variation (W):
Measure the luminance of gray level 255 at 5 points
W = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]

Horizontal Line
D

Vertical Line

D/4

W/4

D/2

W/2

3D/4

2
X

: Test Point
X=1 to 5

3W/4

Active Area

Version 1.0

Issued Date: Jun. 15, 2005

Model No.: V270B1 - L01

Preliminary
8. DEFINITION OF LABELS
8.1 CMO MODULE LABEL
The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation.

CHI

MEI

OPTOELECTRONICS

V270B1

-L01 Rev. XX

E207943
MADE IN TAIWAN

XXXXXXXYMDLNNNN

(a) Model Name: V270B1-L01

(b) Revision: Rev. XX, for example: A0, A1 B1, B2 or C1, C2etc.
(c) Serial ID: X X X X X X X Y M D L N N N N
Serial No.
Product Line
Year, Month, Date
CMO Internal Use
CMO Internal Use
Revision
CMO Internal Use
Serial ID includes the information as below:
(a) Manufactured Date: Year: 1~9, for 2001~2009
Month: 1~9, A~C, for Jan. ~ Dec.
Day: 1~9, A~Y, for 1st to 31st, exclude I ,O, and U.
(b) Revision Code: Cover all the change
(c) Serial No.: Manufacturing sequence of product
(d) Product Line: 1 -> Line1, 2 -> Line 2, etc.

Version 1.0

Issued Date: Jun. 15, 2005

Model No.: V270B1 - L01

Preliminary
9. PACKAGING
9.1 PACKING SPECIFICATIONS
(1) 4 LCD TV modules / 1 Box
(2) Box dimensions : 742(L) X 327 (W) X 510 (H)
(3) Weight : approximately 19Kg ( 4 modules per box)

9.2 PACKING METHOD

Figures 9-1 and 9-2 are the packing method

LCD TV Module

Carton dimensions: 742(L)x327(W)x510(H)mm

Weight : Approx 19Kg(4modules per carton)

Anti-Static Bag

PE Foam(Bottom)

Drier

Carton Label

Carton

Figure.9-1 packing method

Version 1.0

Issued Date: Jun. 15, 2005

Model No.: V270B1 - L01

Preliminary

Corner Protector:L1020*50mm*50mm
Pallet:L1100*W1100*H135mm
Corrugated Fiberboard:L1100*W1100mm
Pallet Stack:L1100*W1100*H1160mm
Gross:168kg
PE Sheet
Carton Label
Film

PP Belt

Figure. 9-2 packing method

Version 1.0

Issued Date: Jun. 15, 2005

Model No.: V270B1 - L01

Preliminary
10. PRECAUTIONS
10.1 ASSEMBLY AND HANDLING PRECAUTIONS
(1) Do not apply rough force such as bending or twisting to the module during assembly.
(2) It is recommended to assemble or to install a module into the users system in clean working areas.
The dust and oil may cause electrical short or worsen the polarizer.
(3) Do not apply pressure or impulse to the module to prevent the damage of LCD panel and backlight.
(4) Always follow the correct power-on sequence when the LCD module is turned on. This can prevent the
damage and latch-up of the CMOS LSI chips.
(5) Do not plug in or pull out the I/F connector while the module is in operation.
(6) Do not disassemble the module.
(7) Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and
easily scratched.
(8) Moisture can easily penetrate into LCD module and may cause the damage during operation.
(9) High temperature or humidity may deteriorate the performance of LCD module. Please store LCD
modules in the specified storage conditions.
(10) When ambient temperature is lower than 10C, the display quality might be reduced. For example, the
response time will become slow, and the starting voltage of CCFL will be higher than that of room
temperature.

10.2 SAFETY PRECAUTIONS

(1) The startup voltage of a backlight is over 1000 Volts. It may cause an electrical shock while assembling
with the inverter. Do not disassemble the module or insert anything into the backlight unit.
(2) If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In
case of contact with hands, skin or clothes, it has to be washed away thoroughly with soap.
(3) After the modules end of life, it is not harmful in case of normal operation and storage.

Version 1.0

Issued Date: Jun. 15, 2005

Model No.: V270B1 - L01

Preliminary

CHI MEI

11. MECHANICAL CHARACTERISTICS

Version 1.0

Issued Date: Jun. 15, 2005

Model No.: V270B1 - L01

CHI MEI

Preliminary

Version 1.0

Spare Part List for LCT2701TD

Item

Part Number

Part Description

Usage Unit
/ unit
1
piece

E6203-27CD02

DISPLAY LCD

771EL27AD02-01

MAIN BOARD

set

771-L27AD02-01

TERMINAL PCBA

set

E7802-005006

DVD BOARD

piece

771LL27AD02-01

TUNER & AUDIO PCBA

set

E7802-004009

POWER BOARD PBA

set

771-L27AD01-01

KEY PCB ASSY

set

771-L32AD01-03

KEY PCB ASSY MICO DVD

set

771-L32AD01-01

REMOTE RECEIVE PCBA

set

10

E4101-027001

POWER SWITCH

piece

11

E4801-124001

SPEAKER

piece

12

E3471-000048

KEY WIRE FOR DVD

piece

13

E3471-000049

DVD SILGNAL WIRE

piece

14

E3461-064017

DVD POWER WIRE

piece

15

E3461-064019

TV+COMBO FOR DVD POWER WIRE

piece

16

E3421-925038

WIRE ASSY TJC3-2Y L=850MM SPK-L

piece

17

E3421-925053

WIRE ASSY FOR TV&DVD AUDIO L/R/MUTE

piece

18

E3421-925054

WIRE ASSY FOR TV&DVD TUNER

piece

19

E3471-002001

WIRE WS SHIELD WIRE FOR 27LCD

TV+COMBO DVD SIGNAL WIRE

piece

20

E3421-925032

WIRE ASSY L=450MM

piece

21

E3421-229007

WIRE 3P

piece

22

E3471-000044

SHIELD WIRE FOR 32LCD COMBO MICO

KEY 13P/8P+5P

piece

23

E3471-000046

SHIELD WIRE FOR MICO CMO(1366X768)

piece

24

E3461-064021

FLAT WIRE FOR 32LCD COMBO DVD

BOARD +SV POWER

piece

25

E3461-064018

FLAF WIRE FOR TV+COMBO DVD

STANDBY POWER WIRE

piece

26

E3471-000050

SHIELD WIRE FOR TV+COMBO DVD

COAXIAL WIRE

piece

27

E3461-064016

FLAF WIRE FOR TV+COMBO INVERTER

WIRE

piece

28

E3404-157005

AC CORD

piece

29

230-26LA11-01RV

STAND COVER

piece

30

200-L27AD11-STD01AV CABINET FRONT SIL/BLK

piece

31

202-L27AD11-01AV

piece

BACK CABINET BLACK

Spare Part List for LCT2701TD

Item

Part Number

Part Description

Usage Unit
/ unit
1
piece

32

206-L27AD11-01RV

SPEAKER CABINET

33

370-42D101-01

RUBBER FOOT

piece

34

E7301-010002

BATTERY AAA

piece

35

E7501-060001

REMOTE CONTROL

set

36

236-L27AD11-01RV

DVD COVER

piece

37

258-L27AD11-01RV

DVD FUNCTION KNOB COVER

piece

38

277-L32AD11-03S

FUNCTION KEY

piece

39

426-L27AD02-01S

POWER CABLE CLIP

piece

40

483-L27AD01-01S

SHIELD COVER-MAIN PCB

piece

41

436-L27AD01-01S

TERMINAL SHEET

piece

42

269-42SD01-01L

REMOTE LENS

piece

43

277-L27AD11-01S

DVD FUNCTION KNOB

piece

44

510-L27AD03-STU01K

CARTON BOX LCT2701TD

piece

45

300-L27AD06-02C

POLFOAM TOP

piece

46

300-L27AD05-02C

POLFOAM BOTTOM

piece

47

310-383550-07V

POLYBAG 38"X35"X0.5MM

piece

48

310-111404-07V

POLYBAG FOR INSTRUCTION MANUAL

11"X14"X0.04

piece

49

310-041104-01V

POLYBAG

piece

50

580-L27ADHS-TU01L

INSTRUCTION MANUAL

piece

51

579-L27AD09-01

CAUTION LABLE

piece

52

387-L32AB01-STU01H

MODEL PLATE

piece

53

590-L27AD01-03

WARRANTY CARD

piece

54

593-L27AD01-02

INSERTION CARD

piece

55

579-L27AD02-02

UPC LABEL OF G/B

piece

56

568-P46T02-02

WARNING LABEL

57

579-L32AD04-01

LASER WARNING LABEL

piece

58

579-42D103-02

ON/OFF LB ENG

piece

59

579-42D102-09

SERIAL NO/BAR CODE LABEL

piece

60

579-L32AD03-02

CLASS I LASER PRODUCT LOGO

piece

61

579-42D105-01

PROTECTIVE EARTH LABE

piece

4"X11"X0.04

piece

If you forget your V-Chip Password

- Omnipotence V-Chip Password: 8205.
- Press MENU button.
- Press LEFT RIGHT buttons to highlight "MISC" Menu.
- Press Up, Down buttons to highlight "Parentald".
- Press ENTER button to pop up "Input your Password Please".
- Use the Number buttons (0~9) to enter an omnipotence Password.
- Press ENTER button to confirm and your can select "CHANGE PASSWORD".
- Suggest: Change to your familiar Password again.

Software upgrade
- Connect the RS-232C input jack to an external control device (such as a computer) and software upgrade.

Type of connector; D-Sub 9-pin male

No.
1
2
3
4
5
6
7
8
9

Pin name
No connection
RXD (Receive data)
TXD (Transmit data)
DTR (DTE side ready)
GND
DSR (DCE side ready)
RTS (Ready to send)
CTS (Clear to send)
No Connection

9
6

RS-232C configurations
3-wire configuration
(Not standard)

7-wire configuration
(Standard RS-232C cable)

RXD
TXD
GND
DTR
DSR
RTS
CTS

PC

PDP

2
3
5
4
6
7
8

2
3
5
6
4
8
7

D-Sub 9

D-Sub 9

TXD
RXD
GND
DSR
DTR
CTS
RTS

RXD
TXD
GND
DTR
DSR
RTS
CTS

99/100
7475

PC

PDP

2
3
5
4
6
7
8

2
3
5
4
6
7
8

D-Sub 9

D-Sub 9

TXD
RXD
GND
DTR
DSR
RTS
CTS

Software upgrade Process

- Power Switch OFF.
- Connect the serial port of the control device to the RS-232 jack on the LCD-TV back panel.
RS-232C connection cables are not supplied with the LCD-TV.
- Power Switch ON. The power indicator on the front of the panel should now display red, means
that the LCD-TV is in standby mode.
- Copy the software (MTKTOOL) to the computer.
- Open the software (MTKTOOL.EXE)
- Select MTK 8205 and Point "browse" on the interface of the MTKTOOL.exe.
- Select the file which will be update.
- Point "update" on the interface of the MTKTOOL.exe.
- Waiting for the upgrader programing, when it is finished, the bar will display 100%.
- After the upgrader is finished, shut down the power switch, take out the RS-232C connection
after the power indicator is extinguished.
Note: After upgrading, the first time of power on will be some long.