EDI LP Labs

Rapid Adoption Kit - Encounter Low-Power Design Flow
Cadence Design Systems, Inc.

Rapid Adoption Kit (RAK)
Encounter Low-Power Design Flow
CPF Implementation
To get the Lab data click on: Lab_Data
Tool Version Encounter Digital Implementation 11.x and above
COPYRIGHT 2014, CADENCE DESIGN SYSTEMS, INC.

ALL RIGHTS RESERVED.
Table of Contents
Module 1:
Getting Started .................................................................................................................. 4
Lab 1-1 Introduction to the Labs ......................................................................................................... 5

Multiple Supply Voltages (MSV) and Power Shut Off (PSO) ......................................................... 5
Flow Setup/Environment Scripts ...................................................................................................... 6
Implementation Scripts..................................................................................................................... 6
Flow Directory Structure .................................................................................................................. 7
Lab 1-2 Setting Up the Workshop....................................................................................................... 8
Foundation Flow Step: run_init.tcl ................................................................................................... 8
CPF ................................................................................................................................................... 8
Lab 1-3 MMMC ................................................................................................................................. 10
Loading and Committing CPF to the Encounter System ................................................................ 10
Defining Power Domain Physical Attributes ................................................................................. 12
Power Domain Floorplan ................................................................................................................ 13
Power Switch Insertion................................................................................................................... 13
Power Planning ............................................................................................................................... 13
Lab 1-4 Generating DB by run_init.tcl ............................................................................................. 16
Module 2: Foundation Flow Step: run_place.tcl ..................................................................................... 17
Lab 2-1 Creating a Domain-Aware Placement ................................................................................. 18
DB Generated by run_place.tcl ...................................................................................................... 19
Module 3: Foundation Flow Step: run_prects.tcl .................................................................................... 20
Lab 3-1 Optimizing the Domain-Aware preCTS .............................................................................. 21
Always-on Buffering ...................................................................................................................... 22
DB Generated by run_prects.tcl ..................................................................................................... 22
Module 4: Foundation Flow Step: run_cts.tcl ......................................................................................... 23
Lab 4-1 Running the Domain-Aware Clock Tree Synthesis ............................................................. 24
DB Generated by cts step ............................................................................................................... 24
Module 5: Foundation Flow Step: run_postcts.tcl .................................................................................. 26
Lab 5-1 Running the Domain-Aware PostClock-Tree Synthesis ...................................................... 27
DB Generated by run_postcts.tcl .................................................................................................... 27
Module 6: Foundation Flow Step: run_route.tcl ..................................................................................... 28

Lab 6-1 Routing the Design .............................................................................................................. 29
DB Generated by run_route.tcl ....................................................................................................... 29
Highlighting the Results ................................................................................................................. 29
Module 7: Foundation Flow Step: run_postroute.tcl .............................................................................. 33
Lab 7-1 Running a Domain-Aware Postroute Optimization ................................................... 34
Workshop Summary ....................................................................................................................... 35
Workshop Limitation...................................................................................................................... 35

Module 1: Getting Started

Lab 1-1
Objective:
Introduction to the Labs

To introduce the concepts and materials in the workshop.
In this lab, EDI is used to implement and practice Multi-Mode-Multi-Corner (MMMC) on the simple
DMA design through the Cadence Low Power Design Foundation Flow by using CPF. This tutorial
helps you to take advantage of CPF to implement designs with multiple supply voltage (MSV) and
power shut-off (PSO) architecture, and show you how to use the LP foundation flow. This workshop
requires the EDI license with LP options to run.
The DMA gate-level netlist was generated by Cadence RTL Compiler (RC) using the same CPF.
There are separate LABs for the frontend parts such as RC and CLP.
Multiple Supply Voltages (MSV) and Power Shut Off (PSO)
Cadence Encounter Low Power Design Flow supports advanced power management techniques such
as multiple power domains with power shut-off (PSO) scheme, which can only be implemented at the
physical level (post synthesis). By adopting CPF, the designers intent for advanced power
management techniques can be captured as design and technology-related power constraints in a single
file format for use throughout the RTL and GDSII design flow including verification, validation,
synthesis, test, physical implementation, and signoff analysis.
In this workshop, CPF captures the following implementation techniques and will be loaded and
committed before power planning in this low power design flow. The explicit power domain creation
and shifter/isolation insertion will not be needed any more:
Level shifter, isolation cell, state retention cell, power switch cell definition.
Level shifter, isolation cell, power switch cell insertion rule definition.
Power/ground net creation.
Power domain and power/ground net connection creation.
Hard macro/IP low power intent modeling
Library set creation.
Different analysis view creation based on combination of different operating corner or
power mode creation and bind with different library set.
Based on different analysis views, you can practice MMMC clock tree insertion and design
optimization on different stages such as preCTS, postCTS, and postRoute stages, respectively.

Refer to the foundation flow document for detailed info. Here is a brief description about the low
power foundation flow and how to run the flow in this workshop.
The low power foundation flow consists of three flow setup/environment scripts and a number of the
implementation scripts.
Flow Setup/Environment Scripts
setup.tcl: It is unique for each design. It specifies variables for the design (netlist), libraries,
constraints including CPF, and some timing views.
edi_config.tcl: it specifies variables for the EDI flow options; and plug-in scripts.
lp_config.tcl: It specifies variables for low power related options in the EDI flow.
Implementation Scripts
run_init.tcl: create initial Database

run_place.tcl: Cell Placement
run_prects.tcl: PreCTS Optimization
run_cts.tcl: Clock Tree Synthesis
run_postcts.tcl: PostCTS Optimization
run_postcts_hold.tcl: PostCTS Hold Fixing (not shown in this workshop)

run_route.tcl: Global/Detail Route
run_postroute.tcl: PostRoute Optimization
run_postroute_hold.tcl: PostRoute Hold Fixing (not shown in this workshop)
run_postroute_si_hold.tcl: SI Hold Fixing (not shown in this workshop)
run_postroute_si.tcl: SI Optimization (not shown in this workshop)
run_signoff.tcl: Signoff Timing/Verify (not shown in this workshop)
Each flow step has optional pre and post step plugins for user to customize this step. Each step script
will automatically source its plugin scripts.
Flow Directory Structure
The workshop is under LowPower directory. Under the LowPower, the directory structure is as
follows:
LIBS/: Contains the libraries including CapTable, LEF, lib

INPUT/: The workshop data including netlist, sdc, and CPF
PLUG/: LP Foundation Flow Plug in script
EDI/: All the EDI plug scripts are in this directory
SCRIPTS/: LP Foundation Flow Makefile generation script, flow environment/setup scripts

EDI/: All LP Foundation Flow scripts are in this directory
<YourWorkingDir>/: It is created by user to run the foundation flow there.

DBS/: It is created by foundation flow script to store all the saved DBs at each
Implementation step
LOG/: It is created by foundation flow script to store all the log files at each
Implementation step
RPT/: It is created by foundation flow script to store report files at each Implementation
step
make/: It is created by foundation flow script to stamp which step has been run.

Lab 1-2
Setting Up the Workshop
1. Go to the workshop directory (LowPower)

2. mkdir <yourWorkingDir>
3. cd <yourWorkingDir>
4. cp ../SCRIPTS/setup.tcl .
5. cp ../SCRIPTS/edi_config.tcl .
6. cp ../SCRIPTS/lp_config.tcl
7. cp ../SCRIPTS/Makefile .
8. generate Make file: tclsh ../SCRIPTS/gen_edi_flow.tcl all; It generates Makefile for all the
implementation steps (not shown in this workshop)
9. make f Makefile [all|singleTarget]
Target all will run all the implementation steps. singleTarget will run the single implementation step
such as init, place, prects, cts, postcts, route, and postroute.
After each implementation step is run, you can restore this step DB and browse it with the interface.
Foundation Flow Step: run_init.tcl
The script is in ./SCRIPTS/EDI directory. It will source the two plug-in pre_init.tcl and post_init.tcl in
PLUG/EDI.
pre_init.tcl is for the automatic PG connection enhancement. It is not needed in EDI11.1 usr2.
post_init.tcl is written to do the floorplan, power switch insertion; power planning and routing in this
workshop.
1. At the command prompt, enter this command string:
make f ../SCRIPTS/Makefile init
2. It will run run_init.tcl. The script loads the design; do the floorplan, power switch insertion,
power planning and routing; and then saves the init.enc DB in the ./DBS under your working
directory.
The followings are some detailed descriptions about the major stages in the run_init.tcl.
CPF
The completed CPF file../INPUT/rc.pfi_dac.cpf contains:
Technology
Level shifter, isolation cell, state retention cell, power switch cell definition.
Design
Library set creation.

Power/ground net creation.
Power domain and its power/ground net definition; the instances PG connection is done
automatically.
Different analysis view creation.

Level shifter, isolation cell, power switch cell, and state retention cell insertion rule
definitions

Lab 1-3 MMMC

EDI11 onwards only MMMC flow is supported. In the low power flow, users can either define the
MMMC using CPF commands or EDI CTE commands (viewDefinition.tcl) or both. The
viewDefinitoin.tcl has higher priority.
In the LP foundation flow, users must specify the MMMC objects in setup.tcl, it then converts those
variables to viewDefinition.tcl under FF dir in your working directory for the design import. But, this
viewDefinition.tcl is not complete for power domain binding. The power domain binding is through
CTE command: update_delay_corner power_domain. In this workshop, this is done by
loadCPF/commitCPF (MMMC is defined in CPF). Please check viewDefinition.tcl in the init.enc.dat
under DBS directory.
Loading and Committing CPF to the Encounter System
1. To load the CPF file into EDI, use the loadCPF command. To commit the CPF in the EDI,
use the commitCPF command. Both commands are in run_init.tcl and are executed
automatically once you specify the CPF file through vars(cpf_file) in setup.tcl.
2. commitCPF also created implicit ISO or LS rules based on the power modes defined in
CPF. The implict rules are background rules without -pins and are created between all
possible two domains even if there is no logic connection. Those implict rules are used by
optDesign/BTS/verifyPowerDomain commands to prevent or check any LP Errors.
3. After loadCPF and commitCPF, run_init.tcl creates RC corners and binds them to the
views defined in CPF through the delay corners. The rc corners are specified in the
vars(rc_corners) and the binding is defined in the vars(delay_corner,rc_corner) in setup.tcl. The
delay corners are created by commitCPF. The delay corner name is the view name followed by
_dc such as <viewname>_dc.
run_init.tcl sets the active views for implementation based on the vars(active_setup_views) and
vars(active_hold_views) defined in setup.tcl. The first view in the view list is the default view.
MMMC scenario has been created by loadCFP/commitCPF and some EDI CTE commands
such as create_rc_corner and setup_analysis_view. You can take the following steps to browse
the created analysis views, delay corners, constraint modes, library sets, RC corners and the
relationship among them:
4. Restore DBS/init.enc by entering
encounter init DBS/init.enc.
5. Choose Timing Configure MMMC

You see a form with Analysis View List on the left side and Delay Corner List on the right side as
shown here.
You can click the + to browse the MMMC information.

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6. Click Close after you have browsed the MMMC.

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Defining Power Domain Physical Attributes

Besides loadCPF and commitCPF, for physical-related attributes such as minGap and rsExts are
needed to be specified for the power domains. Those attributes are defined by EDI command
modifyPowerDomainAttr in the ../PLUG/EDI/post_init.tcl which is automatically run by run_init.tcl.
MinGap is a halo around the domain fence, and serves as a placement blockage. The row
will cut in MinGap so that there is no row overlap between domains.
RouteSearchExt is a search distance for the power router to look for a legal target to connect
the power net.
modifyPowerDomainAttr PD1 -minGaps 5.0 5.0 30.0 5.0

modifyPowerDomainAttr PD1 -rsExts 20.0 20.0 45.0 20.0
Floorplanning
The post-init plug-in ./PLUG/EDI/post_init.tcl defines the die/core size using EDI command floorplan.

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Power Domain Floorplan
The power domains need to be resized and reshaped after they have been placed in the core area. To
place, resize and reshape the power domain in the core area, use the EDI command setObjFPlanBox
for rectangular power domain or setObjFPlanBoxList for rectilinear power domain. The power domain
floorplan is in ../PLUG/EDI/post_init.tcl .
Power Switch Insertion
There are two types of the power switches: column and ring switches. This workshop uses the columntype power switches. Those switches are inserted in the switchable domains after power domain
floorplan by addPowerSwitch.
Power Planning
Examine the../PLUG/EDI/scripts/post_init.tcl script.
In this workshop, a power and ground ring is created for each power domain. An M8 stripe over the
PDmac1 and PDmac2 power domains is created to connect the column-type power switch cell. In the
addStripe command, combining option -over_power_domain 1, -over_pin 1 and -master HSWX1 to
generate and connect the stripe based on the pattern of power switch cell HSWXl in both PDmacl and
PDmac2 power domains.
13

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Power Routing
The ../PLUG/EDI/post_route.tcl connects power pins for blocks and standard cells in each power
domain as shown here.

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Lab 1-4
Generating DB by run_init.tcl
After running the run_init.tcl script, the low power DB is created in DBS/init.enc. You can check low
power setup DB. Use reportShifter and reportIsolation to report shifter and isolation connections.
1. Restore DBS/init.enc by entering
encounter -init DBS/init.enc
2. Type reportShifter -outfile LS_added_after_commitCPF.rpt in the command line window

and the level shifters that were added are reported in the LS_added_after_commitCPF.rpt
file.
How many shifters are reported?
Answer:
3. Type reportIsolation -outfile ISO_added_after_commitCPF.rpt in the command line

window and the isolation cells that were added will be reported in the
ISO_added_after_commitCPF.rpt file.
How many isolation instances are reported?
4. Choose Power Multiple Supply Voltage Verify Power Domain
5. Select Shifter and Isolation Cell.
6. Click OK to verify the power domains.
7. Please find the answers in the command line window:
How many nets are missing required level-shifters?
How many nets are missing required isolation cells?
Note:
Use verifyPowerDomain to check whether the power domains are correctly setup.
To apply this command independently, run

verifyPowerDomain gconn xNetPD isoNetPD.

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Module 2: Foundation Flow Step:

run_place.tcl

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Lab 2-1
Creating a Domain-Aware Placement
1. The ../SCRIPTS/EDI/run_place.tcl does the domain aware placement. It has two plugin scripts: pre_place.tcl and post_place.tcl under ../PLUG/EDI.
2. The pre_place.tcl script is running before placement. You can put setPlaceMode to control
place behavior such as controlling ISO/LS placement(no show in this workshop).
3. The post_place.tcl script is executed after placement. It does tie-high/low insertion and
highlight ISO/LS for ISO/LS placement checking
4. The run_place.tcl does the placement using the placeDesign EDI command
5. To run this foundation step, at the command prompt, enter the following:
make f ../SCRIPTS/Makefile place
The placement result is shown here.

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DB Generated by run_place.tcl
After running run_place.tcl, the placed DB is created in DBS/place.enc.
1. You can restore it using the restoreDesign EDI command and checking the placed result
such as shifter/isolation placement.

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run_prects.tcl

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Lab 3-1
Optimizing the Domain-Aware preCTS
The ../SCRIPTS/EDI/run_prects.tcl does the domain aware preCTS optimization. It has two plug-in
scripts: pre_prects.tcl and post_prects.tcl under ../PLUG/EDI.
The pre_prects.tcl is run before optimization; it can be used for mode setting such as setOptMode
and/or setTrialRouteMode and always-on buffer availability check. From EDI 11 user can use
command called reportAlwaysOnBuffer. It reports how many always-on buffers optDesign can see per
domain. Always-on buffering has big impact on the optimization QoR. It is useful to check the alwayson buffer availability during always-on buffering. The followings are several reason that always-on
buffer is not available for buffering:
1. Always-on buffer needs to define in CPF using define_always_on_cell
2. Always-on buffer is set DontUse (using cmd setDontUse to set it false)
3. Always-on buffers should be bound to that power domain
4. Always-on buffer Site must be defined in that power domain
In this workshop, you will need to buffer the always-on nets using always-on buffers. The
pre_prects.tcl sets the always-on buffers to dont use and dont touch to false and use
reportAlwaysOnBuffer to check the always-on availability as follows:
Always on buffers found for each power domain:
PowerDomain "PD09" (pd tag = "1") has 2 always on buffer(s) to use PowerDomain
"PDmac1" (pd tag = "2") has 2 always on buffer(s) to use PowerDomain "PDmac2" (pd
tag = "3") has 2 always on buffer(s) to use PowerDomain "PDcore" (pd tag = "4") has
2 always on buffer(s) to use
Once always-on buffer is available, optDesign is able to use them whenever the always-on buffers are
necessary during DRV fixing.
The run_prects.tcl runs EDI command verifyPowerDomain to check if there is any low power violation
generated by optDesign.
1. To run this foundation step, at the command prompt, enter the following:
make f ../SCRIPTS/Makefile prects
2. After completing the preCTS optimization, you can find the initial timing summary and the
preCTS optimization final summary in the optDesign log in ./LOG/prects.log.
What is the initial worse negative slack?
What is the worst max_tran violation?
What is the prects final worse negative slack?
What is the prect final worst max_tran violation?

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Always-on Buffering
In designs that contain modules that are shut-off, there will be nets that need to be always-on buffering.
Here are some examples:
Control signals of SRPG cells

Enable nets of isolation cells
Enable nets of power switch cells
Feed-through nets
(These are nets crossing from one domain to another domain through shutoff power domain.)
Special buffers or always-on buffers are often used for buffering these nets, which have an extra power
pin that is connected to the different power net from primary power net of the location domain.
The EDI command, optDesign, can automatically detect when always-on buffers are needed according
to the driver, receiver and location power domain; and insert the always-on buffers to buffer the nets
whenever necessary; and then define the global connection for the always-on buffers secondary power
pins. Please run verifyPowerDomain isoNetPD xNetPD to check if there is any lower power
violation. It is also recommended to run CLP for signoff check.
In this workshop, the PBUFX2 and PINVX1 is an always-on buffer/inverter with a secondary power
pin
DB Generated by run_prects.tcl
After running run_prects.tcl, the preCTS optimized DB is created in DBS/prects.enc. You can restore
it using the restoreDesign EDI command and checking the optimized result such as running CLP. If
there are still a number of DRVs, you can analyze this DB and may run bufferTreeSynthesis to buffers
the remaining DRV nets.

22

run_cts.tcl

23
Lab 4-1
Running the Domain-Aware Clock Tree Synthesis
The ../PLUG/EDI/pre_cts.tcl and ../PLUG/EDI/cts.tcl do the domain-aware clock tree synthesis. The
clock specification is automatically generated by ../PLUG/EDI/pre_cts.tcl; and the clock buffers are
defined with both regular buffers and always-on buffers. clockDesign is able to choose which buffer it
need during clock synthesis. If it uses always-on buffers, it can automatically connect the always- on
buffers 2nd power pin.
The ../PLUG/EDI/cts.tcl synthesizes the clock trees using the generated clock specification. To run this
foundation step, at the command prompt, type the following:
make f ../SCRIPTS/Makefile cts
DB Generated by cts step

After running the cts step, the CTS DB is created in DBS/cts.enc. You can restore it with the
restoreDesign and check the clock tree synthesized result, such as browsing the clock tree and viewing
the clock tree graphically.
Browsing the Clock Tree
1. Restore DBS/cts.enc by entering
encounter init DBS/cts.enc.
2. To view the clock tree that crosses the power domains, choose Clock Browse
Clock Tree.
3. Select the first clock in the list.
4. Click Select in Clock Selection.
5. Select Pre-Route in Route Selection.
6. Click OK.
7. The clock tree inside a power domain is built from the fence buffers. The fence buffers
are inserted to divide the global clock net into the local clock net inside a power domain. The
fence buffers also ensure that the single entry/exit point to t/from the power domain. Fence
buffer can be either regular or always-on buffers. clockDesign decides it based on the driver,
receiver and location power domains. After you have browsed the clock tree, close the browser.
Viewing the Clock Tree in the Graphical Interface
1. To visualize the clock tree in the GUI, select Clock Display Display Clock Tree.
2. Select Pre-Route in Route Selection.
3. Select Display Clock Tree and All level and then click OK.
You might want to turn off the view of nets and snets to better view the clock tree.
24
4. To clear the clock tree display after you finished looking at it, select Clock Display
Clear Clock Tree Display.

25

run_postcts.tcl

26
Lab 5-1
Running the Domain-Aware PostClock-Tree Synthesis
The ../SCRIPTS/EDI/run_postcts.tcl does the domain aware postCTS optimization. The optimization
setups are the same as those in preCTS optimization. Always-on buffers are available whenever
necessary. In this workshop, we skip the postCTS hold optimization.
1. To run this foundation step, at the command prompt, type the following:
make f ../SCRIPTS/Makefile postcts
DB Generated by run_postcts.tcl
After running the run_postcts.tcl script, the postCTS optimized DB is created in DBS/postcts.enc.
1. You can restore it using the restoreDesign EDI command.

27

run_route.tcl

28
Lab 6-1
Routing the Design
The ../SCRIPTS/EDI/run_route.tcl routes the design. It has two plug-in scripts: pre_route.tcl and
post_route.tcl under ../PLUG/EDI.
The pre_route.tcl script is run before the routing. It routes the secondary power pin for always-on
buffers, level shifters, and SRPG cells using the routePGPinUseSignalRoute command.
setNanoRouteMode routeStripeLayerRange 4:8 to control the 2nd power pin routing layers. It then
sets the route mode using the setNanoRouteMode EDI command.
The post_route.tcl script is run after the routing. It inserts the fillers using the addFiller EDI command.
1. To run this foundation step, at the command prompt, type the following:
make f ../SCRIPTS/Makefile route
DB Generated by run_route.tcl
After running the run_route.tcl script, the routed DB is created in DBS/route.enc. You can restore it
using the restoreDesign EDI command.
Next, explore GUI highlight and power debug using the routed DB.
Highlighting the Results
1. Restore DBS/route.enc by entering
encounter init DBS/route.enc
2. Select Physical View above the All Colors button. Deselect the visibility for types Net
and Special Nets. This choice turns them off and allows better visibility of the analysis results.
3. Choose Power Multiple Supply Voltages Highlight Power Domain.

4. Try to select different objects and then click Highlight to see selected object highlighted in
the interface.

29
5. Deselect the objects and Clear All to clear the highlights and then try other objects.
6. Click the Signal Nets/HLS Cell tab, select the PDcore power domain for Src. of PD.
7. Click Add to add one entry to the left panel, and then select this new added entry
Net:PDcore

30
8. Click Highlight to see nets inside PDcore to be highlighted in the interface. Deselect Net and
Special Net under All Colors.
Do you find any net routed as feed through?

31
9. Click Clear All to clear the highlights.

10. Click Close to close the form.

32

run_postroute.tcl

33
Lab 7-1 Running a Domain-Aware Postroute Optimization

The ../SCRIPTS/EDI/run_postcts.tcl does the domain-aware postroute optimization. After
optimization, you can find out the final timing numbers in the optDesign log in
./LOG/postroute.log.
What is the worst slack reported by optDesign?
1. To run this foundation step, at the command prompt, enter this command string:
make f ../SCRIPTS/Makefile postroute
DB Generated by run_route.tcl
1. After running the run_postroute.tcl script, the postroute optimized DB is created in
DBS/postroute.enc. You can restore it using the restoreDesign EDI command.
The optDesign EDI command can do leakage power optimization while optimizing
timing and area by setting setOptMode -leakagePowerEffort.
Note: In this workshop, you do not turn on this option. If you want to turn it on, you
need to load the HVT, RVT, and LVT libraries.

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Congratulations on finishing the Encounter Low-Power Design Flow CPF Implementation lab.
Workshop Summary
You completed the following steps to implement a multiple-power-domain design by CPF
under MMMC.
Create Power Domain and Insert Level Shifter and Isolation Cell using CPF.
MSV floorplanning
MSV power gating
MSV power planning and routing
MMMC optimization and always-on buffering.
Power mode aware clock tree synthesis
2nd power pin routing
We have used the EDI LP foundation flow to go through each step. You can see the default
command/option setups throughout the flow by checking the EDI run logs in the LOG directory
of your run directory.
Although the test case design is small, all steps that have been performed are applicable to a
design of a larger size.
Workshop Limitation
This workshop uses the general library developed by Cadence so that we can deliver the
workshop to customers. However, the library is still in the first release, it still needs some
enhancements such as the pin access for the route.

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Rapid Adoption Kit - Encounter Low-Power Design Flow

Cadence Design Systems, Inc.

Tool Version Encounter Digital Implementation 11.x and above

COPYRIGHT 2014, CADENCE DESIGN SYSTEMS, INC.

Rapid Adoption Kit - Encounter Low-Power Design Flow

Getting Started .................................................................................................................. 4

Lab 1-1 Introduction to the Labs ......................................................................................................... 5

Rapid Adoption Kit - Encounter Low-Power Design Flow

Module 6: Foundation Flow Step: run_route.tcl ..................................................................................... 28

COPYRIGHT 2014, CADENCE DESIGN SYSTEMS, INC.

Rapid Adoption Kit - Encounter Low-Power Design Flow

Module 1: Getting Started

COPYRIGHT 2014, CADENCE DESIGN SYSTEMS, INC.

Rapid Adoption Kit - Encounter Low-Power Design Flow

Introduction to the Labs

COPYRIGHT 2014, CADENCE DESIGN SYSTEMS, INC.

Rapid Adoption Kit - Encounter Low-Power Design Flow

run_init.tcl: create initial Database

Rapid Adoption Kit - Encounter Low-Power Design Flow

run_postcts_hold.tcl: PostCTS Hold Fixing (not shown in this workshop)

LIBS/: Contains the libraries including CapTable, LEF, lib

SCRIPTS/: LP Foundation Flow Makefile generation script, flow environment/setup scripts

<YourWorkingDir>/: It is created by user to run the foundation flow there.

COPYRIGHT 2014, CADENCE DESIGN SYSTEMS, INC.

Rapid Adoption Kit - Encounter Low-Power Design Flow

Setting Up the Workshop

1. Go to the workshop directory (LowPower)

Rapid Adoption Kit - Encounter Low-Power Design Flow

Library set creation.

Different analysis view creation.

COPYRIGHT 2014, CADENCE DESIGN SYSTEMS, INC.

Rapid Adoption Kit - Encounter Low-Power Design Flow

Lab 1-3 MMMC

5. Choose Timing Configure MMMC

COPYRIGHT 2014, CADENCE DESIGN SYSTEMS, INC.

Rapid Adoption Kit - Encounter Low-Power Design Flow

6. Click Close after you have browsed the MMMC.

COPYRIGHT 2014, CADENCE DESIGN SYSTEMS, INC.

Rapid Adoption Kit - Encounter Low-Power Design Flow

Defining Power Domain Physical Attributes

modifyPowerDomainAttr PD1 -minGaps 5.0 5.0 30.0 5.0

COPYRIGHT 2014, CADENCE DESIGN SYSTEMS, INC.

Power Domain Floorplan

Rapid Adoption Kit - Encounter Low-Power Design Flow

Rapid Adoption Kit - Encounter Low-Power Design Flow

COPYRIGHT 2014, CADENCE DESIGN SYSTEMS, INC.

Rapid Adoption Kit - Encounter Low-Power Design Flow

COPYRIGHT 2014, CADENCE DESIGN SYSTEMS, INC.

Rapid Adoption Kit - Encounter Low-Power Design Flow

2. Type reportShifter -outfile LS_added_after_commitCPF.rpt in the command line window

3. Type reportIsolation -outfile ISO_added_after_commitCPF.rpt in the command line

To apply this command independently, run

COPYRIGHT 2014, CADENCE DESIGN SYSTEMS, INC.

Rapid Adoption Kit - Encounter Low-Power Design Flow

Module 2: Foundation Flow Step:

COPYRIGHT 2014, CADENCE DESIGN SYSTEMS, INC.

Rapid Adoption Kit - Encounter Low-Power Design Flow

Creating a Domain-Aware Placement

COPYRIGHT 2014, CADENCE DESIGN SYSTEMS, INC.

Rapid Adoption Kit - Encounter Low-Power Design Flow

COPYRIGHT 2014, CADENCE DESIGN SYSTEMS, INC.

Rapid Adoption Kit - Encounter Low-Power Design Flow

Module 3: Foundation Flow Step: