[CSM51A F10] Homework 2

Assigned: 10/8/10 Due: 10/15/10

TAs: Pouya Dormiani (pouya@cs.ucla.edu), Jet Jiang (jetjiang@cs.ucla.edu)
Homework is due beginning of discussionno exceptions!

Problem 1
The exclusive-or (Xor) of two variables is defined as x y = x0 y + xy 0 . You may not use any truth tables.
1. Prove or disprove that Xor is associative.
Solution:
x (y z) = x0 (y z) + x(y z)0
= x0 y 0 z + x0 yz 0 + xyz + xy 0 z 0
= (x0 y + xy 0 )z 0 + (xy + x0 y 0 )z
= (x y) z
2. Prove or disprove that x (y + z) = x y + x z.
Solution:
x y + x z = x0 y + xy 0 + x0 z + xz 0
= x(y 0 + z 0 ) + x0 (y + z)
= x( yz )0 + x0 ( y + z )
| {z }
|{z}
f1 =yz

f2 =y+z

Since f1 6= f2 , then x (y + z) 6= x y + x z

3. Prove or disprove that: if x y = z y, then x = z.

Solution:
xy =zy
0

(x y + xy 0 ) = (z 0 y + zy 0 )
(x0 y + xy 0 )x = x(z 0 y + zy 0 )
xy 0 = xz 0 y + xzy 0
(xy 0 )y 0 = (xz 0 y + xzy 0 )y 0
xy 0 = xzy 0
x = xz x = z

Problem 2
What are the maxterms of the following gate?

x
z
y
output
y

1. What are the maxterms of the gate?

Solution:
The maxterms correspond to the expression corresponding to the pull-down network of the gatethis is
because the pull-down network is the network which produces an output of zero.
(x + y)z + (x + y)(y + z)

xyz

output

000
001
010
011
100
101
110
111

1
1
0
0
1
0
0
0

M (2, 3, 5, 6, 7)

2. Simplify this gate to use the fewest number of transistors. Draw the circuit diagram for your improved gate
design.
2

Solution:

f (x, y, z) = (x + y)z + (x + y)(y + z)

= xz + yz + xy + xz + yy + yz
= xz + y

y
output
x

Problem 3
A mystery gate is provided to you having three inputs and two outputs. By trying different input sequences to
the gate you have obtained the following table. Prove or disprove that the gate is universal.

x1 x2 x3

x1 x2 x3

z1 z0

000
001
010
011
100
101
110
111

00
01
01
10
01
10
10
11

?
z1

z2

Solution:
z1 (x, y, z) = x1 x2 x3
z2 (x, y, z) = x1 x2 + x1 x3 + x2 x3
Forming a Not gate,
z1 (1, 0, x) = 1 0 x = 1 x = x0
Forming an Or gate,
z2 (1, x, y) = x + y + xy = x + y
3

Forming an And gate,

z2 (0, x, y) = xy

Problem 4
A multiplexor (MUX) has the following switching function. Fig. 3.8(c) of your book shows how a two-input MUX
can be implemented using transmission gates.

z
s

sx1 x0

000
001
010
011
100
101
110
111

0
0
1
1
0
1
0
1

Can a fixed number of multiplexors be used to implement any arbitrary switching function with 3-inputs? If
not, why? If yes, then how?
Solution:
0
1s
0
0

1s

1s

0
0

f (x, y, z)

1s

1s
0
0

1s

1s

Problem 5
Convert the following truth table to a switching expression and simplify it as much as possible.
x2
0
0
0
0
1
1
1
1

x1
0
0
1
1
0
0
1
1

x0
0
1
0
1
0
1
0
1

z
0
0
0
1
1
0
1
1

Solution:
z(x2 , x1 , x0 ) = x02 x1 x0 + x2 x01 x00 + x2 x1 x00 + x2 x1 x0
= x1 x0 (x02 + x2 ) + x2 x00 (x01 + x1 )
= x1 x0 + x2 x00

Problem 6
We have a logic family which uses the following voltages to represent binary values:
VHmax
VHmin
VLmax
VLmin

3.3V
2.0V
0.8V
0.0V

The following shows the results of some measurements on a circuit. x1 and x0 are inputs and z is the output.
x1 (V)
3.3
0.1
0.7
3.2
0.1
3.0

x0 (V)
3.0
0.2
2.3
0.8
3.3
0.5

z(V)
2.5
0.1
0.3
0.6
0.0
0.4

What logic gate does this circuit implement? (Hint: Consider both positive and negative logics.)
Solution: Using the voltage specification, we have the follwing interpretation:
x1
VH
VL
VL
VH
VL
VH

x0
VH
VL
VH
VL
VH
VL

z
VH
VL
VL
VL
VL
VL

After eliminating those redundant but consistent rows, we have the following results for positive logic and
negative logic respectively:

x1
0
0
1
1

positive
x0
0
1
0
1

z
0
0
0
1

x1
1
1
0
0

negative
x0
1
0
1
0

z
1
1
1
0

Therefore, this circuits implements AND gate for positive logic and OR gate for negative logic.

Problem 7
Suppose we need to implement the switching expression (a0 + bc) using a CMOS circuit. Consider the following
implementations:
5

1. Draw the naive implementation of the above switching expression using NOT, AND, and OR logic gates.
2. Transform the above switching expression such that only NAND operation appears in the expression. (Hint:
DeMorgans Law!)
3. Draw the logic gate implementation of the above transformed expression. How many transistors are used in
the naive implementation and the transformed implementation, respectively?
Solution:
1.

b
c
2. a0 + bc = a0 + ((bc)0 )0 = (a(bc)0 )0
3.

b
c
The naive implementation uses 2 (1 NOT) + 6 (1 AND) + 6 (1 OR) = 14 transistors; The transformed NAND
implementation uses 8 (2 NAND) transistors, which is more efficient.

Problem 8
Derive an quivalent NOR implementation for the following NAND circuit.
x
y

g1

g2

g4

g3

Solution:
First we derive an equivalent switching expression which only involves NOR operations:
f (x, y, z) = (x(xy)0 )0 (y(xy)0 )0 z)0
= ((x0 + xy)(y 0 + xy)z)0
= ((x0 + y)(y 0 + x)z)0
= ((x0 y 0 + xy)z)0
= (x0 y 0 z + xyz)0
= ((x + y + z 0 )0 + (x0 + y 0 + z 0 )0 )0
The circuit is as follows: