Interrupt

Dr. Amr Elsayed

Interrupt

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Interrupt

An interrupt allows a program or an external device to
interrupt the execution of a program.

The generation of an interrupt can occur by



Hardware (hardware interrupt)

Software (softwareinterrupt).

When an interrupt occurs an interrupt service routine

(ISR) is called.

A hardware interrupt the ISR then communicates with

the device and processes any data, Then returns to the
original program.

A software interrupt includes reading a key from the
keyboard,
keyboard outputting text to the screen and reading the
current date and time.
time

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Software interrupts

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BIOS and the operating system

The BIOS has two main parts


The first is the part permanently stored in a ROM (the

ROM BIOS).
BIOS It starts the computer (or bootstap) and
contains programs which communicate with resident
devices.

The second stage is loaded when the operating

system is started.
started This part is non-permanent and
allows the user to access the hardware in an easy-touse manner. It accepts commands from the keyboard
and displays them to the monitor.

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BIOS and the operating system

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Interrupt vectors

Interrupt vectors are addresses which inform the
interrupt handler as to where to find the ISR.

All interrupts are assigned a number from 0 to 255.

The interrupt vectors associated with each interrupt

number are stored in the lower 1024 bytes of PC
memory.

The first two bytes store the offset and the next two
store the segment address.
address

For example,



Interrupt 0 is stored from 0000:

0000:0000 to 0000:
0000:0003

Interrupt 1 from 0000:

0000:0004 to 0000:
0000:0007,
0007 and so
on.

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Processor interrupts

The processor-generated interrupts normally
occur either when a program causes a certain
type of error or if it is being used in a debug
mode.

In the debug mode the program can be made to

break from its execution when a break-point
occurs.

This allows the user to test the status of the
computer.

It can also be forced to step through a program
one operation at a time (single-step mode).

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Hardware Interrupts

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Hardware Interrupts

To service external equipment



Polling
Interrupt-driven software

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Hardware Interrupts
Interrupt Handling

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Interrupt Vectors

Each device that requires to be interrupt-driven is
assigned an IRQ (interrupt request) line.

Each IRQ is active high.

The first eight (IRQ0IRQ7) map into interrupts 8 to 15

(08h0Fh)

The next eight (IRQ8IRQ15) into interrupts 112 to 119

(70h77h).

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Interrupt Vectors

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Interrupt Vectors

Interrupt handling

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Typical uses of Interrupts

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Typical uses of Interrupts

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Typical uses of Interrupts

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Typical uses of Interrupts

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Programmable interrupt controller (PIC)

8259 is Programmable Interrupt Controller (PIC)

It is a tool for managing the interrupt requests.
requests.

8259 is a very flexible peripheral controller chip:





PIC can deal with up to 64 interrupt inputs

interrupts can be masked

various priority schemes can also programmed.

originally (in
(in PC XT)
XT) it is available as a separate IC

Later the functionality of (two PICs) is in the
motherboards chipset.
chipset.

In some of the modern processors, the functionality of

the PIC is built in.
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Programmable interrupt controller (PIC)

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Programmable interrupt controller (PIC)

8-bit bibi-directional data bus, one address line is needed,

PIC has two control registers to be programmed, you can think of

them as two output ports or two memory location.

The direction of data flow is controlled by RD and WR.

CS is as usual connected to the output of the address
decoder.

Interrupt requests are output on INT which is connected
to the INTR of the processor. Int. acknowledgment is
received by INTA.

IR0
IR0-IR7
IR7 allow 8 separate interrupt requests to be
inputted to the PIC.

sp/en=1
sp/en=1 for master , sp/en=0
sp/en=0 for slave.

CAS0
CAS0-3 inputs/outputs are used when more than one
PIC to cascaded.

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Programmable interrupt controller (PIC)

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Programmable interrupt controller (PIC)

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Programmable interrupt controller (PIC)

Example of two cascaded PICs

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Programmable interrupt controller (PIC)

Example of
two cascaded
PICs

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Programmable interrupt controller (PIC)

OPERATION

PIC is to be initialized and programmed to control its

operation.

The operation in simple words:

when an interrupt occurs , the PIC determines the highest

priority, activates the processor via its INTR input, and
sends the type number onto the data bus when the
processor acknowledges the interrupt.

Priority:

What is used in PC is fully nested mode. That is the lowest

numbered IRQ input has highest priority. Lower priority
interrupts will not be forwarded to the processor until the
higher priority interrupts have been serviced.
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Programmable interrupt controller (PIC)

a) Simultaneous interrupt requests arrive on IR4 and IR6. IR4 has highest
priority and its IS bit is set as the IR4 service routine is put in service. (b)
The IR4 service routine issues a rotate-on-nonspecific-EOI command,
resetting IS4 and assigning it lowest priority. IR6 is now placed in service.
(c) The IR6 service routine issues a rotate-on-nonspecific-EOI command,
resetting IS6 and assigning it lowest priority.

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Programmable interrupt controller (PIC)

Interrupt port addresses

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Programmable interrupt controller (PIC)

Interrupt mask register bit definitions

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Programmable interrupt controller (PIC)

Interrupt control register bit
definitions

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Programmable interrupt controller (PIC)

Example:
Example:

the lines IRQ0

IRQ0, IRQ1
IRQ1 and IRQ6
IRQ6 are allowed to interrupt the
processor, whereas, IRQ2
IRQ2, IRQ3
IRQ3, IRQ4
IRQ4 and IRQ7
IRQ7 are disabled.
disabled.

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