International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)

Web Site: www.ijettcs.org Email: editor@ijettcs.org, editorijettcs@gmail.com

Volume 1, Issue 2, July August 2012
ISSN 2278-6856

IMPLEMENTATION OF ALU USING FPGA

Shikha Khurana1, Kanika Kaur2
M.Tech Student, KIIT Gurgaon, India 1
Research Scholar, JJTU, Rajasthan, India

Abstract: This paper primarily deals with the construction

of arithmetic Logic Unit (ALU) using Hardware Description
Language (HDL) using Xilinx ISE 9.2i and implement them
on Field Programmable Gate Arrays (FPGAs) to analyze the
design parameters.. ALU of digital computers is an aspect of
logic design with the objective of developing appropriate
algorithms in order to achieve an efficient utilization of the
available hardware. The hardware can only perform a
relatively simple and primitive set of Boolean & arithmetic
operations and are based on a hierarchy of operations that
are built by using algorithms employing the hardware. Speed,
power and utilization of ALU are the measures of the
efficiency of an algorithm. In this paper, we have simulated
and synthesized the various parameters of ALUs by using
VHDL on Xilinx ISE 9.2i and SPARTAN 3E FPGA board.

Keywords: FPGA, ALU, XILINX

1. INTRODUCTION
The design and implementation of FPGA based
Arithmetic Logic Unit is of core significance in digital
technologies as it is an integral part of central processing
unit. ALU is capable of calculating the results of a wide
variety of basic arithmetical and logical computations.
The ALU takes, as input, the data to be operated on
(called operands) and a code, from the control unit,
indicating which operation to perform. The output is the
result of the computation. Designed ALU will perform the
following operations:
Arithmetic operations
Bitwise logic operations
All the modules described in the design are coded using
VHDL which is a very useful tool with its degree of
concurrency to cope with the parallelism of digital
hardware. The top level
module connects all the stages into a higher level at
Register Transfer Logic (RTL). RTL describes the
requirements of data and control units in terms of digital
logic to execute the desired operations. Each instruction
from the architecture's instruction set is defined in detail
in the RTL Once identifying the individual approaches
for input, output and other modules, the VHDL
descriptions are run through a VHDL simulator and then
is downloaded the design on FPGA board for verification.

2. DESIGN OF TOP LEVEL (RTL) VHDL ODULE

OF 4- BIT ARITHMETIC LOGICAL UNIT (ALU)

Volume 1, Issue 2 July-August 2012

High level design methodology allows managing the

design complexity in a better way and reduces the design
cycle. [10]. A high-level model makes the description and
evaluation of the complex systems easier. RTL
description specifies all the registers in a design, and the
combinational logic between them. The registers are
described either
explicitly through component
instantiation or implicitly through inference [3]. The
combinational logic is described by logical equations,
sequential control statements subprograms, or through
concurrent statements [3]. Designing at a higher level of
abstraction delivers the following benefits [10]:
Manages complexity: Fewer lines of code improves
productivity and reduces error.
Increases design reuse: Implementation of
independent designs as cell library & reuse in
various models.
Improves verification: Helps to run process faster

Figure 1 Block Diagram of ALU [6]

3. OPERATION OF ALU
There are two kinds of operation which an ALU can
perform first part deals with arithmetic computations and
is referred to as Arithmetic Unit. It is capable of addition,
subtraction, multiplication, division, increment and
decrement. The second part deals with the Gated results
in the shape of AND, OR, XOR, inverter, rotate, left shift
and right shift, which is referred to as Logic Unit. The
functions are controlled and executed by selecting
operation or control bits.
3.1 Software Approach
The VHDL software interface used in this design reduces
the complexity and also provides a graphic presentation
of the system. The key advantage of VHDL when used for
systems design is that it allows the behavior of the
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International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)

Web Site: www.ijettcs.org Email: editor@ijettcs.org, editorijettcs@gmail.com
Volume 1, Issue 2, July August 2012
ISSN 2278-6856
required system to be described (modeled) and verified
(simulated) before synthesis tools translate the design into
real hardware (gates and wires). This software not only
compiles the given VHDL code but also produces
waveform results.
3.2 Hardware Approach
The VHDL code which implies the hardware part of ALU
is downloaded on FPGA processor using JTAG cable
interfacing PC and the hardware element. A final point is
that when a VHDL model is translated into the "gates and
wires" that are mapped onto a programmable logic device
i.eFPGA, and then it is the actual hardware being
configured, rather than the VHDL code being "executed"
as if on some form of a processor chip.

4. VHDL CODE OF 4- BIT ALU

Following portion of the VHDL code uses Data Flow
Style of Modeling for implementation Logical and
Arithmetic functions:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity alu is
Port ( a : in STD_LOGIC_VECTOR (03
downto 0);
b : in STD_LOGIC_VECTOR (03
downto 0);
opcode : in STD_LOGIC_VECTOR
(03 downto 0);
y : out STD_LOGIC_VECTOR (03
downto 0));
end alu;
Architecture Behavioral of alu is
begin
with opcode (3 downto 0) select
y<= a when "0000",
(not a) when "0001",
b when "0010",
(not b) when "0011",
a and b when "0100",
a or b when "0101",
a nand b when "0110",
a nor b when "0111",
a xor b when "1000",
a+1 when"1001",
b+1 when "1010",
a+b when "1011",
a-1 when "1100",
b-1 when "1101",
a-b when "1110",
a xnor b when "1111",
"0000" when others;
end Behavioral;

ALU Specifications:
OPCOD
E
0000

Table 1
OPERATION SPECIFICATIONS
A

0001

NOT a

0010

0011

NOT b

0100

a AND b

0101

a OR b

0110

a NAND b

0111

a NOR b

1000

a XOR b

1001

a+1

1010

b+1

1011

a+b

1100

a-1

1101

b-1

1110

a-b

1111

a XNOR b

Y is assigned the
value of a (input)
Y is assigned the
value of NOT a
Y is assigned the
value of b (input)
Y is assigned the
value of NOT b
Y is assigned the
value of a AND b
Y is assigned the
value of a OR b
Y is assigned the
value of a NAND b
Y is assigned the
value of a NOR b
Y is assigned the
value of a XOR b
Y is assigned the
value of increment a
Y is assigned the
value of increment
b
Y is assigned the
value of a + b
Y is assigned the
value of a -1
Y is assigned the
value b-1
Y is assigned the
value of a -b
Y is assigned the
value a XNOR b

5. SYNTHESIS RESULT
5.1 RTL VIEW

Fig.2

Volume 1, Issue 2 July-August 2012

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International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)

Web Site: www.ijettcs.org Email: editor@ijettcs.org, editorijettcs@gmail.com
Volume 1, Issue 2, July August 2012
ISSN 2278-6856
7. IMPLEMENTATION OF ALU ON FPGA BOARD
The VHDL coding of this paper design is compiled and
simulated using Xilinx ISE 9.2 i and has been
downloaded in FPGA using SpartanXC3S100E kit as
shown in Figure 4 The data is updated in the kit using
two separate select inputs A and B each carrying 4 bits.
The function of FPGA is embedded on the kit along with
PROM, LCD, LEDs and DIP switches. A Joint Test
Action Group (JTAG) interface connects the FPGA chip
with PROM and leads to PC through a serial interface.
Since FPGA is a user programmable, therefore JTAG is
of core significance. PROM has several postulates in the
shape of data storage and debugging, permanent storage
of data, consistency of operation, low cost, high speed and
compactness. PROM used in this design of
ALUisXC10S, which is equipped with the inbuilt
circuitry to support and store complex functions.

Fig. 3
5.2 Technology View

Figure 6 [11]

Figure 4

6. SIMULATION
By behavioral simulation for a-b where a = 10 & b = 8:Y = a-b =2, gives following results:

Figure 7[11]

Figure 5

Volume 1, Issue 2 July-August 2012

In real time application, after the process of compilation

and simulation of the VHDL design, the hardware
realization is carried out and tested as shown in Fig. 5.
Here the 4-bit inputs are given by means of two sets of
DIP switches and the output can be displayed on a LCD
panel and the result can be verified with the simulated
output. The status of the flag registers is indicated by a
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International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)

Web Site: www.ijettcs.org Email: editor@ijettcs.org, editorijettcs@gmail.com
Volume 1, Issue 2, July August 2012
ISSN 2278-6856
series of 8-bit LEDs. The provision of a select switch used
in this hardware enables the user to perform the required
operation on the FPGA processor.

8. CONCLUSION
This study helped to understand the complete flow of
RTL design, starting from designing a top level RTL
module for 4-bit ALU using hardware description
language, VHDL. Verification of the designed RTL code
using simulation techniques, synthesis of RTL code to
obtain gate level netlist using Xilinx ISE tool and
Arithmetic Logic Unit was successfully designed and
implemented using Very High Speed Hardware
Descriptive Language and Xilinx Spatan-3E Field
Programmable Gate Array.

published a book titled Digital System Design by

SciTech Publication in 2009.Editor of 05 Technical
Proceedings of National & International Seminars.
Convener of many National and International
Symposium. Life member of IETE & ISTE. Awarded as
best academic personality& HOD in 2007 and 2008
NIEC, Delhi. Convener of Research Journal of KIIT
College of Engineering
Shikha Khurana (Lecturer , KIIT, Gurgaon) received
B.E (ECE) from Sant Longowal Institute of Engineering
& Technology (Punjab)in 2004 and presently pursuing
M.Tech. from MDU , Rohtak. Member of Institution of
Engineers India (IEI).

REFERENCES
[1] B.Stephen Brown, V.Zvonko, Fundamentals of
digital logic with VHDL Design2ndEdition,Mc Graw
Hill International Edition, 2005.
[2]Charles H.Roth, Jr., Digital System Design using
VHDL, PWS Publishing Company, 2006.
[3] Douglas L. Perry, VHDL, third edition, McGrawHill, pp. 60-63, 238, July 1999.
[4].Mark Zwolinski, Digital System Design with
VHDL, Prentice Hall, 2000.
[5] Pedroni, Digital Logic Design using VHDL.
[6] S.Kaliamurthy, R.Muralidharan, VHDL Design of
FPGA Arithmetic Processor International Conference
on Engineering and ICT, 2007.
[7] Digilent, Inc.., Spartan 3E Starter Board, Date
Accessed June 2000 http://www.digilentinc.com
[8] Fraunhofer IIS, From VHDL and Verilog to
System.www.iis.fraunhofer.de/bf/ic/icdds/arb_sp/vhdl.
jsp.
[9]Xilinx Technologies, Xilinx Data Sheet for
XC3S100E.http://direct.xilinx.com/bvdocs/publications
/ds312.pdf.
[10]http://www.forteds.com/behavioralsynthesis/index.
asp
[11]Prof. S. Kaliamurthy & Ms. U. Sowmmiya,
VHDL design of arithmetic processor ,Global
Journals Inc.(USA) , November 2011.

Authors
Kanika Kaur (Associate Professor,
KIIT,
Gurgaon)
received
B.Sc
(Electronics) Hons. Degree from Delhi
University in 1997 and M.Sc
(Electronics) Hons. Degree from Jamia
Millia Islamia University in 1999.She
received M.Tech degree from RTU in
2005 and presently pursuing Ph.D from the JJTU,
Rajasthan in the field of Low power VLSI designsubthreshold leakage reduction technique for CMOS.
Published more than 20 research papers in national,
international journal & conferences. She has also
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