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NTNU

Project report
Design of integrated circuits
Daniel Salazar and Filip Savic
21-Nov-14

Abstract
This project deals with the design of a four pixel digital camera and covers the design of both the analog
and the digital parts. The technology used in the analog part of the project was 65 nm CMOS, while for the design
of digital circuits we used the Verilog hardware description language.
This report explains our approach to the problem and provides a basis foundation for the discussion of
the suitability of our proposed solutions.
The report consists of five parts: the introduction provides a more detailed description of the project, the
design of the analog circuitis focused on analog part with discussion of some of the problems we encountered,
the results and simulations, the Design of the digital part, theConclusion and feedback were our results are
summarized, and the Appendix with the corresponding Verilog code.

Contents
Abstract ........................................................................................................................................................................ 2
1.

Introduction .......................................................................................................................................................... 4

2.Analog design ............................................................................................................................................................ 5


2.1. Description of circuit and dimensioning of transistors ..................................................................................... 5
2.2. Simulation and design verification .................................................................................................................... 9
2.3.Layout, DRC and Layout vs Schematic analysis ................................................................................................12
2.5. Post layout simulation .....................................................................................................................................13
3.Digital design ...........................................................................................................................................................16
3.1. State machine ..................................................................................................................................................16
3.2. Timer ..............................................................................................................................................................23
3.3.

Exposure time control circuit ..................................................................................................................... 24

3.4.

Complete design .........................................................................................................................................28

4.

Conclusion and feedback ....................................................................................................................................30

5.

APPENDIX ............................................................................................................................................................31

1. Introduction
In this report we summarize our project workfor the course of Design of integrated circuits
TFE4152 at NTNU. We had approximately three months to design a four pixel digital camera that was
able to condition the signal of an image sensor depending on the user exposure settings. We also had to
create a control block in order to enable the user to change exposure time, take pictures and reset the
system. We divided the project into two parts; the analog and the digital.
For the analog part--covered in detail in section 2--we devised a pixel circuit that consisted of two
switching transistors thatcontrolled exposure and erasure, a sampling capacitor, a voltage buffer readout
switch and one active load.
For the digital part we created a control mechanism that modified exposure time and activated
signal readout procedure in accordance to a defined state diagram. Auxiliary modules where implemented
such as timers to create a complete digital design.
For both parts we carried out the necessary simulations in order to verify our design. We have also
proposed some modifications for the pixel circuit which we found useful. In addition, concerningthe
digital part, we have carried out a very time demanding but interesting task of designing the complete
digital section using structural description, i.e. implementing basic modules in gate level. The design tools
that were used are Cadence and Active HDL. For the analog design the 65 nm CMOS technology was
used.

2.Analog design
2.1. Description of circuit and dimensioning of transistors

The analog subsystem consists of four pixel modules whose schematic is given in figure 2.1

Fig. 2.1 Pixel circuit


These pixel circuits are organized in the following way:

Fig. 2.2 Analog part of 4-pixel camera


5

The idea is that, after exposure takes place and the voltage at the output of the pixel circuit, which
should be proportional to quantity of light acquired by the sensor, is obtained , then, by successive
readout of the rows and AD conversion, digital information is obtained.
If we take a closer look at the pixel circuit it can be concluded that certain elements have the
following functions:
1. NMOS transistor M1 (switch) controls exposure
2. NMOS transistor M2 (switch) controls erasure
3. Capacitor Cs preserves the input information during readout
4. PMOS transistor M3 (source follower) serves as a voltage buffer
5. PMOS transistor M4 (switch) passes buffered input to the output part of the circuit
6. PMOS transistor MCx (active load)
From these functions, one can make approximations regarding the dimensions of certain
transistors. For example, the PMOS transistor which serves as the active load should have the longest
channel length and the shortest channel width as possible to maximize resistance. On the other hand,

regarding PMOS transistors M3and M4, their ratio should be as large as possible.

To explain this, let us first consider transistor M3 which serves, as mentioned before, as a some
sort of voltage buffer. This transistor works in configuration of common drain (or source follower), so its
voltage gain is given as:
 =

 
< 1,
  + 1

  

In our case, we want the gain to be as close as possible to the unitary gain. This can be

accomplished by increasing the transconductance  which is directly proportional to square root of  .
When the switch M4is turned on it would be optimal to have a voltage drop as low as possible
thus its resistance should be relatively very small.Lets we take a closer look at this part of the circuit.

Fig.2.3
We can be see that these transistors have the same drain current but the source-gate voltage of M3 is less
than the source-gate voltage of M4 when its turned on (when the gate is grounded) because of the M3
source-drain voltage drop.
Lets observe the output I=f(V) curve for these transistors and draw a horizontal line representing
the drain current (fig. 2.4):
6

Fig. 2.4 IV curve  =f( )

We can see that for the same M3 and M4 transistor dimensions, the voltage drop across the
transistor M4 is less than the voltage drop across M3, so the majority of the buffered voltage is delivered


to the output. So,  ratio of M4 should not be smaller than  ratio of M2. If this is much larger, then we
push M3 deeply into the triode region and therefore, increase nonlinearities in our transfer function.
There is a tradeoff, between voltage drop across switch M3 and linearity of the transfer function. So we
have decided to choose the same dimensions for both transistors.
Finally, regarding transistors M1 and M2which work as two switches, a similar rule was applied

to control the voltage drop across a switch (increase  ratio) but, we encountered certain problems.
Our design uses the 65 nm CMOS technology. When the dimensions of the channels are scaled
down, there is an inevitable increase in leakage currents. During simulations we realized that these
currents are so significant that the charge on the capacitor which should preserve the input voltage during
readout simply leaks out even though the M2 was turned off.

Therefore, we decided to minimize  ratio for these transistors.
In table 2.1 all dimensions are given:
Transistor
M1
M2
M3
M4
MCx

Channel length (L) [nm]


Channel width (W) [nm]
180
135
180
135
60
1000
60
1000
180
135
Table 2.1 Transistor dimensions

One of the biggest issues we encountered during the design of the analog part of the circuit is
related to the relatively small photodiode current at dark conditions which is approximately 200 pA. We
cannot neglect the transistors leakage currents because they are significant at this level. Therefore we
approached a solution for this problem in the following way.
At the input of the circuit, the photodiode was modeled as a current generator. Instead of directly
connecting a photodiode to the input of the circuit, we decided to put a PMOS current mirror like depicted
in the following figure:

Fig. 2.5 Modified circuit

Fig. 2.6 Magnified part with current mirror




By using a current mirror and tuning  ratios of the transistors we can achieve current gain, just to
raise the level of dark current. This amplification is not large andin our case it turned to be relatively

 
optimal for the ratio  =   1.5 . When we say optimal, we mean that the trade-off between


current amplification and leakage currents for these transistors is acceptable. It is important to note that
that we used the maximum length for the transistors for this technology in order to reduce leakage
currents.
Another issue was determining the capacitance of the sampling capacitor. If too little capacitance
was used (e.g. 1 pF), the charge will just leaks out through the NMOS transistor whose purpose is to erase
the signal. Again, to big capacitance is not suitable, not only because of the layout dimensions but also
because relatively small driving currents would not be able to use a full voltage swing at the input of the
source follower. For this reason in our design, we used a capacitor of 20 pF1.

Decision will be elaborated in the following text.

2.2. Simulation and design verification


For this part, we will examine the transfer function for the output circuit (source follower readout
switch and active load). It is desirable that the signal conditioning be as linear as possible for the
operating input voltages. Transistors which mostly influence this behavior are M3 and M4 and their
dimensions and reasons for choosing them were mentioned previously.
In the following figure this part of the circuit is analyzed using DC sweep analysis:

Fig. 2.7 Output part of the circuit

Fig. 2.8 Voltage transfer curve (W/L = 1000[nm]/60[nm])


As it can be seen from figure 2.8, the circuit shows linear behavior for a relatively wide range of
input voltages (from 200 mV to 750 mV) so we intend to operate in this region.
Just for illustration purposes, if we increase the width of the switch the benefits were not good
enough to waste valuable layout space:

Fig. 2.9 Voltage transfer curve (W/L = 1200[nm]/60[nm] switch, source follower unchanged)
The dimensions of the rest of transistors are given in table 2.1. Before elaborating the results of
simulations, an explanation of capacitor value is needed.
In dark conditions, the photodiode current is appx. 200 pA, which, at the output of current mirror,
gives I = 1.5*200 pA = 300 pA. Ideally, this current will charge the capacitor, so it can be written for
capacitor voltage:
#$ %&' =


&
()

In the project specifications it was mentioned that the maximum exposure time (which is needed
in this situation) was 30 milliseconds.As mentioned before, our intention is to keep the input voltage
below 700 mV to avoid non linaritesin the output circuit. So, for this boundary case, capacitance is easily
calculated:
() 

 +,-./)01,_3415 300 9 30 :

13 9<
3,)61,3
0.7 

Similarly, in case of bright conditions, (exposure time is now 2 ms2, output current from mirror
equals 2nA*2=1.5 = 3 nA):
() 

 +,-./)01,_=16>?@ 3 A 2:

9 9<
3,)61,3
0.7 

Of course, we will chose the greatest value which is ()  13 9<. Because of large leakage currents
and the fact that these were the calculations for upper bound of the input voltage, we increased the value
for the capacitor to 20 pF.This will also help in keeping the voltage level as constant as possible during
the readout phase.
The initial output voltage will be approximately 50-100 mV higher than input because of voltage
drops. The test circuit and the results of simulation are given on the following figures:

If user chooses long exposure times for bright conditions, there will be saturation and poor depth resolution.

10

Fig. 2.10 Test circuit

Fig. 2.11 Exposure (violet), erasure (green) signals and output voltages
in dark conditions for currents (0,100 and 200 pA; blue,red,yellow respectively)

Fig. 2.12 Exposure (violet), erasure (green) signals and output voltages
in bright conditions for currents (0,1 and 2 nA; cyan,brown,red respectively)
11

As it can be seen from simulations, our designed was verified, although there were some small
deviations from our calculations.

2.3.Layout, DRC and Layout vs Schematic analysis


In the following picture, the layout of the circuit is depicted:

Fig. 2.13 Layout of the pixel circuit (connections and some layers only)
If we look from left to right, we can notice two PMOS transistors of current mirror, then two
NMOS transistors (exposure and erasure) and finally, three PMOS transistors (source follower, readout
switch and active load). For interconnecting silicon poly to metal, vias were used. M1_NOD is N-well
contact connected to VDD and M1_POD is a bulk contact connected to ground.

Fig. 2.14 Layout of the pixel circuit (detailed view)


12

DRC analysis showed that all rules are satisfied:

Fig. 2.15 DRC results


Layout vs Schematic analysis also gave positive outcome:

Fig. 2.16 Layout vs schematic results


The next step was extraction of parasitic elements.

2.5. Post layout simulation


After successful extraction of parasitic, a comparison between modules based on schematic and
layout was carried out. Simulation included dark conditions (0 and 200 pA from photodiode) and bright
conditions (0 and 2nA). Exposure time was changed accordingly. Test circuit and results are depicted in
the following figures:

13

Fig. 2.17 Test circuit (module based on schematic up, and layout down)

Fig. 2.18 Output voltages in case of schematic (red) and layout (green)
based module for dark (0 pA green, 200pA red on the right) and bright conditions (0 nA green, 2nA red
on the left)
If we magnify, some differences can be spotted:

14

Fig. 2.19 Output voltages in case of schematic (red) and layout (green)- magnified, bright conditions
2 nA from photodiode

Fig. 2.20 Output voltages in case of schematic (red) and layout (green)- magnified, dark conditions
200 pA from photodiode
It is obvious that there are small differences between responses (cca 5 mV) of these two modules,
which were expected. Of course, extracted parasitics are not significant enough to influence the responses
more.

15

3.Digital design
As mentioned
oned before, digital part of the circuit consists of a mechanism which controls the
exposure time, initiates the exposure and finally converts the analog signal by activating ADC.
It is proposed in the project specification that this part of the project cconsist
onsist of three modules: state
machine, exposure time control circuit and timer which will indicate when exposure time has elapsed.
Proposal has been accepted and these modules are designed as follows.

3.1. State machine


In our design of a state machine
machine, we had two different approaches. The first
irst approach is, more or
less, straightforward, and the machine, based on task specifications, has three states as follows:
1. Idle state where the user sets exposure time
2. Exposure state
3. Readout state

The state diagram is shown in figure 3.1

Fig. 3.1 State diagram


For now, let us focus on Readout state. In order to decode system outputs (Nre1, Nre2, ADC)
during readout state, a binary counter
er and a combinational logic were used.
As it is possible to see from
rom time chart, Readout state lasts for 9 clock ticks. The corresponding
counter is, therefore, composed of 4 flip flops. It is a simple upward binary counter which counts from 0
until it reached 8. When the counter enters its first not allowed state 9, it resets the complete
compl machine and
itself.
The counter
ounter was designed using a structural description. We have already designed a D flip flop,
and considering the fact that basic building block of a counter is T flip flop3, first this instance was
created as follows:

Fig.
Fig.3.2 T flip flop using D flip flop
Connecting four of these units in a cascade, one can design an binary counter:
3

T flip flop (toggle flip flop) changes its state on every clock tick only if input T=1 .

16

Fig. 3.3 Binary counter with decoding logic


T flip flop T1 is the first in cascade and it is enabled by high logic level on its T input, provided by
input signal start. If reset is low, T1 will change its state on every clock tick. Its output is connected to
input of T flip flop T2, which will change its output with the frequency two times slower than T1. When
both T1 and T2 have high output, T3 will change it state on next clock tick etc. Logic OR gate were used
for resetting the counter when it enteredthe first not allowed state 9 (bin. 1001 i.e. when outputs of T4
and T1 become high, or when input signal reset is high). FSM_reset internal signal is generated using one
AND gate: <DEF,),@  G G .
Combinational logic is quite simple and is derived in the following way:
Q3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

Q2 Q1 Q0 Nre1 Nre2 ADC


0
0
0
1
1
0
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
1
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
0
0
1
1
0
0
0
1
X
X
X
0
1
0
X
X
X
0
1
1
X
X
X
1
0
0
X
X
X
1
0
1
X
X
X
1
1
0
X
X
X
1
1
1
X
X
X
Table 3.1 Combinational logic

Using Karnaugh maps, the following logic functions were obtained :


KKK KKKK
KKK G
KKK + G
KKKK
HIJ1 = G
G KKK
G + G G
 G
KKK
KKK
KKK
KKK
KKK
KKK
KKKK
HIJ2 = G G G + G G G + G G
KKKK
KKK
L( = G
 G G

The previous functions were implemented using NOR and OR gates because for simplicity.
The Verilog code for this logic is given in the appendix. The following figure represents the
combinational logic in RTL view generated using Quartus II software.
17

Fig.3.4 Combinational logic


A waveform of output signals, clock signal and counter state (c4-c1) are given in the next figure4:

Fig. 3.5 Waveforms of output signals, clock signal and counters state
Now let us consider the rest of the state machine design.
The state machine has three states, so two flip flops are needed. Its inputs are:
1. Ovf (exposure time has expired)
2. Rst (external reset signal)
3. Init (initialization)
, and its outputs are:
1. Exp (expose signal)
2. Ers (erase signal)
3. Nre1 (readout row 1)
4. Nre2 (readout row 2)
5. ADC (ADC enable)
The internal startsignal which enables previously described counter.
Based on task specifications and considering the state diagram on figure 3.1, the following
behavior can be derived:

Start signal is an internal signal, set logic high when machine enters Readout state.

18

Ovf Rst Init


0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1

D1
0
0
1
1
0
0
1
1

D0
0
1
0
1
0
1
0
1

Q1
0
0
1
0
0
0
1
0

Q0
0
1
0
0
1
1
0
0

1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
1
1
0
0
1
1
0

0
0
0
0
1
0
0
0

Table 3.2 (orange marks Idle -> Exposure transition,


while green Exposure -> Readout transition)
This is an example of a Mileys machine, because the next state depends both on current state and
input signals. These dependences can be described as (using Karnaugh map minimization):
KKKKKK KKKK
G KKK
G + M#N
G G
L  A& KKKK
L = M#N KKKK
G G + G KKK
G

Machines outputs are easily derived from states:

OP9 = G
OI = G G
&I& = G

Gate level implementation of the state machine with counter is given in the next figure:

19

Fig. 3.6
Next figure depicts the waveforms of importance during a typical operation:

Fig. 3.7
As mentioned before, there were two approaches to the design of state machine. The second
approach was focused on finding an optimal structure in terms of the number of logic gates.
Figure 3.8 illustrates our target output signals for the control circuit. The state machine receives
fourinputs; the clock, the initialize and reset signal, and the done signal from the exposure triggered by
the exposure
re counter. The state machine was expected to produce 5 outputs in their correct sequence.
Overall the state machine uses 11 states which must be encoded using at least 4 bits.

Fig. 3.8 Time chart


20

To make an efficient circuit we should minimize the number of logic gates used to encode the
states and the output signals. The encoding of each state affects the number of logic states of our circuit.
If we use brute force algorithms to find the optimal encoding we would have to search 16!/5! = 174
billion different combinations for 4 bits or 32!/21! = 5,150 trillion for 5 bit encoding.
To avoid brute force search, we searched for patterns in the outputs signals. We noticed that
different sets of states were similar. Since we are trying to minimize the logic gates, similar states should
be encoded as close as possible in order to simplify our Boolean functions.
It can be shown that the following sets of states shared similar output signals:
Table 3.3
Similar sets
(4, 5, 6) ~ (8, 9, 10)
(4) ~ (6)
(8) ~ (10)
(5) ~ (9)
(3) ~ (7) ~ (11)
(1) ~ (2)

Description
Interchange N1 and N2.
Same output.
Same output.
Interchange N1 and N2, trigger ADC.
Same output.
They do not share similarity with more than 2 other states.

From the similarity table the following 4 bit state encoding is created:
Table 3.4
State
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11

Q3
0
0
0
1
1
1
0
1
1
1
0

Q2
0
0
1
0
0
0
1
1
1
1
1

Q1
0
1
0
0
1
0
1
0
1
0
0

Q0
X
X
0
0
X
1
X
0
X
1
1

The resulting logic for the state machine and output signals is the following.
Temporary variables:
Q KKK
QK
(
R( S = TKKKK
Q  Q W
(
KKKK
Q KKKK
Q
State machine:
Q
Q
\ KKK KKK
`
KKK
KKK
C %G + G ' + G %G A& + ( KKKKKKK
LAJ'_
Q
[
X Y=
Q
[ Q %Q + Q ' + C Q + Q LAJ _
Q
KKKK + Q '
%Q  + Q  ' %Q
Z
^
Outputs:

21

KKK
( G
OIJ
\OP9J ` \ ( G `
_
[
_ [[KKK
_
=
G
+
G
H1


[
_ [
_
[ H2 _ [ KKKKKKKKKK
G G _
Z L( ^ Z G G ^



Figure 3.8 shows the diagram for this optimized state machine and in figure 3.9 the simulation for
the output signal for the control circuit.

Fig. 3.8 Gate level diagram

Fig. 3.9 Waveforms obtained through simulation

22

3.2. Timer
Next step was the implementation of aTimer module, whose purpose was to inform the state
machine that the exposure time has elapsed. This module was implemented as a 5-bit5 binary counter with
possibility of parallel writing to it. It starts by counting from a given value until it overflows.
This module has the following inputs:
1.
2.
3.
4.

Initial ( starting value ) (implemented as a bus)


Start ( counter enable signal )
Clock
Reset

And one output Ovf, which notifies the state machine about the end of the exposure phase.
Again, this module was implemented from gate level. For the purpose of parallel writing, at the
input of every D flip flop, there is a 2/1 multiplexer which decides, depending on the start input value,
whether the counter is loading or the normal counting procedure is in progress.
First, MUX 2/1 is implemented and in figure 3.10 the Quartus II netlist viewer provided the gate
level structure:

Fig. 3.10 MUX 2/1


After that, using structural description, modules (MUX, DFF and logic gates) are used to
implement the timer. The Verilog code for timer is given in appendix. Here is gate level structure of it
provided:

Fig. 3.11 Structure of the timer


It is easily seen the structure of T flip flop using XOR gate and D flip flop when start is logic
high.
Overflow signal is decoded simply as:

M#N  Ga G G G G

Simulation, where random numberswere first loaded and then the counting procedure started is
depicted in figure 3.12:

It is 5-bit because the maximum exposure time is 30 ms = 30 clockticks.

23

Fig. 3.12 Waveforms obtained through simulation

3.3.

Exposure time control circuit

The purpose of this module was to enable the user to tune the desired exposure time, providing
simple interface with two commands to exp_increase and exp_decrease.
This module has following inputs:
1.
2.
3.
4.

Exp_inc
Exp_dec
Clock
Reset

And one output Initial which is implemented as a bus.


Regarding the project specifications, exposure time is constrained to interval of time [2,30] ms.
Because the previously described timer counts from Initial value till overflow and the fact that clock
preiod is 1 ms, it can easily be seen that in order to obtain 2 ms period, Initial value should be (31-2=29)
and to obtain 30 ms period (31-30=1).
But, if we recall, both of our state machine designs change their state after ovf signal is set to
high. So, between overflow of the timer and change the state of the state machine there is one clock
period which should be calculated. Therefore, Initial takes values from interval [2,30].
When the system is reset, theInitial value is set to 2 (maximum exposure time).
Again, this module is implemented using structural description i.e. using already implemented
modules. To obtain the previously mentioned functionality, an up/down counter is selected. General
structure of this counter is given on next figure:

Fig. 3.13 Up/down counter (general structure)


It is clear that a down counter is nothing else but repeating structure of an up counter using only
inverted outputs of flip flops. Simple combinational logic shown in previous figure can do the work or 2/1
24

multiplexers can be used. We have chosen the first solution because of the smaller number of gates.
Counter will have 5 flip flops.
In order to make it possible to set some predefined values in case of system reset, a small change
in design of D flip flop is necessary. It is needed to add asynchronous set functionality. This is depicted in
next figure:

Fig. 3.14 D flip flop with asynh. set and reset


After applying these changes to Verilog code and simulating it in Quartus II software, a netlist
was obtained:

Fig. 3.15 D flip flop with asynh. set and reset gate level
Afterwards, another module, T flip flop, with asynchronous set is implemented:

Fig. 3.16 T flip flop


The next issue was related to the question: How to stop the counter when boundary values are
reached?. It was decided to use some sort of clock gating which would stop distribution of clock to flip
flops when certain conditions are met. These conditions are:
1. Counter reaches value of 30 (minimum exposure time) and user wants to decrease it more
25

2. Counter reaches value of 2 (maximum exposure time) and user wants to increase it more
3. No inputs are active
So, when any of these conditions is met, clock should not propagate to flip flops. It is easily
solved by next combinational logic:
KKKKKKKKKKKKKKKKKKKKKKKKKKK
KKKKexp _nc %Ga + G + G + Q
KKKK + G + exp
bc  G
KKKKKKKKKKK'
_nc %exp _inc + exp _dec' clk_in
a G G G Q  KKKKKKKKKKK

where clk_in is input clock, and clk is distributed to flip flops.

The only thing left is an edge detector on inputs, because it is expected when the user presses a
button, it increments or decrements the value of the counter only for one unit (not during the pressure).
Simple edge detector is depicted in next figure and it gives high logic level on output in duration of one
clock period for every positive edge on input:

Fig. 3.17 Edge detector


Next picture contains waveforms obtained from Active HDL simulator:

Fig. 3.18 Waveforms obtained through simulation (edge detector)


After implementing the module, netlist viewer provided following structure:

Fig. 3.19 Exposure time control circuit


or magnified:

26

Fig. 3.20 Input section

Fig. 3.21 Clock gating


Simulation verified design and results are given in next figure:

Fig. 3.22 Waveforms obtained through simulation (exposure time control circuit)
27

One can easily see that counter is sensitive on positive edge only and that is not possible to
decrement counter value more than minimum (upper part of figure) nor increment it more than maximum
value (lower part of figure).

3.4.

Complete design

The only thing left is to connect previously designed modules. This is done using structural
description in Verilog code (detailed in appendix):
state_machine FSM( clk,init ,rst ,expose ,erase ,start ,ovf,nre1,nre2,adc );
exp_time_control_circuit UD( clk ,rst , Initial, exp_increase,exp_decrease);
timer_counter TMR( Initial ,expose ,clk ,rst ,ovf );
Netlist viewer provided following structure:

Fig. 3.23 Complete design (modules)


And finally, AHDL simulator verified design:

Fig. 3.24 Waveforms obtained through simulation

Just to clarify, the clock frequency used for simulation was 20 MHz (so the clock period is 50 ns).
First, the exposure time is 30 (1500/50=30) clock ticks (30 ms in reality), after that the exposure time is
decreased for 2 clock ticks (1400/50=28 -> 28 ms).
In the figure below, there is a situation with minimum exposure time:

28

Fig. 3.24 Waveforms obtained through simulation

29

4. Conclusion and feedback


Our design for the 4 pixel camera IC compatible with 65nm technology was successful. We were
able to create good analog components and design efficient digital circuits. To complete this project we
used divide and conquer in order to break the problem into more manageable tasks. Furthermore, for the
digital control circuit section we came up with two different designs so we had the possibility to choose
the best design based on our desired criteria. (The criterion that we chose was the minimization of the
number of logic gates)
Despite relatively high leakage currents inherit to 65nm process, we were able to extract the signal
for each pixel. A good quality of our design is the output voltage linear gain with respect to the sensors
current for a given exposure time. Although Digital to Analog Conversion was beyond the scope of this
project, we suggest using additional dummy pixels (dark pixels) to subtract any offset the signal may have
in order to achieve high color depth.
We think that this project gave us the foundations to design our own IC. We learned how to use
software tools such as Cadence and Verilog and we had the opportunity to design this four pixel camera
from scratch. We are very satisfied with the results and we are hoping to use this valuable knowledge in
the near future.

30

5. APPENDIX
1. D flip flop
//----------------------------------------------------------------------------// Title
: dff
// Design : Student project
// Author : Daniel Salazar & Filip Savic
// Company : NTNU
//----------------------------------------------------------------------------`timescale 1 ns / 1 ps
module dff ( reset, clk ,d ,q ,q_bar );
output q ;
output q_bar ;
input clk, reset = 1;
input d ;
wire w1,w2,s,r;
nand G1(w2,w1,s);
nand G2(s,w2,clk,reset);
nand G3(r,s,clk,w1);
nand G4(w1,d,r,reset);
nand G5(q,s,q_bar);
nand G6(q_bar,q,r,reset);
endmodule

2. T flip flop
//----------------------------------------------------------------------------// Title
: tff
// Design : Student project
// Author : Daniel Salazar & Filip Savic
// Company : NTNU
//----------------------------------------------------------------------------`timescale 1 ns / 1 ps
module tff ( t ,rst ,clk ,q ,q_bar );
output q;
output q_bar ;
input t ;
input rst ;
input clk ;
wire w;
xor(w,q,t);
dff G(rst,clk,w,q,q_bar);
endmodule

31

3. D flip flop with asynchrounous set/reset

//----------------------------------------------------------------------------// Title
: dff_set_reset
// Design : Student project
// Author : Daniel Salazar & Filip Savic
// Company : NTNU
//----------------------------------------------------------------------------`timescale 1 ns / 1 ps
module dff_set_reset ( reset ,set ,d ,clk ,q ,q_bar );
output q ;
output q_bar ;
input reset ;
input set ;
input d ;
input clk ;
nand G1(w2,w1,s,set);
nand G2(s,w2,clk,reset);
nand G3(r,s,clk,w1);
nand G4(w1,d,r,reset);
nand G5(q,s,q_bar,set);
nand G6(q_bar,q,r,reset);
endmodule

4. T flip flop with asynchrounous set/reset


// Title
: tff_set_reset
// Design : full_adder
// Author : Daniel Salazar & Filip Savic
// Company : NTNU
`timescale 1 ns / 1 ps
module tff_set_reset ( t ,reset ,set, clk ,q ,q_bar );
output q ;
wire q ;
output q_bar ;
wire q_bar ;
input t ;
wire t ;
input clk ;
wire clk ;

32

input reset ;
wire reset ;
input set ;
wire set ;
xor(w,q,t);
dff_set_reset G(reset,set,w,clk,q,q_bar);
endmodule

5. Logic for decoding outputs of state machine (design approach #1)


//----------------------------------------------------------------------------// Title
: logic
// Design : Student project
// Author : Daniel Salazar & Filip Savic
// Company : NTNU
//----------------------------------------------------------------------------`timescale 1 ns / 1 ps
module logic ( q0 ,q1 ,q2 ,q3 ,nre1 ,nre2 ,adc ,q0_bar,q1_bar,q2_bar,q3_bar);
output nre1 ;
wire nre1 ;
output nre2 ;
wire nre2 ;
output adc ;
wire adc ;
input q0 ;
wire q0 ;
input q1 ;
wire q1 ;
input q2 ;
wire q2 ;
input q3 ;
wire q3 ;
input q0_bar,q1_bar,q2_bar,q3_bar;
wire w1,w2,w3,w4,w5,w6,w7,w8;
nor(w3,q2,q1,q0);
nor(w4,q3_bar,q2,q1);
nor(w5,q3,q2_bar);
or(nre1,w3,w4,w5);
nor(w6,q3,q1,q0);
nor(w7,q3,q2);
or(nre2,w6,w7,w3);
nor(adc,q3,q1_bar,q0);
endmodule

33

6. Counter for readout phase (design approach #1)


//----------------------------------------------------------------------------// Title
: counter
// Design : Student project
// Author : Daniel Salazar & Filip Savic
// Company : NTNU
//----------------------------------------------------------------------------`timescale 1 ns / 1 ps
module counter ( clk ,rst ,q0 ,q1 ,q2 ,q3, fsm_rst,nre1,nre2,adc,start);
output q0 ;
wire q0 ;
output q1 ;
wire q1 ;
output q2 ;
wire q2 ;
output q3 ;
wire q3 ;
output fsm_rst,nre1,nre2,adc;
input clk ;
input start;
wire clk ;
input rst ;
wire rst ;
supply1 vdd;
wire w1,w2,w3,w4,w5;
wire q0_bar,q1_bar,q2_bar,q3_bar;
and(w5,q0,q3);
not(w2,rst);
nor(w1,w2,w5);
and(w3,q0,q1);
and(w4,w3,q2);
tff T1(start,w1,clk,q0,q0_bar);
tff T2(q0,w1,clk,q1,q1_bar);
tff T3(w3,w1,clk,q2,q2_bar);
tff T4(w4,w1,clk,q3,q3_bar);
and(fsm_rst,q0,q3);
logic L(q0,q1,q2,q3,nre1,nre2,adc,q0_bar,q1_bar,q2_bar,q3_bar);
endmodule

34

7. State machine (design approach #1)


//----------------------------------------------------------------------------// Title
: state_machine
// Design : Student project
// Author : Daniel Salazar & Filip Savic
// Company : NTNU
//----------------------------------------------------------------------------`timescale 1 ns / 1 ps
module state_machine ( clk,Init ,Rst ,exp ,ers ,start ,ovf,nre1,nre2,adc );
output exp ;
wire exp ;
output ers ;
wire ers ;
output start ;
wire start ;
output nre1,nre2,adc;
input Init ;
input clk;
wire Init ;
input Rst ;
wire Rst ;
wire FSM_rst ;
input ovf ;
wire ovf ;
wire w1,w2,w3,w4,w5,q0,q1,q0_bar,q1_bar,master_rst,d0,d1,ovf_not;
not(ovf_not,ovf);
nor(master_reset,FSM_rst,Rst);
dff D0(master_reset,clk,d0,q0,q0_bar);
dff D1(master_reset,clk,d1,q1,q1_bar);
and(w1,ovf,q1_bar,q0);
and(w2,q1,q0_bar);
or(d1,w1,w2);
and(w3,Init,q0_bar,q1_bar);
and(w4,ovf_not,q1_bar,q0);
or(d0,w3,w4);
assign exp = q0;
assign start = q1;
xnor(ers,q0,q1);
wire c1,c2,c3,c4;
counter C1(clk,master_reset,c1,c2,c3,c4,FSM_rst,nre1,nre2,adc,start);
not (d1_not,d1);
endmodule

35

8. State machine (design approach #2 no necessity for readout counter)


//----------------------------------------------------------------------------// Title
: daniel_machine
// Design : Student project
// Author : Daniel Salazar & Filip Savic
// Company : NTNU
//--------------------------------------------------------------------------`timescale 1 ns / 1 ps
module daniel_machine ( reset1 ,init ,done ,n1 ,n2 ,adc ,erase ,expose ,clk );
output n1 ;
wire n1 ;
output n2 ;
wire n2 ;
output adc ;
wire adc ;
output erase ;
wire erase ;
output expose ;
wire expose ;
input reset1 ;
wire reset1 ;
input init ;
wire init ;
input done ;
wire done ;
input clk ;
wire clk ;
wire d0,d1,d2,d3,c0,c1,c2,q0,q0_bar,q1,q1_bar,q2,q2_bar,q3,q3_bar,not_done;
wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12;
not (reset,reset1);
and G1(c0,q3,q1_bar);
and G2(c1,q3_bar,q1);
nor G3(c2,q2,q3);
////////////////////////
// A0
assign d0 = q3;
////////////////////////
///////////////////////
// A1 first term
nand G4(w1,q2,q0);
and G5(w2,c0,w1);
// A1 second term
and G6(w3,q1_bar,init);
not (not_done,done);
and G7(w4,c1,not_done);
or G8(w5,w3,w4);
and G9(w6,q2_bar,w5);
// A1 together
or G10(d1,w6,w2);
////////////////////////

36

////////////////////////
// A2
and G11(w7,q3,q2);
and G12(w8,c0,q0);
and G13(w9,q2,q1);
and G14(w10,c1,done);
or(d2,w7,w8,w9,w10);
////////////////////////

////////////////////////
// A3
or G15(w11,q2,q3);
or G16(w12,q0_bar,q1);
and G17(d3,w11,w12);
////////////////////////
//module dff ( reset, clk ,d ,q ,q_bar );
dff D0(reset,clk,d0,q0,q0_bar);
dff D1(reset,clk,d1,q1,q1_bar);
dff D2(reset,clk,d2,q2,q2_bar);
dff D3(reset,clk,d3,q3,q3_bar);

////////////////////////
// decoding logic
and G18(erase,q1_bar,c2);
and G19(expose,q1,c2);
nand G20(n1,q3,q2_bar);
nand G21(n2,q3,q2);
and G22(adc,q3,q1);
////////////////////////
endmodule

37

9. Exposure timer
//----------------------------------------------------------------------------// Title
: timer_counter
// Design : Student project
// Author : Daniel Salazar & Filip Savic
// Company : NTNU
//--------------------------------------------------------------------------`timescale 1 ns / 1 ps
module timer_counter ( Initial ,start ,clk_in ,rst1 ,ovf );
output ovf ;
wire ovf ;
input [4:0]Initial;
input start ;
wire start ;
input clk_in ;
wire clk_in ;
input rst1 ;
wire rst ;
wire q0,q1,q2,q3,q4,q0_bar,q4_bar,q1_bar,q2_bar,q3_bar;
wire dff0,dff1,dff2,dff3,dff4;
supply1 vdd;
wire not_ovf;
not (not_ovf,ovf);
not (rst,rst1);
and (clk,clk_in,1);
xor(w1,q0,vdd);
mux2_1 M0(Initial[0],w1,start,dff0);
xor(w2,q0,q1);
mux2_1 M1(Initial[1],w2,start,dff1);
and (w3,q0,q1);
xor (w4,w3,q2);
mux2_1 M2(Initial[2],w4,start,dff2);
and (w5,w3,q2);
xor (w6,w5,q3);
mux2_1 M3(Initial[3],w6,start,dff3);
and (w7,w5,q3);
xor (w8,w7,q4);
mux2_1 M4(Initial[4],w8,start,dff4);
dff D0(rst,clk,dff0,q0,q0_bar);
dff D1(rst,clk,dff1,q1,q1_bar);
dff D2(rst,clk,dff2,q2,q2_bar);
dff D3(rst,clk,dff3,q3,q3_bar);
dff D4(rst,clk,dff4,q4,q4_bar);
and(ovf,q0,q1,q2,q3,q4);
endmodule

38

10. Exposure time control circuit


//----------------------------------------------------------------------------// Title
: exp_time_control_circuit
// Design : Student project
// Author : Daniel Salazar & Filip Savic
// Company : NTNU
//--------------------------------------------------------------------------`timescale 1 ns / 1 ps
module exp_time_control_circuit ( clk_in ,reset ,Initial ,EXP_inc ,EXP_dec );
output [4:0]Initial ;
input clk_in ;
wire clk_in ;
input reset ;
wire reset ;
input EXP_inc ;
wire EXP_inc ;
input EXP_dec ;
wire EXP_dec ;
wire q0_bar,q1_bar,q2_bar,q3_bar,q4_bar;
supply1 vdd;
wire exp_dec,exp_inc;
not(rst,reset);
button B1(clk_in,EXP_inc,exp_inc,rst);
button B2(clk_in,EXP_dec,exp_dec,rst);
tff_set_reset T1(vdd,rst,vdd,clk,Initial[0],q0_bar);

//setting Q0

not (exp_dec_b,exp_dec);
not (exp_inc_b,exp_inc);
and G1(w2,exp_inc_b,Initial[0]);
and G2(w3,exp_inc,q0_bar);
or
G3(w4,w2,w3);
tff_set_reset T2(w4,vdd,rst,clk,Initial[1],q1_bar);
and G4(w5,w2,Initial[1]);
and G5(w6,w3,q1_bar);
or G6(w7,w5,w6);
tff_set_reset T3(w7,rst,vdd,clk,Initial[2],q2_bar);
and G7(w8,w5,Initial[2]);
and G8(w9,w6,q2_bar);
or G9(w10,w8,w9);
tff_set_reset T4(w10,rst,vdd,clk,Initial[3],q3_bar);
and G10(w11,w8,Initial[3]);
and G11(w12,w9,q3_bar);
or G12(w13,w11,w12);
tff_set_reset T5(w13,rst,vdd,clk,Initial[4],q4_bar);
nand (w15,Initial[4],Initial[3],Initial[2],q0_bar,Initial[1],exp_inc_b);
or (w16,Initial[4],Initial[3],Initial[2],q1_bar,Initial[0],exp_inc_b);
or (w17,exp_inc,exp_dec);
and(clk,w15,w16,w17,clk_in);
endmodule

39

11. Complete design (approach #1)

//----------------------------------------------------------------------------// Title
: complete0
// Design : Student project
// Author : Daniel Salazar & Filip Savic
// Company : NTNU
//--------------------------------------------------------------------------`timescale 1 ns / 1 ps
module complete0 ( exp_increase,exp_decrease,clk ,rst ,init ,nre1 ,nre2 ,adc ,expose ,erase );
output nre1 ;
wire nre1 ;
output nre2 ;
wire nre2 ;
output adc ;
wire adc ;
output expose ;
wire expose ;
output erase ;
wire erase ;
wire [4:0]Initial ;
input exp_increase ;
input exp_decrease ;
input clk ;
wire clk ;
input rst ;
wire rst ;
input init ;
wire init ;
wire ovf;
state_machine FSM( clk,init ,rst ,expose ,erase ,start ,ovf,nre1,nre2,adc );
exp_time_control_circuit UD( clk ,rst , Initial, exp_increase,exp_decrease);
timer_counter TMR( Initial ,expose ,clk ,rst ,ovf ) ;
endmodule

40

12. Complete design (approach #2)

//----------------------------------------------------------------------------// Title
: complete_dani
// Design : Student project
// Author : Daniel Salazar & Filip Savic
// Company : NTNU
//--------------------------------------------------------------------------`timescale 1 ns / 1 ps
module complete_dani ( rst ,clk ,exp_inc ,exp_dec ,init ,nre1 ,nre2 ,adc ,expose ,erase );
output nre1 ;
wire nre1 ;
output nre2 ;
wire nre2 ;
output adc ;
wire adc ;
output expose ;
wire expose ;
output erase ;
wire erase ;
input rst ;
wire rst ;
input clk ;
wire clk ;
input exp_inc ;
wire exp_inc ;
input exp_dec ;
wire exp_dec ;
input init ;
wire init ;
wire [4:0]Initial ;
daniel_machine DM(rst,init,done,nre1,nre2,adc,erase,expose,clk);
exp_time_control_circuit EXP( clk ,rst , Initial, exp_inc,exp_dec);
timer_counter TMR( Initial ,expose ,clk ,rst ,done )
;
endmodule

41