ASIC-System on Chip-VLSI Design: Issues with Mu...

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Issues with Multi Height Cell Placement in Multi Vt Flow

Creating the reference libraries
There are two reference libraries required. One is low Vt cell library and another is high Vt cell library. These
libraries have two different height cells. Reference libraries are created as per the standard synopsys flow.
Library creation flow is given in Figure 1. Read_lib command is used for this purpose. As TF and LEF files are
available TF+LEF option is chosen for library creation. After the completion of the physical library preparation
steps, logical libraries are prepared.

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Figure 1 Library preparation command window

Backend (Physical Design) Interview Questions

and Answers
Below are the sequence of questions asked for a
physical design engineer. In which field are you
interested? Answer to this question...

Different Unit Tile Creation

The unit tile height of lvt cells is 2.52 and hvt cells are 1.96 . Hence two separate unit tiles have to be
created and should be added in the technology file. Hvt reference library is created with the unit tile name unit
and lvt reference library is created with unit tile name lvt_unit. By default unit tile is defined in technology file
and the other unit tile lvt_unit is also added to the technology file.

Process-Voltage-Temperature
(PVT) Variations and Static Timing
Analysis
The major design challenges of
ASIC design consist of
microscopic issues and
macroscopic issues [1]. The microscopic issues
are ultra-high s...
What is the difference between FPGA and ASIC?
This question is very popular in VLSI fresher
interviews. It looks simple but a deeper insight
into the subject reveals the fact that the...

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ASIC-System on Chip-VLSI Design: Issues with Mu...

http://asic-soc.blogspot.in/2008/04/issues-with-mul...

Clock Gating
Clock tree consume more than 50
% of dynamic power. The
components of this power are: 1)
Power consumed by
combinatorial log...
Embedded System for Automatic
Washing Machine using Microchip
PIC18F Series Microcontroller
The design uses the PIC18F
series microcontroller. All the
control functionalities of the
system are built around this. Upgradeability is
th...
Clock Definitions
lock Definitions: Rising and falling
edge of the clock For a +ve edge
triggered design +ve (or rising)
edge is called ...

Figure 2. Tile height specifications in library preparation

Floor Planning

What is the difference between FPGA and

CPLD?
FPGA-Field Programmable Gate Array and
CPLD-Complex Programmable Logic Device-both are programmable logic devices made by
the same compani...

70% of the core utilization is provided. Aspect ratio is kept at 1. Rows are flipped, double backed and made
channel less. No Top Design Format (TDF) file is selected as default placement of the IO pins are considered.
Since we have multi height cells in the reference library separate placement rows have to be provided for two
different unit tiles. The core area is divided into two separate unit tile section providing larger area for Hvt unit
tile as shown in the Figure 3.

Setup and hold slack

13. Setup and hold slack Slack
Slack is defined as difference
between actual or achieved time
and the desired time for a timing
...
Temperature controller using
Microchip PIC16F877A
Microcontroller
In continuously monitoring the
surrounding temperature of
industrial applications
Temperature Monitoring Control System play v...
Verilog code for asynchronous FIFO
Verilog code for asynchronous FIFO is given
below. The module a_fifo5 should be used for
Modelsim (or any other HDL simulator)
simulation...

Figure 3. Different unit tile placement

First as per the default floor planning flow rows are constructed with unit tile. Later rows are deleted from the
part of the core area and new rows are inserted with the tile lvt_unit. Improper allotment of area can give rise
to congestion. Some iteration of trial and error experiments were conducted to find best suitable area for two
different unit tiles. The unit tile covers 44.36% of core area while lvt_unit 65.53% of the core area. PR
summary report of the design after the floor planning stage is provided below.

PR Summary:
Number of Module Cells: 70449
Number of Pins: 368936
Number of IO Pins: 298
Number of Nets: 70858
Average Pins Per Net (Signal): 3.20281
Chip Utilization:
Total Standard Cell Area: 559367.77
Core Size: width 949.76, height 947.80; area 900182.53
Chip Size: width 999.76, height 998.64; area 998400.33
Cell/Core Ratio: 62.1394%
Cell/Chip Ratio: 56.0264%
Number of Cell Rows: 392

Placement Issues with Different Tile Rows

Legal placement of the standard cells is automatically taken care by Astro tool as two separate placement area
is defined for multi heighten cells. Corresponding tile utilization summary is provided below.

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Issues with Multi
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ASIC-System on Chip-VLSI Design: Issues with Mu...

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PR Summary:
[Tile Utilization]
============================================================
unit 257792 114353 44.36%
lvt_unit 1071872 702425 65.53%
============================================================

But this method of placement generates unacceptable congestion around the junction area of two separate unit
tile sections. The congestion map is shown in Figure 4.

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Figure 4. Congestion

February 2008
(2)
January 2008 (3)

There are two congestion maps. One is related to the floor planning with aspect ratio 1 and core utilization of
70%. This shows horizontal congestion over the limited value of one all over the core area meaning that design
cant be routed at all. Hence core area has to be increased by specifying height and width. The other
congestion map is generated with the floor plan wherein core area is set to 950 m. Here we can observe
although congestion has reduced over the core area it is still a concern over the area wherein two different unit
tiles merge as marked by the circle. But design can be routable and can be carried to next stages of place and
route flow provided timing is met in subsequent implementation steps.

2007 (109)

There was an error in

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Tighter timing constraints and more interrelated connections of standard cells around the junction area of
different unit tiles have lead to more congestion. It is observed that increasing the area isn't a solution to
congestion. In addition to congestion, situation verses with the timing optimization effort by the tool. Timing
target is not able to meet. Optimization process inserts several buffers around the junction area and some of
them are placed illegally due to the lack of placement area.

Corresponding timing summary is provided below:

Timing/Optimization Information:
[TIMING]
Setup Hold Num Num
Type Slack Num Total Target Slack Num Trans MaxCap Time
========================================================
A.PRE -3.491 3293 -3353.9 0.100 10000.000 0 8461 426 00:02:26
A.IPO -0.487 928 -271.5 0.100 10000.000 0 1301 29 00:01:02
A.IPO -0.454 1383 -312.8 0.100 10000.000 0 1765 36 00:01:57
A.PPO -1.405 1607 -590.9 0.100 10000.000 0 2325 32 00:00:58
A.SETUP -1.405 1517 -466.4 0.100 -0.168 6550 2221 31 00:04:10
========================================================

Since the timing is not possible to meet design has to be abandoned from subsequent steps. Hence in a multi
vt design flow cell library with multi heights are not preferred.

References
[1] Astro, User Guide, Version X-2005.09, September 2005

Tags: Congestion, Multi Vt, Physical Design, Placement

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ASIC-System on Chip-VLSI Design: Issues with Mu...

http://asic-soc.blogspot.in/2008/04/issues-with-mul...

6 comments:
kiran May 5, 2008 at 6:01 PM
i hav gone through ur blog .. good collection of material.... done good job.. [:)]
Reply

Murali

May 10, 2008 at 9:02 AM

thanks a lot and enjoy !

Reply

shankar May 21, 2008 at 11:15 AM

Good & very informative collection in a glance :)
Reply

Anonymous September 21, 2008 at 4:50 AM

u r blog is very informative..I really really liked it...thanks for your efforts!!
Reply

manoz January 22, 2009 at 12:15 PM

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Reply

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