sdc constraints in detail

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sdc constraints in detail

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sdc constraints in detail

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20th October
2010,18:58

#1

chanducs24
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sdc constraints in detail

in a chip,NMOSCAP) or VCC(the highest voltage in
a...

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20th October 2010,18:58

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sdc
constraints
in
detail
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can
anyone
explain
me
about
SDC
constra
ints..w
hat it
contain
s? how
it
would
be
useful
in ascii
design
s?
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sdc constraints in detail

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21st October
2010,00:34

bala_EE
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#2

Re:
sdc
constraints
in
detail
Constr
aints in
general
can be
divided
into
two
categor
ies,
namely
,
Design
Rule
Constr
aints
and
Optimi
zations
Constr
aints.
Design
rule
constra
ints are
implicitl
y
defined
by the
vendor
of the
library
that is
being
used
for
synthe
sizing
the
design.
For
exampl
e,
transiti
on
time,
fanout

04/22/2014 11:12 AM

sdc constraints in detail

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http://www.edaboard.com/thread191042.html
load
and
cap.
The
optimiz
ation
constra
ints are
the
ones
that
are
given
by the
design
er. For
exampl
e,
clock
uncerta
inity,
latency
, input
delay,
output
delay,
etc.
For
more
details
refer
the
SDC
user
manual
.
Please
clarify
if my
post is
mislea
ding in
anyway
.

FvM (53), ro9ty (37), erikl (30), betwixt (28),

rahul.achates (25)

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Octobe
r 2010

04/22/2014 11:12 AM

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at
00:36.
Reaso
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precisio
n

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21st October
2010,04:17

chanducs24
Member level 2

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#3

Re:
sdc
constraints
in
detail
Hi
bala,
thank
u..its
good
one..i
underst
ood
chandr
a.

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5th February
2011,20:07

birdy123
Full Member level 3

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#4

Re:
sdc
constraints
in
detail
Hi
Chandr
a,
I am
comple
tly
agree
with

5 of 9

04/22/2014 11:12 AM

sdc constraints in detail

http://www.edaboard.com/thread191042.html
Bala.
For
SDC
details,
what it
contain
and
how
can
you
write
the
SDC ..
you
can
check
followin
g Blog:
VLSI
concep
ts:
Synops
ys
Design
Constr
aints
(SDC)
Basics
-Birdy

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5th February
2011,21:27

bala_EE
Junior Member level 3

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#5

Re:
sdc
constraints
in
detail
Like I
said
the
design
constra
ints are
mentio
ned by
the

04/22/2014 11:12 AM

sdc constraints in detail

http://www.edaboard.com/thread191042.html
library
vendor.
For
exampl
e, if the
library
file
contain
s three
types
of Wire
Load
Models
namely
small,
mediu
m and
large.
We
can
choose
from
the
three
and
specify
throug
h the
SDC
file that
we
would
like DC
to use
SMALL
or
MEDIU
M or
LARG
E Wire
Load
Model.
Thus
SDC
file is
used to
convey
the
design
intent.

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6th February
2011,01:57

icfbicfb
Newbie level 1

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Re:
sdc
constraints
in
detail
see
synops
ys
SDC
constra
ints
docum
ents ,
SDC is
original
synops
ys
format
, now
is open
format
,
accept
ed by
all
vendor
s,

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6th February
2011,05:05

phoenixpavan
Full Member level 4

8 of 9

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#7

Re:
sdc
constraints
in
detail
The
blog
gives
very
good
detail
of the
SDC

04/22/2014 11:12 AM

sdc constraints in detail

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file..nic
e one

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