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Application note
Getting started with the STM8S
Introduction
This application note complements the information in the STM8S datasheets by describing
the minimum hardware and software environment required to build an application around an
STM8S 8-bit microcontroller device. It is divided into the following sections:
Power supply
Clock management
This application note also contains detailed reference design schematics with descriptions
of the main components. In addition, some hardware recommendations are given.
April 2009
1/42
www.st.com
Contents
AN2752
Contents
1
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
2.2
2.3
Analog power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2
Analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1
4.2
Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3
External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Reset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1
5.2
2/42
RC circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1
6.2
Component position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.3
6.4
Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.5
Other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.6
6.7
User options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1
Components reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.2
Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Doc ID 14651 Rev 3
AN2752
Contents
7.3
8.2
10
Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SWIM overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.1.2
8.1.3
Hardware connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Emulator STice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.2.1
STice overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.2.2
8.2.3
9.2
Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.3
Firmware library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10.2
10.3
10.2.1
Project editing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.2.2
Online help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10.3.2
10.3.3
10.3.4
10.3.5
10.3.6
Follow up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
11
12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3/42
List of tables
AN2752
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
4/42
AN2752
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
External capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Typical layout of VDD/VSS pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Analog input interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
System clock distribution internal clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Reset management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
RC circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
LQFP 80-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Debug system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Hardware connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Connection description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
STice in emulation configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
In-circuit programming and debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
STM8 software toolchain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
STM8 firmware library examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
STVD open example workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
STVD MCU edit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
STM8 firmware library online help manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
STVD: Building the project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
STVD: Selecting the debug instrument. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Connecting the debug instrument to the STM8 evaluation board. . . . . . . . . . . . . . . . . . . . 36
STVD: Starting the debug session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
STVD: Run the software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
STM8 evaluation board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5/42
AN2752
6/42
Power supply
Clock management
Reset management
AN2752
Power supply
Power supply
2.1
One pair of pads VDD/VSS (3.3 V 0.3 V to 5 V 0.5 V) dedicated to the main regulator
ballast transistor supply.
Note:
Two pairs of pads dedicated for VDD_IO/VSS_IO (3.3 V 0.3 V to 5 V 0.5 V), which are
used to power only the I/Os. On 32-pin packages, only one pair is bonded.
For VDDIO/VSSIO next to VDD/VSS, it is recommended to connect these two pairs together
and to use only one decoupling capacitance. The purpose is to ensure good noise immunity
by reducing the connection length between both supplies and also between VDD/VDDIO and
the capacitor.
Figure 1.
Power supply
Analog
signal
VDDA
VSSA
Analog functions
VCAP
3.3V - 5V
VDD/VDDIO1
VSS/VSSIO1
CPU
RAM
Logic
VDDIO2
VSSIO2
OSCIN
Star connected
Note:
OSCOUT
VDDIO
VDDIO
IOs
VSSIO
VSSIO
XTAL
ai15330
The capacitors must be connected as close as possible to the device supplies (especially
VDD in case of dedicated ground plane).
Placing a crystal/resonator on OSCIN/OSCOUT is optional. The resonator must be
connected as close as possible to the OSCIN and OSCOUT pins. The loading capacitance
ground must be connected as close as possible to VSS.
7/42
Power supply
2.2
AN2752
Symbol
CEXT
Parameter
Conditions
Min
Max
Unit
470
1000
nF
1. Care should be taken when selecting the capacitor, due to its tolerance, as well as its dependency on
temperature, DC bias and frequency in addition to other factors.
Figure 2.
External capacitor
ESR
ESL
Where:
ESR is the equivalent series resistance
Rleak
2.3
Recommendations
All pins need to be properly connected to the power supplies. These connections, including
pads, tracks and vias should have the lowest possible impedance. This is typically achieved
with thick track widths and preferably dedicated power supply planes in multi-layer printed
circuit boards (PCBs).
In addition, each power supply pair should be decoupled with filtering ceramic capacitors (C)
at 100 nF with one chemical C (1..2 F) in parallel on the STM8S device. The ceramic
capacitors should be placed as close as possible to the appropriate pins, or below the
appropriate pins, on the opposite side of the PCB. Typical values are 10 nF to 100 nF, but
8/42
AN2752
Power supply
exact values depend on the application needs. Figure 3 shows the typical layout of such a
VDD/VSS pair.
Figure 3.
Via to VSS
Cap.
VDD
VSS
STM8
9/42
AN2752
3.1
Analog power
The ADC unit has an independent, analog supply reference voltage, isolated on input pin
VDDA, which allows the ADC to accept a very clean voltage source. This analog voltage
supply range is the same as the digital voltage supply range on pin VDD. An isolated analog
supply ground connection on pin VSSA provides further ADC supply isolation. Together, the
analog supply voltage and analog supply ground connection, offer a separate external
analog reference voltage input for the ADC unit on the VREF+ pin. This gives better accuracy
on low voltage input as follows:
3.2
VREF+ (input, analog reference positive): The higher/positive reference voltage for the
ADC should be between [250 mV, VDDA]. For more details about VREF+ values please
refer to the Root part number 2 datasheet. This input is bonded to VDDA in devices that
have no external VREF+ pin (packages with 48 pins or less).
VREF- (input, analog reference negative): The lower/negative reference voltage for the
ADC should be higher than VSSA. For more details about VREF- values please refer to
the Root part number 2 datasheet. This input is bonded to VSSA in devices that have no
external VREF- pin (packages with 48 pins or less).
Analog input
Root part number 2 devices have 16 analog input channels, which are converted by the
ADC one at a time, and each multiplexed with an I/O.
The analog input interface of the ADC is shown in Figure 4.
Figure 4.
VIN
VIN_EXT
REXT
CEXT
10/42
Inside ADC
SWSAMP
CSAMP
AN2752
where:
CEXT is the total external capacitance on the path of VIN to the macro pin. This includes
parasitic routing capacitance, pad and pin capacitance and external capacitance. To
ensure proper and accurate sampling the following equation must be satisfied
Equation 2:
3
( R SW + R EXT ) ( C SAMP + C EXT ) < ------ T S
10
where:
RSW = 30 kOhm
CSAMP = 3 pF
Equation 2 is specific for REXT and CEXT when designing an analog input interface for the
ADC.
Please refer to the Root part number 2 datasheet and/or the corresponding family reference
manual (RM0016) for more details.
11/42
Clock management
AN2752
Clock management
4.1
16 MHz/128 kHz
internal RC
CCO pin
Clock unit
OSCOUT
Prescaler
WDG/AWU
Timer
Clock distribution
lnternal clock
For more details please refer to the section on clock management in the datasheet
4.2
Internal clock
The RC oscillator has an internal capacitor (C) and an internal resistor ladder (R). STM8S
devices have two kinds of internal clock: a high speed internal clock (HSI) running at
16 MHz and a low speed internal clock (LSI) running at 128 kHz.
After reset, the CPU starts with the internal RC (HSI clock signal) divided by 8, i.e. 2 MHz.
4.3
External clock
STM8S devices can connect to an external crystal or an external oscillator.
Note:
When no external clock is used, OSCIN and OSCOUT can be used as general purpose
I/Os.
Figure 6 describes the external clock connections.
12/42
AN2752
Clock management
Figure 6.
Clock sources
Hardware configuration
STM8
External clock
OSCIN
OSCOUT
(I/O available)
External source
Frequency: 32 kHz 24 MHz
Comparator hysteresis: 0.1 * VDD
Caution: Without prescaler, a duty cycle of maximum 45/55% must be respected
STM8
Crystal/ceramic resonators
OSCIN
OSCOUT
Q1
CL1
CL2
Load capacitors
The values of the load capacitors CL1 and CL2 are heavily dependent on the crystal type and
frequency. The user can refer to the datasheet of the crystal manufacturer to select the
capacitances. For best oscillation stability CL1 and CL2 normally have the same value.
Typical values are in the range from below 20 pF up to 40 pF (cload: 10 20 pF). The
parasitic capacitance of the board layout also needs to be considered and typically adds a
few pF to the component values.
Recommendations
In the PCB layout all connections should be as short as possible. Any additional signals,
especially those that could interfere with the oscillator, should be locally separated from the
PCB area around the oscillation circuit using suitable shielding.
13/42
Reset control
AN2752
Reset control
5.1
Power-on reset (POR) and brown-out reset (BOR): During power-on, the POR keeps
the device under reset until the supply voltage (VDD and VDDIO) reach the voltage level
at which the BOR starts to function.
SWIM reset: An external device connected to the SWIM interface can request the
SWIM block to generate a microcontroller reset
Illegal opcode reset: If a code to be executed does not correspond to any opcode or
prebyte value, a reset is generated
Figure 7.
Reset management
Simplified functional I/O reset schematic
STM8
VDD_IO
External reset
RPU
Filter
NRST
System reset
14/42
IWDG/WWDG/software reset
SWIM reset
EMS reset
POR/BOR reset
AN2752
Reset control
Output characteristics
A valid pulse on the pin is guaranteed with a 20 ns pulse duration on the internal
output buffer.
Figure 8.
Output characteristics
20 ns
Reset requested
Input characteristics
All train/burst spikes with a ratio of 1/10 must be filtered. This means that a negative
spike of up to 75 ns is always filtered, when a 7.5 ns interval between spikes occurs
(ratio 1/10).
All pulses with duration more than 450 ns are recognized as valid pulses
Figure 9.
Input characteristics
>7.5 ns
>7.5 ns
450 ns
<75 ns
<75 ns
Pad
<75 ns
>30 ns
Negative train of glitch filtered
5.2
Reset requested
System reset
15/42
Reset control
5.2.1
AN2752
RC circuit
The RC circuit concept is the simplest and most cost-effective external reset solution, where
the supply waveform is monotonous and the maximum rise time is known. The principle is to
let the RESET pin rise with the microcontroller supply voltage after a delay. The circuit is
shown in Figure 10.
The basic solution is to use an RC delay determined by the rise rate of the supply itself. The
component values must be chosen to create enough delay to keep the RESET pin below the
VIL specification until VCC reaches a safe operating voltage. Normally, a delay (time
constant) corresponding to at least 30 % of the total rise time is advised.
Figure 10. RC circuit
STM8
VDD_IO
RPU
NRSTIN
Push button
C1
100nF
The RC circuit scheme requires a certain delay between a power-down and the next powerup, because the delay generator has to be reinitialized. In practice, a pull-down capacitor
between RESET and VSS needs to be discharged.
16/42
AN2752
Recommendations
Recommendations
6.1
6.2
Component position
A preliminary layout of the PCB must separate the different circuits according to their
electromagnetic interference (EMI) contribution in order to reduce cross-coupling on the
PCB, i.e. noisy, high-current circuits, low voltage circuits, and digital components.
6.3
6.4
Decoupling
The standard decoupler for the external power is a 100 F pool capacitor. Supplementary
100 nF capacitors must be placed as close as possible to the VSS/VDD pins of the micro in
order to reduce the area of the current loop.
As a general rule, decoupling all sensitive or noisy signals improves electromagnetic compatibility (EMC) performances.
There are 2 types of decouplers:
Inductors. Although often ignored, ferrite beads, for example, are excellent inductors
due to their good dissipation of EMI energy and there is no loss of DC voltage (which is
not the case when simple resistors are used).
17/42
Recommendations
6.5
AN2752
Other signals
When designing an application, the following areas should be closely studied to improve
EMC performances:
In addition to:
6.6
6.7
User options
STM8S devices have user option features that can be used for remapping or
enabling/disabling an automatic reset or low speed watchdog. For more details please refer
to the product datasheet.
18/42
AN2752
Reference design
Reference design
7.1
Components reference
Table 2.
ID
Component list
Component name
Reference
Quantity
Comments
Refer to the Pinouts and pin description
and Package characteristics sections of
the Root part number 2 datasheet, to
choose the right package
Microcontroller
STM8S
Push button
Resistor
10 kOhm
Capacitor
100 nF
Capacitor
1 F
Decoupling capacitor
Capacitor
470 nF
Capacitor
20..40 pF
Crystal
1..24 MHz
SWIM connector
4 pins
19/42
Reference design
7.2
AN2752
Schematics
B1
C2
20 pF
100 nF
C3
C1
PA0
PA1
PA2
24M Hz
VCAP
20 pF
Clock(H SE )
R eset
X1
C4
470 nF
4
3
2
1
73
74
75
76
77
78
79
80
SW IM connector
Debug
VDD 2)
VDD 2)
VDD 2)
C6
100 nF
C7
100 nF
C8
100 nF
34
33
32
31
30
29
28
27
42
43
44
45
46
47
50
51
CN1
C5
100 nF
1
2
3
9
10
11
12
6
C9
1 F
8
49
7
23
5
24
4
48
U1
NRST
PE0/CLK_CCO
PA1/OSCIN
PE1/I 2C_SCL
PA2/OSCOUT
PE2/I 2C_SDA
PA3/TIM2_CH3[TIM3_CH1] PE3/TIM1_BKIN
PA4/UART1_RX
PE4
PA5/UART1_TX
PE5/SP I_NSS
PA6/UART1_CK
PE7/AIN8
VCAP
PE6/AIN9
PB0/AIN0[TIM1_CH1N]
PB1/AIN1[TIM1_CH2N]
PB2/AIN2[TIM1_CH3N]
PB3/AIN3[TIM1_ETR]
PB4/AIN4[I2C_SCL]
PB5/AIN5[I2C_SDA]
PB6/AIN6
PB7/AIN7
PC0/ADC_ ETR
PC1/TIM1_CH1
PC2/TIM1_CH2
PC3/TIM1_CH3
PC4/TIM1_CH4
PC5/SPI_SCK
PC6/SPI_MOSI
PC7/SPI_MI SO
PF0/AI N10
PF1/VREF PF2/VREF +
PF3/AI N11
PF4/AI N12
PF5/AI N13
PF6/AI N14
PF7/AI N15
PG0/CAN_TX
PG1/CAN_RX
PG2
PG3
PG4
PG5
PG6
PG7
PD0/TIM3_CH2[TIM1_BKIN][CLK_CCO] PH0
PD1/SWIM
PH1
PD2/TIM3_CH1[TIM2_CH3]
PH2
PD3/TIM2_CH2[ADC_ETR]
PH3
PD4/TIM2_CH1[BEE P]
PH4/TI M1_ETR
PD5/UART3_TX
PH5/TIM1_CH3N
PD6/UART3_RX
PH6/TIM1_CH2N
PD7/TL I[TIM1_CH4]
PH7/TIM1_CH1N
VDDIO_1
VDDI O_2
VDD
VDDA
VSS
VSSA
VSSIO_1
VSSIO_2
PI0
PI1
PI2
PI3
PI4
PI5
PI6
PI7
26
25 PF1
22 PF2
21
20
19
18
17
R1
R2
0
0
[ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a
duplication of the function).
1)
VDD 2)
52
53
54
55
56
63
64
65
13
14
15
16
35
36
37
38
57
58
59
60
61
62
71
72
MCU
Decoupling Capacitor
20/42
70
69
68
67
66
41
40
39
ai15471B
AN2752
Pinouts
STM8S devices have several package types, including the LQFP 80-pin pinout shown in
Figure 12. Please refer to the Root part number 2 datasheet for more details.
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PD7/TLI[TIM1_CH1]
PD6/UART3_RX
PD5/UART3_TX
PD4 (HS)/TIM2_CH1[BEEP]
PD3 (HS)/TIM2_CH2[ADC_ETR]
PD2 (HS)/TIM3_CH1[TIM2_CH3]
PD1 (HS)/SWIM
PD0(HS)/TIM3_CH2[TIM1_BKIN][CLK_CCO]
PI7
PI6
PE0/CLK_CCO
PE1/I2C_SCL
PE2/I 2C_SDA
PE3/TIM1_BKIN
PE4
PG7
PG6
PG5
PI5
PI4
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PI3
PI2
PI1
PI0
PG4
PG3
PG2
PG1/CAN_RX
PG0/CAN_TX
PC7/SPI_MISO
PC6/SPI_MOSI
VDDIO_2
VSSIO_2
PC5/SPI_SCK
PC4 (HS)/TIM1_CH4
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1
PC0/ADC_ETR
PE5/SPI_NSS
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
NRST
OSCIN/PA1
OSCOUT/PA2
VSSIO_1
VSS
VCAP
VDD
VDDIO_1
[TIM3_CH1]TIM2_CH3/PA3
UART1_RX/PA4
UART1_TX/PA5
UART1_CK/PA6
(HS) PH0
(HS) PH1
PH2
PH3
AIN15/PF7
AIN14/PF6
AIN13/PF5
AIN12/PF4
AIN11/PF3
VREF+
VDDA
VSSA
VREFAIN10/PF0
AIN7/PB7
AIN6/PB6
[I2C_SDA]AIN5/PB5
[I2C_SCL]AIN4/PB4
[TIM1_ETR]/AIN3/PB3
[TIM1_CH3N]AIN2/PB2
[TIM1_CH2N]AIN1/PB1
[TIM1_CH1N]AIN0/PB0
TIM1_ETR/PH4
TIM1_CH3N/PH5
TIM1_CH2N/PH6
TIM1_CH1N/PH7
AIN8/PE7
AIN9/PE6
7.3
Reference design
1.
2.
[ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a
duplication of the function).
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8.1
8.1.1
SWIM overview
In-circuit debugging mode or in-circuit programming mode are managed through a single
wire hardware interface based on an open-drain line, featuring ultra fast memory
programming. Coupled with an in-circuit debugging module, the SWIM also offers a nonintrusive read/write to RAM and peripherals. This makes the in-circuit debugger extremely
powerful and close in performance to a full-featured emulator.
The SWIM pin can be used as a standard I/O (with 8 mA capability) which has some
restrictions if the user wants to use it for debugging. The most secure way to use it is to
provide a strap option on the PCB. Please refer to the STM8 SWIM communication protocol
and debug module user manual (UM0470) for more SWIM protocol details.
Figure 13. Debug system block diagram
100 kHz Osc
Peripheral
SWIM entry
DBG
Comm CMD
layer decode
DM
STM8
core
RAM
NVM
Internal RC
8.1.2
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Pin name
Pin 1
VDD
Pin 2
SWIM pin
Pin 3
VSS
Pin 4
Reset
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8.1.3
Hardware connection
Figure 14. Hardware connection
AD/ICC SWIM adapter
Application board
SWIM connector
VDD
2
3
2
3
VDD
STM8
SWIM cable
Caution:
It is recommended to place the SWIM header as close as possible to the STM8S device, as
this minimizes any possible signal degradation caused by long PCB tracks.
8.2
Emulator STice
8.2.1
STice overview
The STice is a modular, high-end emulator system which connects to the PC via a USB
interface, and to the application board in place of the target microcontroller.
It is supported by the free STM8 toolset: IDE ST visual develop (STVD) programmer, ST
visual programmer (STVP) and STM8 assembler. Please refer to the STice emulator for
STM8 for more details.
Figure 15. Connection description
Emulation system
Connection flex
Connection adapter
Adapter socket
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Emulator box
Connection flex
Connection adapter
Adapter socket
8.2.2
Connection adapter: Links the connection flex to the footprint of the target
microcontroller on the users application board.
Adapter socket: Socket that solders to the application board in place of the
microcontroller and receives the connection adapter.
The above accessories are not included with the STice system. To determine exactly what
is required for any supported microcontroller, refer to the online product selector on
www.st.com.
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AD/xxxx: Connection
adapter to link connection
cable to microcontroller
8.2.3
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SWIM
connector
to microcontroller
(SWIM
protocol linked
for STM8,
or ICC protocol
for ST)
ST microcontroller on
application board
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In order to write, compile and run the first software on an STM8S device, the following components of the
software toolchain are required (see Figure 18):
Compiler
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9.1
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9.2
Compiler
STM8S devices can be programmed by a free assembler toolchain which is included in the
ST toolset.
As the core is designed for optimized high-level-language support, use of a C compiler is
recommended!
C compilers for STM8 are offered by the third party companies Cosmic and Raisonance.
A free version of the C compiler with up to 16 Kbytes of generated code is available at:
www.cosmic-software.com and www.raisonance.com.
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9.3
Firmware library
The STM8 firmware library is a complete set of source code examples for each STM8
peripheral. It is written in strict ANSI-C and it is fully MISRA C 2004 compliant (see
Figure 19).
All examples are delivered with workspace and project definition files for STVD and Cosmic
C compiler which enables the user to load and compile them easily into the development
environment.
The examples run on the STMicroelectronics STM8 evaluation board and can be tailored
easily to other types of hardware.
For additional information on the STM8 firmware library, please contact STMicroelectronics.
Figure 19. STM8 firmware library examples
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10
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10.1
C compiler
2.
ST toolset
3.
The Rlink does not need any dedicated software installation in the STM8 development
environment because the necessary drivers are delivered with the ST toolset.
Note:
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10.2
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10.2.1
Project editing
All project source files are visible and can be edited (see Figure 21).
Figure 21. STVD MCU edit mode
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10.2.2
Online help
An online help manual is available inside the firmware installation directory (see Figure 22)
to help the user understand the structure of the STM8 firmware library.
Figure 22. STM8 firmware library online help manual
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10.3
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10.3.1
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10.3.2
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10.3.3
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Rlink adapter
for STM8
Caution:
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On the Rlink ICC/SWIM adapter board, the SWIM jumper must be set.
If there is no pull-up on the application SWIM line, the ADAPT jumper is also set.
In any case, PW-5V and 12MHz jumpers must not be set.
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10.3.4
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10.3.5
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After entering debug mode, the software can be started by the run command in the menu Debug Run
(see Figure 27).
Figure 27. STVD: Run the software
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10.3.6
Follow up
Step by step, additional peripherals of STM8S devices can be run, following on from the
initial debug session described above.
Many features of STM8S devices are supported by dedicated hardware on the STM8
evaluation board. The necessary software drivers (CAN driver, LIN driver, buttons, memory
cards, buzzer, etc) are delivered in the STM8 firmware library.
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11
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Application
Tools
STM8 firmware library and release note (detailed descriptions of the library are
included as help files)
STM8 SWIM communication protocol and debug module user manual (UM0470)
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12
Revision history
Revision history
Table 4.
Date
Revision
Changes
03-Jun-2008
Initial release
01-Sep-2008
01-Apr-2009
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