ECE 321 PROJECT

Wednesday December 5, 2014

Abigail Jacoby
Matthew D. Scarborough
Telmo Diez

2-to-1 Multiplexer Design

Index

I. Project goals
II. List of Figures
III. List of Tables
IV. Design Requirements
V. L-edit Procedure
VI. L-Edit Layout and Design
VII. PSPICE Procedure
VIII. Results
IX. Interpretation and Conclusions
X. Work Distribution
XI. Background and References

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I.

Project Goals

In this project we are asked to design and layout a 2-to-1 Multiplexer.

Multiplexers are used as analog and digital switch. Plus they are key
components in CMOS data treatment and memory. In order to complete this
task, we have to put in practice our knowledge in L-edit and PSPICE to design
an optimum Multiplexer for power, area and delay. First of all, we are going to
explain the requirements for the project. Next, we are going to show the
work we did with L-edit, including schematics, layout and dimensions. Finally,
we are going to study the simulation we did in PSPICE and extract some
conclusions. The report will include figures, schematics, tables, a work
distribution table and a bibliography.

Figure 1: 2-to-1 Multiplexer Block Diagram

II. List of Figures

- Figure 1: 2-to-1 Multiplexer Block Diagram
-

Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure

2: 2-to-1 Multiplex transmission gates

3: SCMOS Layout Rule- Active
4: Designed 2-to-1 Multiplexer in L-Edit
5: CMOS process layers in layout tools
6: CMOS process layers in layout tools
7: VA1 Worst Case Switching Energy
8: VB Worst Case Switching Energy
9: VA2 Worst Case Switching Energy
10: VB Worst Case Switching Energy
11: tphl waveform
12: tplh waveform
13: VcapA waveform
14: VcapB waveform
15: VcapVS waveform

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Figure 16: V0RA waveform

Figure 17: V0RB waveform

III.
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List of Tables

Table 1: Layout area, measured switching energy, and measured delay.

Table 2: Cell Characterization Value

IV.

Design Requirements

The design of the required multiplexer has a series of requirements that we may
accomplish. In the bibliography we may find the reference of the model we used to
begin.

Figure 2: 2-to-1 Multiplex transmission gates

Then we had to design this model in L-edit. We have been provided with an L-edit
student version, design rules, layer definitions, an L-edit guide and a professor
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example. In order to design an optimum Multiplexer, we had to respect some design

rules that have been given to us. The rules are a standard 2um process from MOSIS
with 2 metal layers. Once we have finished designing our Mux, we had to create a
SPICE file to extract our design into PSPICE and perform a simulation. We used
PSPICE transistor model to define MOSFETs and added an input voltage and
command to perform the simulation. Plus we are supposed to provide a schematic
done in Power Point Schematic Template. Also, we may use a 5V power supply and a
100fF load capacitor in the output.

V.

L-edit procedure

Lets now take a look to the L-edit part. In this part we are looking to design an
optimum 2-to-1 Multiplexer for area, power and delay. The characteristics of a good
layout are the following. A good layout must be dense; cells have to pack up well
together. Next, we need a good performance which is done by keeping the
capacitances low and interconnects short. Also it must be reliable. This is given for
example by using a proper width in power rails. Finally we have to do final checks.
Layout has to matchup with the circuit being built, and the layout has to respect the
manufacturing design rules.
The design rule checking is one of the most important parts in the design because
we have to find the maximum density and performance respecting the design rules.
So finding the dimensions was a delicate job because it was finding the equilibrium
between the high density and low area and the design rules. Once we have the
dimensions figured out we can do the circuit in L-edit using the dimensions we
consider efficient. Below is an example of design rules that we have been provided:

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Figure 3: SCMOS Layout Rule- Active

So, in L-edit, with the model that we found online we designed the 2 to 1 MUX with
our knowledge, professor demo and the L-Edit help guide.

VI. L-Edit Layout and Design

Below we find our L-Edit final labeled design wit the area.

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Figure 4: Designed 2-to-1 Multiplexer in L-Edit

Density= 71.3884%

Figure 5: CMOS process layers in layout tools

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VII. PSPICE procedure

First of all we have to extract the PSPICE file from L-edit. Once the file is created,
using PSPICE transistor model, we are going to perform the simulations adding
commands and an input voltage.
In general, each exercise was performed by reading the instructions for what to type
into the PSPICE netlist, saving the file as a .cir file, importing the file into the
simulation editor by choosing the file dropdown menu and selecting the circuit file in
question. After, the simulation was run and any errors in the netlist were corrected,
and the output file was opened through the PSPICE program in the same window as
the netlist. To save each output file, the dropdown print command was selected, and
the file was printed to cutepdf.
In order to perform the simulations we did a series of things. First of all we put
pulses to the clock. Also we used static DC voltages. Then we tested our simulation
with between 0V and 5V.
Next, an appropriate transient analysis time was determined to run the simulation
so that an output graph could show the operation of the circuit in its entirety. Finally
the netlist was input into PSPICE as shown in figure 6:

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Figure 6: CMOS process layers in layout tools

We were also asked to the worst case switching energy. For the switching energy we
can obtain it by two ways:
Export the Current across C1 when it is switching on or off (whichever has the
t1

highest current change) with the integral E = Vdd*

I dd (t )dt
0

. I have set up the

graph so that the output is the capacitor voltage and the current across it, so the
current would need to be exported somehow probably into matlab and Im not sure
how to do that really.
The second method is to find the average current over the period T where the
current is switching, then multiply this by the time in the period, then finally
multiply this value by Vdd, this will also give the switching energy. (Vdd in our case
is A or B, both should have the same switching activity so I wouldnt bother
checking both).
We did a code to derive the worst case switching energy that will be included in the
project folder as simp.py. Also find attached a file called testdata.dat with all the
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times and the amperages obtained from the code. Please note I used a Simpson
integration instead of a Riemann integration so we should have slightly more
accuracy with our results.

Also, we wrote a code to integrate over 4.8ns to 8.8ns since our switching current
took a while to dissipate fully:
1. VA 0 ; VB 5

Figure 7: VA1 Worst Case Switching Energy

Figure 8: VB Worst Case Switching Energy

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2. VA 5 ; VB 0 (WORST CASE: VB@<5,0>)

Figure 9: VA2 Worst Case Switching Energy

Figure 10: VB Worst Case Switching Energy

The value boxed in red is the worst case switching energy.

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VIII. Results
In this section we are going to summarize our results of the PSPICE work.
First of all, below we may find all the waveforms, with its corresponding data, from
PSPICE simulation that shows the functionality of the multiplexer.

Figure 11: tphl waveform

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Figure 12: tplh waveform

Figure 12: VcapA waveform

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Figure 14: VcapB waveform

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Figure 15: VcapVS waveform

Figure 16: V0RA waveform

Figure 17: V0RB waveform

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Find below the measured delay, area and switching energy and also the cell
characterization table plus its corresponding calculations.
Measured Area

Measured Switching
Measured Delay
Energy
1090.421 m
2.616x10-12 pW
371.286 ps
Table 1: Layout area, measured switching energy, and measured delay.
Related Calculations

W =32.513 :

H= 33.538

W H= A

Cell
A (I0)
B (I1)
Vs (Sel)

Cin
Rout
71.3862 fF
NA
201.608 fF
NA
35.7623 fF
3940.14493
Table 2: Cell Characterization Value

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Related Calculations

T plh=0.69 C R (/ out)
CinA
492.547 ps=0.69 C10 k

492.547 ps
(0.69 10 k )

C 7.13862e-14 F
CinB
1.3911 ns=0.69 C 10 k

1.3911 ns
(0.69 10 k )

C 2.01608e-13

CinVs
246.760 ps=0.69 C 10 k

246.760 ps
(0.69 10 k )

C 3.57623e-14 F
Rout
2.7187 ns=0.69 1 pF Rout

Rout=

2.7187 ns
(0.69 1 pF)

Rout=3940.14493

IX. Interpretations and Conclusions

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Taking a look to our results, we may observe some strange spikes. This is due
because have a very high short circuit voltage leakage due to the transmission gate
style we have chosen. This is caused by voltage being fed back toward the input in
the system when the voltage is not quite high enough to overcome the feedback.
On our waveforms for both A and B high and Tc-q, we see peaks at each clock input
where this happens. Our gate style will have higher internal capacitance as
compared to a CMOS gate design, but the power dissipation should remain the
same. As for dynamic power dissipation, there should be some small reduction
overall in what is lost during logic.
Some other major issues with our gate style is the fact that we can not necessarily
isolate between inputs and outputs because they are tied together and source and
drain actively switch during logic. The output will also progressively become worse
with use due to circuit deterioration.
The benefit of our design is that we were able to minimize the number of transistors
required to create the correct logic. In doing this we were able to reduce our overall
area greatly and make a much more compact design.

X.

Work Distribution

Each member of the group spent about around 4 hours research 6 hours design and
edits, 4 hours in calculations, and 4h on paper writing.

XI. Background and References

Bibliography
-

Class Webpage and Lectures:

http://www.ece.unm.edu/~payman/classes/ECE321/index.html
Hawkins, Segura, Zarkesh-Ha. CMOS Digital Integrated Circuits: A First
Course. . Institution of Engineering & Technology, 2012
Sriteja Tarigopula, 2-to-1 MULTIPLEXOR USING L-EDIT.
www.cas.unt.edu/~sriteja/multiplexor.ppt
Wikipedia. Multiplexer. http://en.wikipedia.org/wiki/Multiplexer
Equipment

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L-Edit Win 64 15.02, the layout editor.

PSPICE: Allegro AMS simulator
ledit.tdb : design rules and layer definitions
template.ext : device definition
ledit_demo.tdb: Professor Example
L-Edit Quick Start Guide

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