TABLE OF CONTENTS

Page
LIST OF FIGURES......................................................................................................6
LIST OF TABLES........................................................................................................7
ABSTRACT..................................................................................................................8

CHAPTERS................................................................................................................10
1.

INTRODUCTION AND MOTIVATION...................................................10

2.

OVERVIEW OF SKYBRIDGE 3-D FABRIC...........................................14

2.1 Core Fabric Components and Elementary Circuits..................................15
2.1.1 Vertical Silicon Nanowires................................................................15
2.1.2 Vertical Gate-All-Around Transistor and NAND gate......................16
2.1.3 Elementary circuits built on vertical nanowires................................16
2.2 Challenges of Skybridge 3-D Fabric........................................................18
2.2.1 Limited Type of Gate Logic............................................................18
2.2.2 Complicated Control Clock...............................................................19
2.2.3 Large Overhead Due To Buffers........................................................19
2.3 Chapter Summary.....................................................................................19

3.

NP-DYNAMIC-SKYBRIDGE FABRIC OVERVIEW AND CORE

COMPONENTS...........................................................................................21
3.1 NP-Dynamic-Skybridge Fabric Overview...............................................21
3.2 Core Components of NP-Dynamic-Skybridge Fabric.............................21
3.2.1 Vertical Nanowires.............................................................................21
3.2.2 Vertical Gate-All-Around Transistor.................................................23
3.2.3 Coaxial Routing Structure..........................................................24
3.2.4 Ohmic contact and bridge..................................................................25
3.3 Chapter Summary.....................................................................................26

4.

ELEMENTARY CIRCUITS.......................................................................27

4.1 Logic Nanowire........................................................................................27

4.2 Compound Gate...................................................................................28
4.3 Cascaded Gates........................................................................................29
4.3 Chapter Summary.....................................................................................30
5.

BENCHMARKING AND RESULTS.........................................................31

5.1 Benchmarking Methodology....................................................................31
5.2 Benchmarking Results and Scalability.....................................................32
5.2.1 Benchmarking of 4-bit Carry Look-Ahead Adder.............................32
5.2.2 Results of Benchmarking...................................................................33
5.2.3 Scalability Study................................................................................34
5.3 Chapter Summary.....................................................................................35

6.

PROPOSED FUTURE WORK AND TIME LINE...................................36

6.1 GAA Junctionless Device Optimizations.................................................36
6.2 Fan-in Sensitivity Analysis......................................................................37
6.3 Reduction in Switching Activity..............................................................38
6.4 4-bit Microprocessor Benchmarking........................................................38
6.5 Time Line.................................................................................................39

BIBLIOGRAPHY......................................................................................................40

ABSTRACT
NP-DYNAMIC-SKYBRIDGE: A NEW NANOSCALE 3-D COMPUTING
FRAMEWORK WITH COMPLEMENTARY TRANSISTORS
JUNE 2014

B.Sc., UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF

CHINA, CHENG DU, CHINA
M.S.C.E., UNIVERSITY OF MASSACHUSETTS, AMHERST
Directed by: Professor Csaba Andras Moritz
With the scaling of technology nodes, modern CMOS architecture faces severe
challenges. Fundamentally, these challenges stem from device scaling limitations,
interconnection bottlenecks and increasing manufacturing complexities. These
challenges drive researchers to look for revolutionary technologies beyond the end of
CMOS roadmap. Instead of applying conventional 2-D circuits design concepts, a
new nanoscale 3-D computing framework for future integrated circuits, Skybridge,
has been proposed Error: Reference source not found. In this new fabric technology,
researchers co-architect its core aspects from device to circuits style, connectivity,
thermal management and manufacturing pathway to build a uniform 3-D template.
However, the Skybridge fabric uses only n-type transistors in a dynamic circuit style
for arbitrary logic implementations, which results in complex clocking schemes and
logic cascading. Moreover, logical expressions are limited to NAND or AND-ofNAND based implementations. Furthermore, for Skybridges large-scale circuits, the
dynamic circuit style used requires cascaded stages to be micro-pipelined, which
results in large number of buffers causing significant area overhead. In this work, we
propose an extension of original Skybridge fabric, called NP-Dynamic-Skybridge,
that uses both n-and p-type transistors in an innovative circuit style, and solves
Skybridges challenges.
In this new approach, wide variety of logic styles are supported, which allows
static-like circuit implementationsAs a result. Requirements for control clock are
also reduced to only one set of global precharge and evaluate clocks. Since, number of

pipeline stages are significantly reduced, buffer requirements are less compared to
Skybridge. These result in significant benefits in terms of area, power and
performance compared to Skybridge. Our benchmarking results show xxxx benefits.
\. Therefore, in terms of circuits key metrics, it achieves over 2x density benefits of
density over Skybridge 3-D fabrics dual-rail implementation and at least 45% powerdelay product improvement.