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Yi-Hsun Chiu
Yi-Feng Lo
Shun-Chung Wang
Yi-Hua Liu
Department of Electrical
Engineering, NTUST
Taipei, Taiwan, R.O.C
Department of Electrical
Engineering, NTUST
Taipei, Taiwan, R.O.C
D10007201@mail.ntust.edu.tw
D10107203@mail.ntust.edu.tw
Department of Electrical
Engineering, NTUST
Taipei, Taiwan, R.O.C
yhliu@mail.ntust.edu.tw
I.
II.
INTRODUCTION
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iLr and iLm are equal. Output current reaches zero. Both
output rectifier diodes D1 and D2 is reverse biased.
Transformer secondary voltage is lower than output voltage.
Output is separated from transformer. During this period,
since output is separated from primary, Lm is freed to
participate resonant. This mode ends when S1 is turned off.
(3) Mode 3 (t2 < t < t3)at t=t2, S1 is turned off. During
this mode, S1 and S2 are both off. The resonant current iLr
charges (discharges) the parasitic capacitance Coss1 ( Coss 2 ) of
the power switches. When the voltage across Coss1 equals Vin,
the body diode of S2 is turned on.
(4) Mode 4 (t3 < t < t4)The body diode of S2 is turned on
in previous mode, which creates a ZVS condition for S2. Gate
signal of S2 should be applied during this mode. When S2 is
turned on, iLr decreases and this will force secondary diode
D2 conduct and iout begin to increase. Also, from this moment,
transformer sees output voltage on the secondary side. Lm is
clamped with constant voltage V p = n Vout , so it doesnt
participate resonant during this period.
For next half cycle, the operation is same as analyzed
above and is omitted here.
IV.
805
T 1
y[n] = ak x[n k ]
(1)
k =0
806
EXPERIMENTAL RESULTS
(a) Vin=380 V
(VGS: 10 V/div, VDS: 200 V/div, Vp: 500 V/div, ir: 5 A/div, Time: 4 s/div)
(b) Vin=420 V
(VGS: 10 V/div, VDS: 200 V/div, Vp: 500 V/div, ir: 5 A/div, Time: 4 s/div)
807
96
95
(% )
94
93
92
91
90
1
380V
5
6
Output Current(A)
400V
10
ACKNOWLEDGMENT
420V
REFERENCES
[1]
CONCLUSION
808