Академический Документы
Профессиональный Документы
Культура Документы
Features
DDR3 SDRAM
MT41J256M4 32 Meg x 4 x 8 banks
MT41J128M8 16 Meg x 8 x 8 banks
MT41J64M16 8 Meg x 16 x 8 banks
Options1
Features
Marking
Configuration
256 Meg x 4
128 Meg x 8
64 Meg x 16
FBGA package (Pb-free) x4, x8
78-ball (8mm x 11.5mm) Rev. G
78-ball (8mm x 10.5mm) Rev. J
FBGA package (Pb-free) x16
96-ball (8mm x 14mm) Rev. G
96-ball (8mm x 14mm) Rev. J
Timing cycle time
938ps @ CL = 14 (DDR3-2133)
1.07ns @ CL = 13 (DDR3-1866)
1.25ns @ CL = 11 (DDR3-1600)
1.5ns @ CL = 9 (DDR3-1333)
1.87ns @ CL = 7 (DDR3-1066)
Operating temperature
Commercial (0C T C +95C)
Industrial (40C T C +95C)
Revision
Note:
256M4
128M8
64M16
JP
DA
JT
TW
-093
-107
-125
-15E
-187E
None
IT
:G / :J
Target tRCD-tRP-CL
-0931, 2, 3, 4
2133
14-14-14
13.09
13.09
13.09
-1071, 2, 3
1866
13-13-13
13.91
13.91
13.91
1, 2
tRCD
(ns)
tRP
(ns)
CL (ns)
1600
11-11-11
13.75
13.75
13.75
-15E 1
1333
9-9-9
13.5
13.5
13.5
-187E
1066
7-7-7
13.1
13.1
13.1
-125
Notes:
1.
2.
3.
4.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
Table 2: Addressing
Parameter
Configuration
256 Meg x 4
128 Meg x 8
64 Meg x 16
32 Meg x 4 x 8 banks
16 Meg x 8 x 8 banks
8 Meg x 16 x 8 banks
Refresh count
8K
8K
8K
Row addressing
16K (A[13:0])
16K (A[13:0])
8K (A[12:0])
Bank addressing
8 (BA[2:0])
8 (BA[2:0])
8 (BA[2:0])
2K (A[11, 9:0])
1K (A[9:0])
1K (A[9:0])
1KB
1KB
2KB
Column addressing
Page Size
Package
Speed
Revision
MT41J
:G / :J Revision
Temperature
Configuration
256 Meg x 4
256M4
Commercial
128 Meg x 8
128M8
Industrial temperature
64 Meg x 16
64M16
Package
Note:
Rev.
Mark
-093
Speed Grade
tCK = 0.098ns, CL = 14
JP
-107
tCK = 1.07ns, CL = 13
DA
-125
tCK = 1.25ns, CL = 11
JT
-15E
TW
-187E
tCK = 1.5ns, CL = 9
tCK = 1.87ns, CL = 7
None
IT
1. Not all options listed can be combined to define an offered product. Use the part catalog search on
http://www.micron.com for available offerings.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Contents
State Diagram ................................................................................................................................................ 11
Functional Description ................................................................................................................................... 12
Industrial Temperature ............................................................................................................................... 12
General Notes ............................................................................................................................................ 12
Functional Block Diagrams ............................................................................................................................. 14
Ball Assignments and Descriptions ................................................................................................................. 16
Package Dimensions ....................................................................................................................................... 22
Electrical Specifications .................................................................................................................................. 26
Absolute Ratings ......................................................................................................................................... 26
Input/Output Capacitance .......................................................................................................................... 27
Thermal Characteristics .................................................................................................................................. 28
Electrical Specifications I DD Specifications and Conditions ........................................................................... 30
Electrical Characteristics IDD Specifications .................................................................................................. 41
Electrical Specifications DC and AC .............................................................................................................. 44
DC Operating Conditions ........................................................................................................................... 44
Input Operating Conditions ........................................................................................................................ 44
AC Overshoot/Undershoot Specification ..................................................................................................... 48
Slew Rate Definitions for Single-Ended Input Signals ................................................................................... 51
Slew Rate Definitions for Differential Input Signals ...................................................................................... 53
ODT Characteristics ....................................................................................................................................... 54
ODT Resistors ............................................................................................................................................ 55
ODT Sensitivity .......................................................................................................................................... 56
ODT Timing Definitions ............................................................................................................................. 56
Output Driver Impedance ............................................................................................................................... 60
34 Ohm Output Driver Impedance .............................................................................................................. 61
34 Ohm Driver ............................................................................................................................................ 62
34 Ohm Output Driver Sensitivity ................................................................................................................ 63
Alternative 40 Ohm Driver .......................................................................................................................... 64
40 Ohm Output Driver Sensitivity ................................................................................................................ 64
Output Characteristics and Operating Conditions ............................................................................................ 66
Reference Output Load ............................................................................................................................... 68
Slew Rate Definitions for Single-Ended Output Signals ................................................................................. 69
Slew Rate Definitions for Differential Output Signals .................................................................................... 70
Speed Bin Tables ............................................................................................................................................ 71
Electrical Characteristics and AC Operating Conditions ................................................................................... 76
Command and Address Setup, Hold, and Derating ........................................................................................... 96
Data Setup, Hold, and Derating ...................................................................................................................... 104
Commands Truth Tables ............................................................................................................................. 113
Commands ................................................................................................................................................... 116
DESELECT ................................................................................................................................................ 116
NO OPERATION ........................................................................................................................................ 116
ZQ CALIBRATION LONG ........................................................................................................................... 116
ZQ CALIBRATION SHORT .......................................................................................................................... 116
ACTIVATE ................................................................................................................................................. 116
READ ........................................................................................................................................................ 116
WRITE ...................................................................................................................................................... 117
PRECHARGE ............................................................................................................................................. 118
REFRESH .................................................................................................................................................. 118
SELF REFRESH .......................................................................................................................................... 119
DLL Disable Mode ..................................................................................................................................... 120
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
List of Tables
Table 1: Key Timing Parameters ....................................................................................................................... 1
Table 2: Addressing ......................................................................................................................................... 2
Table 3: 78-Ball FBGA x4, x8 Ball Descriptions .............................................................................................. 18
Table 4: 96-Ball FBGA x16 Ball Descriptions ................................................................................................. 20
Table 5: Absolute Maximum Ratings .............................................................................................................. 26
Table 6: DDR3 Input/Output Capacitance ...................................................................................................... 27
Table 7: Thermal Characteristics .................................................................................................................... 28
Table 8: Timing Parameters Used for I DD Measurements Clock Units ............................................................ 30
Table 9: IDD0 Measurement Loop ................................................................................................................... 31
Table 10: IDD1 Measurement Loop .................................................................................................................. 32
Table 11: IDD Measurement Conditions for Power-Down Currents ................................................................... 33
Table 12: IDD2N and IDD3N Measurement Loop ................................................................................................ 34
Table 13: IDD2NT Measurement Loop .............................................................................................................. 34
Table 14: IDD4R Measurement Loop ................................................................................................................ 35
Table 15: IDD4W Measurement Loop ............................................................................................................... 36
Table 16: IDD5B Measurement Loop ................................................................................................................ 37
Table 17: IDD Measurement Conditions for IDD6, IDD6ET, and IDD8 .................................................................... 38
Table 18: IDD7 Measurement Loop .................................................................................................................. 39
Table 19: IDD Maximum Limits Rev. G .......................................................................................................... 41
Table 20: IDD Maximum Limits Rev. J ........................................................................................................... 42
Table 21: DC Electrical Characteristics and Operating Conditions ................................................................... 44
Table 22: DC Electrical Characteristics and Input Conditions .......................................................................... 44
Table 23: Input Switching Conditions ............................................................................................................. 45
Table 24: Differential Input Operating Conditions (CK, CK# and DQS, DQS#) .................................................. 46
Table 25: Control and Address Pins ................................................................................................................ 48
Table 26: Clock, Data, Strobe, and Mask Pins .................................................................................................. 48
Table 27: Allowed Time Before Ringback ( tDVAC) for CK - CK# and DQS - DQS# ............................................... 50
Table 28: Single-Ended Input Slew Rate Definition .......................................................................................... 51
Table 29: Differential Input Slew Rate Definition ............................................................................................. 53
Table 30: On-Die Termination DC Electrical Characteristics ............................................................................ 54
Table 31: RTT Effective Impedances ................................................................................................................ 55
Table 32: ODT Sensitivity Definition .............................................................................................................. 56
Table 33: ODT Temperature and Voltage Sensitivity ........................................................................................ 56
Table 34: ODT Timing Definitions .................................................................................................................. 57
Table 35: Reference Settings for ODT Timing Measurements ........................................................................... 57
Table 36: 34 Ohm Driver Impedance Characteristics ....................................................................................... 61
Table 37: 34 Ohm Driver Pull-Up and Pull-Down Impedance Calculations ....................................................... 62
Table 38: 34 Ohm Driver IOH/IOL Characteristics: V DD = V DDQ = 1.5V ................................................................ 62
Table 39: 34 Ohm Driver IOH/IOL Characteristics: V DD = V DDQ = 1.575V ............................................................. 62
Table 40: 34 Ohm Driver IOH/IOL Characteristics: V DD = V DDQ = 1.425V ............................................................. 63
Table 41: 34 Ohm Output Driver Sensitivity Definition .................................................................................... 63
Table 42: 34 Ohm Output Driver Voltage and Temperature Sensitivity .............................................................. 63
Table 43: 40 Ohm Driver Impedance Characteristics ....................................................................................... 64
Table 44: 40 Ohm Output Driver Sensitivity Definition .................................................................................... 64
Table 45: 40 Ohm Output Driver Voltage and Temperature Sensitivity .............................................................. 65
Table 46: Single-Ended Output Driver Characteristics ..................................................................................... 66
Table 47: Differential Output Driver Characteristics ........................................................................................ 67
Table 48: Single-Ended Output Slew Rate Definition ....................................................................................... 69
Table 49: Differential Output Slew Rate Definition .......................................................................................... 70
Table 50: DDR3-1066 Speed Bins ................................................................................................................... 71
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
List of Figures
Figure 1: DDR3 Part Numbers .......................................................................................................................... 2
Figure 2: Simplified State Diagram ................................................................................................................. 11
Figure 3: 256 Meg x 4 Functional Block Diagram ............................................................................................. 14
Figure 4: 128 Meg x 8 Functional Block Diagram ............................................................................................. 15
Figure 5: 64 Meg x 16 Functional Block Diagram ............................................................................................. 15
Figure 6: 78-Ball FBGA x4, x8 (Top View) ...................................................................................................... 16
Figure 7: 96-Ball FBGA x16 (Top View) ......................................................................................................... 17
Figure 8: 78-Ball FBGA x4, x8 (JP) ................................................................................................................ 22
Figure 9: 78-Ball FBGA x4, x8 (DA) ............................................................................................................... 23
Figure 10: 96-Ball FBGA x16 (JT) .................................................................................................................. 24
Figure 11: 96-Ball FBGA x16 (TW) ................................................................................................................ 25
Figure 12: Thermal Measurement Point ......................................................................................................... 29
Figure 13: Input Signal .................................................................................................................................. 47
Figure 14: Overshoot ..................................................................................................................................... 48
Figure 15: Undershoot ................................................................................................................................... 48
Figure 16: V IX for Differential Signals .............................................................................................................. 49
Figure 17: Single-Ended Requirements for Differential Signals ........................................................................ 49
Figure 18: Definition of Differential AC-Swing and tDVAC ............................................................................... 50
Figure 19: Nominal Slew Rate Definition for Single-Ended Input Signals .......................................................... 52
Figure 20: Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# .................................. 53
Figure 21: ODT Levels and I-V Characteristics ................................................................................................ 54
Figure 22: ODT Timing Reference Load .......................................................................................................... 57
Figure 23: tAON and tAOF Definitions ............................................................................................................ 58
Figure 24: tAONPD and tAOFPD Definitions ................................................................................................... 58
Figure 25: tADC Definition ............................................................................................................................. 59
Figure 26: Output Driver ................................................................................................................................ 60
Figure 27: DQ Output Signal .......................................................................................................................... 67
Figure 28: Differential Output Signal .............................................................................................................. 68
Figure 29: Reference Output Load for AC Timing and Output Slew Rate ........................................................... 68
Figure 30: Nominal Slew Rate Definition for Single-Ended Output Signals ....................................................... 69
Figure 31: Nominal Differential Output Slew Rate Definition for DQS, DQS# .................................................... 70
Figure 32: Nominal Slew Rate and tVAC for tIS (Command and Address Clock) ............................................. 100
Figure 33: Nominal Slew Rate for tIH (Command and Address Clock) ........................................................... 101
Figure 34: Tangent Line for tIS (Command and Address Clock) .................................................................... 102
Figure 35: Tangent Line for tIH (Command and Address Clock) .................................................................... 103
Figure 36: Nominal Slew Rate and tVAC for tDS (DQ Strobe) ......................................................................... 109
Figure 37: Nominal Slew Rate for tDH (DQ Strobe) ...................................................................................... 110
Figure 38: Tangent Line for tDS (DQ Strobe) ................................................................................................ 111
Figure 39: Tangent Line for tDH (DQ Strobe) ............................................................................................... 112
Figure 40: Refresh Mode ............................................................................................................................... 119
Figure 41: DLL Enable Mode to DLL Disable Mode ........................................................................................ 121
Figure 42: DLL Disable Mode to DLL Enable Mode ........................................................................................ 122
Figure 43: DLL Disable tDQSCK .................................................................................................................... 123
Figure 44: Change Frequency During Precharge Power-Down ........................................................................ 125
Figure 45: Write Leveling Concept ................................................................................................................. 126
Figure 46: Write Leveling Sequence ............................................................................................................... 129
Figure 47: Write Leveling Exit Procedure ....................................................................................................... 130
Figure 48: Initialization Sequence ................................................................................................................. 132
Figure 49: MRS to MRS Command Timing ( tMRD) ......................................................................................... 133
Figure 50: MRS to nonMRS Command Timing ( tMOD) .................................................................................. 134
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
10
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
State Diagram
Figure 2: Simplified State Diagram
CKE L
Power
applied
MRS, MPR,
write
leveling
Initialization
Reset
procedure
Power
on
Self
refresh
SRE
ZQCL
From any
state
RESET
ZQ
calibration
MRS
SRX
REF
ZQCL/ZQCS
Refreshing
Idle
PDE
ACT
PDX
Active
powerdown
Precharge
powerdown
Activating
PDX
CKE L
CKE L
PDE
Bank
active
WRITE
WRITE
READ
WRITE AP
Writing
READ
READ AP
READ
WRITE
WRITE AP
Reading
READ AP
WRITE AP
READ AP
PRE, PREA
Writing
PRE, PREA
PRE, PREA
Reading
Precharging
Automatic
sequence
Command
sequence
ACT = ACTIVATE
MPR = Multipurpose register
MRS = Mode register set
PDE = Power-down entry
PDX = Power-down exit
PRE = PRECHARGE
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Functional Description
DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation.
The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write
operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clockcycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, onehalf-clock-cycle data transfers at the I/O pins.
The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data
for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the
data strobes.
The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK
going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble.
Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVATE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with
the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE commands are used to select
the bank and the starting column location for the burst access.
The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
access.
As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM
allows for concurrent operation, thereby providing high bandwidth by hiding row precharge and activation time.
A self refresh mode is provided, along with a power-saving, power-down mode.
Industrial Temperature
The industrial temperature (IT) device requires that the case temperature not exceed
40C or 95C. JEDEC specifications require the refresh rate to double when T C exceeds
85C; this also requires use of the high-temperature self refresh option. Additionally,
ODT resistance and the input/output impedance must be derated when T C is < 0C or
>95C.
General Notes
The functionality and the timing specifications discussed in this data sheet are for the
DLL enable mode of operation (normal operation).
Throughout this data sheet, various figures and text refer to DQs as DQ. DQ is to be
interpreted as any and all DQ collectively, unless specifically stated otherwise.
The terms DQS and CK found throughout this data sheet are to be interpreted as
DQS, DQS# and CK, CK# respectively, unless specifically stated otherwise.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
12
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
13
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
ODT
ZQ
RZQ
ZQCL, ZQCS
CKE
VSSQ
To pull-up/pull-down
networks
ZQ CAL
RESET#
Control
logic
A12
CK, CK#
VDDQ/2
CS#
RAS#
CAS#
WE#
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
OTF
Mode registers
Refresh
counter
16
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
14
14
Bank 0
rowaddress
latch
and
decoder
16,384
RTT(WR)
CK, CK#
sw2
sw1
DLL
(1 . . . 4)
14
Rowaddress
MUX
RTT,nom
Columns 0, 1, and 2
Bank 0
memory
array
(16,384 x 256 x 32)
32
READ
FIFO
and
data
MUX
DQ[3:0]
READ
drivers
DQ[3:0]
DQS, DQS#
VDDQ/2
Sense amplifiers
32
BC4
RTT,nom
8,192
BC4
OTF
I/O gating
DM mask logic
3
A[13:0]
BA[2:0]
17
Address
register
sw1
(1, 2)
Bank
control
logic
Columnaddress
counter/
latch
DQS, DQS#
VDDQ/2
32
Data
interface
Column
decoder
4
Data
WRITE
drivers
and
input
logic
RTT,nom
sw1
RTT(WR)
sw2
DM
3
Columns 0, 1, and 2
CK, CK#
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
sw2
DM
256
(x32)
11
RTT(WR)
14
Column 2
(select upper or
lower nibble for BC4)
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
ODT
ZQ
RZQ
Control
logic
CKE
VSSQ
To ODT/output drivers
ZQ CAL
RESET#
ZQCL, ZQCS
A12
CK, CK#
VDDQ/2
Command
decode
CS#
RAS#
CAS#
WE#
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
OTF
Mode registers
Refresh
counter
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
16
14
14
Bank 0
rowaddress
16,384
latch
and
decoder
RTT(WR)
CK, CK#
sw2
sw1
DLL
(1 . . . 8)
14
Rowaddress
MUX
RTT,nom
Columns 0, 1, and 2
Bank 0
memory
array
(16,384 x 128 x 64)
64
DQ8
READ
FIFO
and
data
MUX
TDQS#
DQ[7:0]
READ
drivers
DQ[7:0]
DQS, DQS#
VDDQ/2
Sense amplifiers
64
BC4
8,192
17
Address
register
RTT(WR)
sw2
sw1
I/O gating
DM mask logic
A[13:0]
BA[2:0]
BC4
OTF
RTT,nom
(1, 2)
Bank
control
logic
VDDQ/2
(128
x64)
64
Data
interface
Column
decoder
Columnaddress
counter/
latch
10
DQS, DQS#
8
Data
WRITE
drivers
and
input
logic
RTT,nom
RTT(WR)
sw2
sw1
DM/TDQS
(shared pin)
3
Columns 0, 1, and 2
CK, CK#
Column 2
(select upper or
lower nibble for BC4)
ODT
ZQ
RZQ
ZQ CAL
RESET#
Control
logic
CKE
VSSQ
To ODT/output drivers
ZQCL, ZQCS
A12
VDDQ/2
CK, CK#
Command
decode
CS#
RAS#
CAS#
WE#
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
OTF
Mode registers
Refresh
counter
16
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
13
13
Bank 0
rowaddress
latch
and
decoder
8,192
DLL
(1 . . . 16)
Bank 0
memory
array
(8192 x 128 x 128)
128
READ
FIFO
and
data
MUX
16
DQ[15:0]
READ
drivers
Address
register
sw2
LDQS, LDQS#
Bank
control
logic
(1 . . . 4)
Columnaddress
counter/
latch
UDQS, UDQS#
VDDQ/2
128
Data
interface
Column
decoder
16
Data
WRITE
drivers
and
input
logic
RTT,nom
sw1
RTT(WR)
sw2
7
(1, 2)
LDM/UDM
3
Columns 0, 1, and 2
CK, CK#
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
RTT(WR)
I/O gating
DM mask logic
(128
x128)
10
RTT,nom
sw1
BC4
OTF
3
DQ[15:0]
VDDQ/2
BC4
128
16,384
16
sw2
sw1
Sense amplifiers
A[12:0]
BA[2:0]
RTT(WR)
CK, CK#
13
Rowaddress
MUX
RTT,nom
Column 0, 1, and 2
15
Column 2
(select upper or
lower nibble for BC4)
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
VSS
VDD
VSS
VDDQ
NC
NF, NF/TDQS#
VSS
VDD
VSSQ
DQ0
DM, DM/TDQS
VSSQ
VDDQ
DQ2
DQS
DQ1
DQ3
VSSQ
VDD
VSS
VSSQ
A
B
C
D
VSSQ
E
VREFDQ
F
NC
VSS
RAS#
CK
VSS
NC
ODT
VDD
CAS#
CK#
VDD
CKE
NC
CS#
WE#
A10/AP
ZQ
NC
VSS
BA0
BA2
NC
VREFCA
VSS
VDD
A3
A0
A12/BC#
BA1
VDD
VSS
A5
A2
A1
A4
VSS
VDD
A7
A9
A11
A6
VDD
VSS
RESET#
A13
NC
A8
VSS
G
H
J
K
L
M
N
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
1. Ball descriptions listed in Table 3 (page 18) are listed as x4, x8 if unique; otherwise,
x4 and x8 are the same.
2. A comma separates the configuration; a slash defines a selectable function.
Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies
to the x8 configuration onlyselectable between NF or TDQS# via MRS (symbols are defined in Table 3).
16
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
VDDQ
DQ13
VSSQ
DQ15
DQ12
VDDQ
VSS
VDD
VSS
UDQS#
DQ14
VSSQ
VDDQ
DQ11
DQ9
UDQS
DQ10
VDDQ
VSSQ
VDDQ
UDM
DQ8
VSSQ
VDD
VSS
VSSQ
DQ0
LDM
VSSQ
VDDQ
VDDQ
DQ2
LDQS
DQ1
DQ3
VSSQ
VSSQ
DQ6
LDQS#
VDD
VSS
VSSQ
VREFDQ
VDDQ
DQ4
DQ7
DQ5
VDDQ
NC
VSS
RAS#
CK
VSS
NC
ODT
VDD
CAS#
CK#
VDD
CKE
NC
CS#
WE#
A10/AP
ZQ
NC
VSS
BA0
BA2
NC
VREFCA
VSS
VDD
A3
A0
A12/BC#
BA1
VDD
VSS
A5
A2
A1
A4
VSS
VDD
A7
A9
A11
A6
VDD
VSS
RESET#
NC
NC
A8
VSS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
1. Ball descriptions listed in Table 4 (page 20) are listed as x4, x8 if unique; otherwise,
x4 and x8 are the same.
2. A comma separates the configuration; a slash defines a selectable function.
Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies
to the x8 configuration onlyselectable between NF or TDQS# via MRS (symbols are defined in Table 4).
17
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Type
Description
A13, A12/BC#,
A10/AP, A [9:0]
Input
Address inputs: Provide the row address for ACTIVATE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one
location out of the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE applies to one bank (A10
LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to
VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during
READ and WRITE commands to determine whether burst chop (on-the-fly) will be
performed (HIGH = BL8 or no burst chop, LOW = BC4). See Table 69 (page 113).
BA[2:0]
Input
Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE,
or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0,
MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are
referenced to VREFCA.
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All control and address input signals
are sampled on the crossing of the positive edge of CK and the negative edge of CK#.
Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.
CKE
Input
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal
circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is
dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE
LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks
idle), or active power-down (row active in any bank). CKE is synchronous for
power-down entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during
SELF REFRESH. CKE is referenced to VREFCA.
CS#
Input
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH. CS#
provides for external rank selection on systems with multiple ranks. CS# is considered
part of the command code. CS# is referenced to VREFCA.
DM
Input
Input data mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH along with the input data during a write access. Although
the DM ball is input-only, the DM loading is designed to match that of the DQ and
DQS balls. DM is referenced to VREFDQ. DM has an optional use as TDQS on the x8.
ODT
Input
On-die termination: ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DDR3 SDRAM. When enabled in normal
operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#,
and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored
if disabled via the LOAD MODE command. ODT is referenced to VREFCA.
Input
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command
being entered and are referenced to VREFCA.
RESET#
Input
Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input
receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH 0.8 VDD and
DC LOW 0.2 VDDQ. RESET# assertion and desertion are asynchronous.
DQ[0:3]
I/O
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are
referenced to VREFDQ.
18
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Type
DQ[0:7]
I/O
Description
Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are
referenced to VREFDQ.
DQS, DQS#
I/O
Data strobe: Output with read data. Edge-aligned with read data. Input with write
data. Center-aligned to write data.
TDQS, TDQS#
Output
VDD
Supply
VDDQ
Supply
DQ power supply: 1.5V 0.075V. Isolated on the device for improved noise immunity.
VREFCA
Supply
VREFDQ
Supply
Reference voltage for data: VREFDQ must be maintained at all times (excluding self
refresh) for proper device operation.
VSS
Supply
Ground.
VSSQ
Supply
ZQ
Reference
NC
No connect: These balls should be left unconnected (the ball has no connection to
the DRAM or to other balls).
NF
No function: When configured as a x4 device, these balls are NF. When configured as
a x8 device, these balls are defined as TDQS#, DQ[7:4].
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
External reference ball for output drive calibration: This ball is tied to an
external 240 resistor (RZQ), which is tied to VSSQ.
19
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Type
Description
A12/BC#, A10/AP, A
[9:0]
Input
Address inputs: Provide the row address for ACTIVATE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one
location out of the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE applies to one bank (A10
LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to
VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during
READ and WRITE commands to determine whether burst chop (on-the-fly) will be
performed (HIGH = BL8 or no burst chop, LOW = BC4). See Table 69 (page 113).
BA[2:0]
Input
Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE,
or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0,
MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are
referenced to VREFCA.
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All control and address input signals
are sampled on the crossing of the positive edge of CK and the negative edge of CK#.
Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.
CKE
Input
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal
circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is
dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE
LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks
idle),or active power-down (row active in any bank). CKE is synchronous for
power-down entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during
SELF REFRESH. CKE is referenced to VREFCA.
CS#
Input
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH. CS#
provides for external rank selection on systems with multiple ranks. CS# is considered
part of the command code. CS# is referenced to VREFCA.
LDM
Input
Input data mask: LDM is a lower-byte, input mask signal for write data. Lower-byte
input data is masked when LDM is sampled HIGH along with the input data during a
write access. Although the LDM ball is input-only, the LDM loading is designed to
match that of the DQ and DQS balls. LDM is referenced to VREFDQ.
ODT
Input
On-die termination: ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DDR3 SDRAM. When enabled in normal
operation, ODT is only applied to each of the following balls: DQ[15:0], LDQS, LDQS#,
UDQS, UDQS#, LDM, and UDM for the x16; DQ0[7:0], DQS, DQS#, DM/TDQS, and
NF/TDQS# (when TDQS is enabled) for the x8; DQ[3:0], DQS, DQS#, and DM for the x4.
The ODT input is ignored if disabled via the LOAD MODE command. ODT is
referenced to VREFCA.
Input
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command
being entered and are referenced to VREFCA.
RESET#
Input
Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input
receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH 0.8 VDD and
DC LOW 0.2 VDDQ. RESET# assertion and desertion are asynchronous.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
20
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Type
Description
UDM
Input
Input data mask: UDM is an upper-byte, input mask signal for write data. Upperbyte input data is masked when UDM is sampled HIGH along with that input data
during a WRITE access. Although the UDM ball is input-only, the UDM loading is
designed to match that of the DQ and DQS balls. UDM is referenced to VREFDQ.
DQ[0:7]
I/O
Data input/output: Lower byte of bidirectional data bus for the x16 configuration.
DQ[7:0] are referenced to VREFDQ.
DQ[8:15]
I/O
Data input/output: Upper byte of bidirectional data bus for the x16 configuration.
DQ[15:8] are referenced to VREFDQ.
LDQS, LDQS#
I/O
Lower byte data strobe: Output with read data. Edge-aligned with read data.
Input with write data. Center-aligned to write data.
UDQS, UDQS#
I/O
Upper byte data strobe: Output with read data. Edge-aligned with read data.
Input with write data. DQS is center-aligned to write data.
VDD
Supply
VDDQ
Supply
DQ power supply: 1.5V 0.075V. Isolated on the device for improved noise immunity.
VREFCA
Supply
VREFDQ
Supply
Reference voltage for data: VREFDQ must be maintained at all times (excluding self
refresh) for proper device operation.
VSS
Supply
Ground.
VSSQ
Supply
ZQ
Reference
NC
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
External reference ball for output drive calibration: This ball is tied to an
external 240 resistor (RZQ), which is tied to VSSQ.
No connect: These balls should be left unconnected (the ball has no connection to
the DRAM or to other balls).
21
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Package Dimensions
Figure 8: 78-Ball FBGA x4, x8 (JP)
0.8 0.1
Seating
plane
0.12 A
78X 0.45
Dimensions apply
to solder balls postreflow on 0.33
NSMD ball pads.
8 0.15
9
Ball A1 ID
Ball A1 ID
A
B
C
D
0.8 TYP
E
F
9.6
CTR
11.5 0.15
H
J
K
L
M
N
0.8
TYP
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
1.2 MAX
6.4 CTR
0.25 MIN
22
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
0.12 A
1.8 CTR
Nonconductive
overmold
78X 0.47
Dimensions apply
to solder balls postreflow on 0.42 SMD
ball pads.
Ball A1 ID
(covered by SR)
9 8 7
Ball A1 ID
3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
10.5 0.1
9.6 CTR
0.8 TYP
1.1 0.1
0.8 TYP
6.4 CTR
0.29 MIN
8 0.1
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
23
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
1.8 CTR
Nonconductive
overmold
96X 0.45
Dimensions apply
to solder balls postreflow on 0.35
SMD ball pads.
0.12 A
Ball A1 ID
9
Ball A1 ID
1
A
B
C
D
E
F
14 0.1
G
H
12 CTR
J
K
L
M
N
P
R
0.8 TYP
1.1 0.1
0.8 TYP
6.4 CTR
0.25 MIN
8 0.1
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
24
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
A
1.8 CTR
Nonconductive
overmold
96X 0.47
Dimensions apply
to solder balls postreflow on 0.42 SMD
ball pads.
Ball A1 ID
(covered by SR)
9 8 7
Ball A1 ID
3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
14 0.1
12 CTR
0.8 TYP
1.1 0.1
0.8 TYP
6.4 CTR
0.29 MIN
8 0.1
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
25
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Electrical Specifications
Absolute Ratings
Stresses greater than those listed in Table 5 may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other
conditions outside those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods
may adversely affect reliability.
Table 5: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
Notes
1
VDD
0.4
1.975
VDDQ
0.4
1.975
VIN, VOUT
0.4
1.975
95
2, 3
40
95
2, 3
2, 3
TC
TSTG
40
105
Storage temperature
55
150
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
1. VDD and VDDQ must be within 300mV of each other at all times, and VREF must not be
greater than 0.6 VDDQ. When VDD and VDDQ are <500mV, VREF can be 300mV.
2. MAX operating case temperature. TC is measured in the center of the package.
3. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC during operation.
26
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
800
1066
1333
1600
1866
2133
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
CK and CK#
CCK
0.8
1.6
0.8
1.6
0.8
1.4
0.8
1.4
0.8
1.3
0.8
1.3
C: CK to CK#
CDCK
0.15
0.15
0.15
0.15
0.15
0.15
pF
Single-end I/O:
DQ, DM
CIO
1.5
3.0
1.5
2.7
1.5
2.5
1.5
2.3
1.5
2.2
1.5
2.1
pF
Differential I/O:
DQS, DQS#,
TDQS, TDQS#
CIO
1.5
3.0
1.5
2.7
1.5
2.5
1.5
2.3
1.5
2.2
1.5
2.1
pF
CDDQS
0.2
0.2
0.15
0.15
0.15
0.15
pF
CDIO
0.5
0.3
0.5
0.3
0.5
0.3
0.5
0.3
0.5
0.3
0.5
0.3
pF
CI
0.75
1.4
0.75
1.35
0.75
1.3
0.75
1.3
0.75
1.2
0.75
1.2
pF
C: CTRL to CK
CDI_CTRL
0.5
0.3
0.5
0.3
0.4
0.2
0.4
0.2
0.4
0.2
0.4
0.2
pF
C: CMD_ADDR
to CK
CDI_CMD_
0.5
0.5
0.5
0.5
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
pF
C: DQS to
DQS#, TDQS,
TDQS#
C: DQ to DQS
Inputs (CTRL,
CMD, ADDR)
ADDR
ZQ pin capacitance
CZQ
3.0
3.0
3.0
3.0
3.0
3.0
pF
CRE
3.0
3.0
3.0
3.0
3.0
3.0
pF
Notes:
1. VDD = 1.5V 0.075mV, VDDQ = VDD, VREF = VSS, f = 100 MHz, TC = 25C. VOUT(DC) = 0.5
VDDQ, VOUT = 0.1V (peak-to-peak).
2. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading.
3. Includes TDQS, TDQS#. CDDQS is for DQS vs. DQS# and TDQS vs. TDQS# separately.
4. CDIO = CIO(DQ) - 0.5 (CIO(DQS) + CIO(DQS#)).
5. Excludes CK, CK#; CTRL = ODT, CS#, and CKE; CMD = RAS#, CAS#, and WE#; ADDR =
A[n:0], BA[2:0].
6. CDI_CTRL = CI(CTRL) - 0.5 (CCK(CK) + CCK(CK#)).
7. CDI_CMD_ADDR = CI(CMD_ADDR) - 0.5 (CCK(CK) + CCK(CK#)).
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
27
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Thermal Characteristics
Table 7: Thermal Characteristics
Parameter/Condition
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Value
Units
Symbol
Notes
0 to +85
TC
1, 2, 3
0 to +95
TC
1, 2, 3, 4
40 to +85
TC
1, 2, 3
40 to +95
TC
1, 2, 3, 4
40 to +85
TC
1, 2, 3
40 to +105
TC
1, 2, 3, 4
C/W
JC
C/W
JC
Junction-to-case
(TOP) - G Rev.
78-ball JP
6.4
96-ball JT
5.7
Junction-to-case
(TOP) - J Rev.
78-ball DA
10.1
96-ball TW
9.4
28
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
(L/2)
Tc test point
(W/2)
W
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
29
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
DDR3
-1066
DDR3
-1333
-25E
-25
-187E
-187
-15E
5-5-5
6-6-6
7-7-7
8-8-8
9-9-9
(MIN) IDD
2.5
1.875
DDR3
-1600
-15
-125E
-125
DDR3
-1866
DDR3
-2133
-107
-093
1.25
1.07
0.938
ns
CL IDD
10
10
11
13
14
CK
tRCD
10
10
11
13
14
CK
20
21
27
28
33
34
38
39
45
50
CK
15
15
20
20
24
24
28
28
32
36
CK
tRC
(MIN) IDD
tRAS
tRP
(MIN) IDD
(MIN) IDD
(MIN)
tFAW
tRRD
10
10
11
13
14
CK
x4, x8
16
16
20
20
20
20
24
24
26
27
CK
x16
20
20
27
27
30
30
32
32
33
38
CK
x4, x8
CK
IDD
x16
CK
tRFC
1Gb
44
44
59
59
74
74
88
88
103
118
CK
2Gb
64
64
86
86
107
107
128
128
150
172
CK
4Gb
104
104
139
139
174
174
208
208
243
279
CK
8Gb
140
140
187
187
234
234
280
280
328
375
CK
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
30
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
D#
D#
Data
A[2:0]
A[6:3]
A[9:7]
A[10]
A[15:11]
BA[2:0]
ODT
WE#
CAS#
ACT
RAS#
Command
CS#
Cycle
Number
SubLoop
CKE
CK, CK#
Static HIGH
Toggling
PRE
ACT
nRC + 1
nRC + 2
nRC + 3
D#
D#
nRC + 4
Repeat cycles nRC + 1 through nRC + 4 until nRC - 1 + nRAS -1; truncate if needed
nRC + nRAS
PRE
2 nRC
4 nRC
6 nRC
8 nRC
10 nRC
12 nRC
14 nRC
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
31
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
D#
D#
Data2
A[2:0]
A[6:3]
A[9:7]
A[10]
A[15:11]
BA[2:0]
ODT
WE#
CAS#
ACT
RAS#
Command
CS#
Cycle
Number
Sub-Loop
CKE
CK, CK#
RD
00000000
Static HIGH
Toggling
PRE
ACT
nRC + 1
nRC + 2
nRC + 3
D#
nRC + 4
D#
Repeat cycles nRC + 1 through nRC + 4 until nRC + nRCD - 1; truncate if needed
nRC + nRCD
RD
00110011
Repeat cycles nRC + 1 through nRC + 4 until nRC + nRAS - 1; truncate if needed
nRC + nRAS
PRE
2 nRC
4 nRC
6 nRC
8 nRC
10 nRC
12 nRC
14 nRC
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
1.
2.
3.
4.
DQ, DQS, DQS# are midlevel unless driven as required by the RD command.
DM is LOW.
Burst sequence is driven on each DQ signal by the RD command.
Only selected bank (single) active.
32
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Name
IDD2P0 Precharge
Power-Down
Current (Slow Exit)1
IDD2P1 Precharge
Power-Down
Current (Fast Exit)1
IDD2Q Precharge
Quiet
Standby Current
IDD3P Active
Power-Down
Current
N/A
N/A
N/A
N/A
Timing pattern
CKE
External clock
tCK
LOW
LOW
HIGH
LOW
Toggling
Toggling
Toggling
Toggling
tCK
tRC
(MIN) IDD
N/A
tCK
(MIN) IDD
N/A
tCK
(MIN) IDD
N/A
tCK
(MIN) IDD
N/A
tRAS
N/A
N/A
N/A
N/A
tRCD
N/A
N/A
N/A
N/A
tRRD
N/A
N/A
N/A
N/A
tRC
N/A
N/A
N/A
N/A
CL
N/A
N/A
N/A
N/A
AL
N/A
N/A
N/A
N/A
CS#
HIGH
HIGH
HIGH
HIGH
Command inputs
LOW
LOW
LOW
LOW
Row/column addr
LOW
LOW
LOW
LOW
Bank addresses
LOW
LOW
LOW
LOW
DM
LOW
LOW
LOW
LOW
Midlevel
Midlevel
Midlevel
Midlevel
Data I/O
Output buffer DQ, DQS
Enabled
Enabled
Enabled
Enabled
Enabled, off
Enabled, off
Enabled, off
Enabled, off
Burst length
Active banks
None
None
None
All
ODT2
Idle banks
All
All
All
None
Special notes
N/A
N/A
N/A
N/A
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
1. MR0[12] defines DLL on/off behavior during precharge power-down only; DLL on (fast
exit, MR0[12] = 1) and DLL off (slow exit, MR0[12] = 0).
2. Enabled, off means the MR bits are enabled, but the signal is LOW.
33
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Cycle
Number
Command
CS#
RAS#
CAS#
WE#
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Data
Sub-Loop
CKE
CK, CK#
D#
D#
Static HIGH
Toggling
47
811
1215
1619
2023
2427
2831
Notes:
Cycle
Number
Command
CS#
RAS#
CAS#
WE#
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Data
Sub-Loop
CKE
CK, CK#
D#
D#
Static HIGH
Toggling
47
811
1215
1619
2023
2427
2831
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
34
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
A[2:0]
Data3
00000000
D#
D#
RD
00110011
D#
D#
Static HIGH
Toggling
815
1623
2431
3239
4047
4855
5663
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
1.
2.
3.
4.
A[6:3]
A[9:7]
A[10]
CAS#
A[15:11]
RAS#
BA[2:0]
CS#
RD
ODT
Command
WE#
Cycle
Number
Sub-Loop
CKE
CK, CK#
DQ, DQS, DQS# are midlevel when not driving in burst sequence.
DM is LOW.
Burst sequence is driven on each DQ signal by the RD command.
All banks open.
35
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
A[2:0]
Data4
00000000
D#
D#
WR
00110011
D#
D#
Static HIGH
Toggling
815
1623
2431
3239
4047
4855
5663
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
1.
2.
3.
4.
A[6:3]
A[9:7]
A[10]
CAS#
A[15:11]
RAS#
BA[2:0]
CS#
WR
ODT
Command
WE#
Cycle
Number
Sub-Loop
CKE
CK, CK#
DQ, DQS, DQS# are midlevel when not driving in burst sequence.
DM is LOW.
Burst sequence is driven on each DQ signal by the WR command.
All banks open.
36
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
D#
D#
Static HIGH
Toggling
1a
1b
58
1c
912
1d
1316
1e
1720
1f
2124
1g
2528
1h
2932
33nRFC - 1
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Data
A[2:0]
A[6:3]
A[9:7]
A[10]
A[15:11]
BA[2:0]
ODT
WE#
REF
CAS#
Command
RAS#
Cycle
Number
CS#
Sub-Loop
CKE
CK, CK#
37
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Table 17: IDD Measurement Conditions for IDD6, IDD6ET, and IDD8
IDD Test
CKE
External clock
IDD8: Reset2
LOW
LOW
Midlevel
Midlevel
tCK
N/A
N/A
N/A
tRC
N/A
N/A
N/A
tRAS
N/A
N/A
N/A
tRCD
N/A
N/A
N/A
tRRD
N/A
N/A
N/A
tRC
N/A
N/A
N/A
CL
N/A
N/A
N/A
AL
N/A
N/A
N/A
CS#
Midlevel
Midlevel
Midlevel
Command inputs
Midlevel
Midlevel
Midlevel
Row/column addresses
Midlevel
Midlevel
Midlevel
Bank addresses
Midlevel
Midlevel
Midlevel
Data I/O
Midlevel
Midlevel
Midlevel
Enabled
Enabled
Midlevel
Enabled, midlevel
Enabled, midlevel
Midlevel
Burst length
N/A
N/A
N/A
Active banks
N/A
N/A
None
Idle banks
N/A
N/A
All
SRT
Disabled (normal)
Enabled (extended)
N/A
ASR
Disabled
Disabled
N/A
ODT1
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
1. Enabled, midlevel means the MR command is enabled, but the signal is midlevel.
2. During a cold boot RESET (initialization), current reading is valid after power is stable
and RESET has been LOW for 1ms; During a warm boot RESET (while operating), current
reading is valid after RESET has been LOW for 200ns + tRFC.
38
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Command
CS#
RAS#
CAS#
WE#
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Data3
Cycle
Number
Sub-Loop
CKE
CK, CK#
ACT
RDA
00000000
Static HIGH
nRRD
ACT
nRRD + 1
RDA
00110011
nRRD + 2
nRRD + 3
2 nRRD
3 nRRD
4 nRRD
Toggling
4 nRRD + 1
nFAW
nFAW + nRRD
nFAW + 2 nRRD
nFAW + 3 nRRD
nFAW + 4 nRRD
nFAW + 4 nRRD + 1
10
2 nFAW
ACT
2 nFAW + 1
RDA
00110011
2 nFAW + 2
2 nFAW + 3
11
2 nFAW + nRRD
ACT
2 nFAW + nRRD + 1
RDA
00000000
2 nFAW + nRRD + 2
2 nFAW + nRRD + 3
12
2 nFAW + 2 nRRD
13
2 nFAW + 3 nRRD
14
2 nFAW + 4 nRRD
2 nFAW + 4 nRRD + 1
3 nFAW
15
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
39
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
3 nFAW + 4 nRRD + 1
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
1.
2.
3.
4.
Data3
A[6:3]
A[2:0]
19
3 nFAW + 4 nRRD
A[9:7]
3 nFAW + 3 nRRD
A[10]
18
A[15:11]
BA[2:0]
3 nFAW + 2 nRRD
ODT
17
WE#
CAS#
3 nFAW + nRRD
RAS#
16
CS#
Cycle
Number
Command
Sub-Loop
CKE
Static HIGH
Toggling
CK, CK#
DQ, DQS, DQS# are midlevel unless driven as required by the RD command.
DM is LOW.
Burst sequence is driven on each DQ signal by the RD command.
AL = CL-1.
40
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
DDR3
-1066
DDR3
-1333
DDR3
-1600
DDR3
-1866
Parameter
Symbol
Width
Units
Notes
IDD0
x4, x8
60
65
70
70
mA
1, 2
x16
75
80
85
90
mA
1, 2
IDD1
x4, x8
80
85
90
90
mA
1, 2
x16
100
110
115
120
mA
1, 2
Precharge power-down
current;Slow exit
IDD2P0 (slow)
All
12
12
12
12
mA
1, 2
Precharge power-down
current;Fast exit
IDD2P1 (fast)
All
25
30
30
35
mA
1, 2
IDD2Q
All
35
35
40
45
mA
1, 2
All
35
40
45
50
mA
1, 2
x4, x8
45
50
55
60
mA
1, 2
x16
55
60
65
75
mA
1, 2
IDD2NT
IDD3P
All
30
30
35
35
mA
1, 2
IDD3N
x4, x8
40
40
45
50
mA
1, 2
x16
45
45
50
55
mA
1, 2
IDD4R
x4, x8
105
125
140
155
mA
1, 2
x16
140
165
190
215
mA
1, 2
IDD4W
x4, x8
110
125
145
160
mA
1, 2
x16
155
180
205
230
mA
1, 2
IDD5B
All
160
165
170
175
mA
1, 2
All
mA
1, 2, 3
All
10
10
10
10
mA
1, 4
x4, x8
195
235
245
260
mA
1, 2
x16
235
265
300
330
mA
1, 2
All
IDD2P0 +
2mA
IDD2P0 +
2mA
IDD2P0 +
2mA
IDD2P0 +
2mA
mA
1, 2
IDD8
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
1.
2.
3.
4.
5.
41
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
DDR3
-1066
DDR3
-1333
DDR3
-1600
DDR3
-1866
DDR3
-2133
Units
Notes
IDD0
Operating current 0:
One bank ACTIVATE-toPRECHARGE
x4, x8
39
41
42
43
46
mA
1, 2
x16
46
48
49
51
55
mA
1, 2
Operating current 1:
IDD1
One bank ACTIVATE-toREAD-to-PRECHARGE
x4, x8
50
54
56
58
60
mA
1, 2
x16
62
67
69
72
75
mA
1, 2
All
12
12
12
12
12
mA
1, 2
All
15
15
15
15
15
mA
1, 2
IDD2Q
All
22
22
22
22
22
mA
1, 2
IDD2N
All
23
23
23
23
23
mA
1, 2
x4, x8
29
32
34
36
40
mA
1, 2
x16
33
36
37
39
43
mA
1, 2
Parameter
Symbol
IDD3P
All
17
17
17
17
17
mA
1, 2
IDD3N
x4, x8
31
33
35
37
40
mA
1, 2
x16
33
36
37
39
43
mA
1, 2
IDD4R
x4, X8
74
88
100
110
125
mA
1, 2
x16
95
115
135
155
180
mA
1, 2
IDD4W
x4, X8
79
91
103
114
126
mA
1, 2
x16
107
127
146
164
184
mA
1, 2
IDD5B
All
155
160
160
165
170
mA
1, 2
All
12
12
12
12
12
mA
1, 2, 3
Extended temperature
self refresh
IDD6ET
All
15
15
15
15
15
mA
1, 4
IDD7
x4, X8
128
157
163
171
190
mA
1, 2
x16
159
179
202
226
248
mA
1, 2
All
IDD2P0 +
2mA
IDD2P0 +
2mA
IDD2P0 +
2mA
IDD2P0 +
2mA
IDD2P0 +
2mA
mA
1, 2
Reset current
IDD8
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
42
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
43
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Symbol
Min
Nom
Max
Unit
Notes
Supply voltage
VDD
1.425
1.5
1.575
1, 2
VDDQ
1.425
1.5
1.575
1, 2
II
IVREF
3, 4
1. VDD and VDDQ must track one another. VDDQ must be VDD. VSS = VSSQ.
2. VDD and VDDQ may include AC noise of 50mV (250 kHz to 20 MHz) in addition to the
DC (0 Hz to 250 kHz) specifications. VDD and VDDQ must be at same level for valid AC
timing parameters.
3. VREF (see Table 22).
4. The minimum limit requirement is for testing purposes. The leakage current on the VREF
pin should be minimal.
Symbol
Min
Nom
Max
Unit
VIL
VSS
n/a
See Table 23
Notes
VIH
See Table 23
n/a
VDD
VREFCA(DC)
0.49 VDD
0.5 VDD
0.51 VDD
1, 2
VREFDQ(DC)
0.49 VDD
0.5 VDD
0.51 VDD
2, 3
VREFDQ(SR)
VSS
0.5 VDD
VDD
VTT
0.5 VDDQ
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
44
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
DDR3-800
DDR3-1066
Symbol
DDR3-1333
DDR3-1600
DDR3-1866
DDR3-2133
Unit
mV
VIH(AC175)min
175
175
VIH(AC150)min
150
150
mV
VIH(AC135)min
135
mV
VIH(AC125)min
125
mV
VIH(DC100)min
100
100
100
mV
VIL(DC100)max
100
100
100
mV
VIL(AC125)max
125
mV
VIL(AC135)max
135
mV
VIL(AC150)max
150
150
mV
VIL(AC175)max
175
175
mV
DQ and DM
Input high AC voltage: Logic 1
VIH(AC175)min
175
mV
VIH(AC150)min
150
150
mV
VIH(AC135)min
135
mV
VIH(DC100)min
100
100
100
mV
VIL(DC100)max
100
100
100
mV
VIL(AC135)max
135
mV
VIL(AC150)max
150
150
mV
VIL(AC175)max
175
mV
Notes:
1. All voltages are referenced to VREF. VREF is VREFCA for control, command, and address. All
slew rates and setup/hold times are specified at the DRAM ball. VREF is VREFDQ for DQ
and DM inputs.
2. Input setup timing parameters (tIS and tDS) are referenced at VIL(AC)/VIH(AC), not VREF(DC).
3. Input hold timing parameters (tIH and tDH) are referenced at VIL(DC)/VIH(DC), not VREF(DC).
4. Single-ended input slew rate = 1 V/ns; maximum input voltage swing under test is
900mV (peak-to-peak).
5. When two VIH(AC) values (and two corresponding VIL(AC) values) are listed for a specific
speed bin, the user may choose either value for the input AC level. Whichever value is
used, the associated setup time for that AC level must also be used. Additionally, one
VIH(AC) value may be used for address/command inputs and the other VIH(AC) value may
be used for data inputs.
For example, for DDR3-800, two input AC levels are defined: VIH(AC175),min and
VIH(AC150),min (corresponding VIL(AC175),min and VIL(AC150),min). For DDR3-800, the address/
command inputs must use either VIH(AC175),min with tIS(AC175) of 200ps or VIH(AC150),min
with tIS(AC150) of 350ps; independently, the data inputs must use either VIH(AC175),min
with tDS(AC175) of 75ps or VIH(AC150),min with tDS(AC150) of 125ps.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
45
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Table 24: Differential Input Operating Conditions (CK, CK# and DQS, DQS#)
Parameter/Condition
Differential input voltage logic high - slew
Symbol
Min
Max
Unit
Notes
VIH,diff
200
n/a
mV
VIL,diff
n/a
200
mV
VIH,diff(AC)
2 (VIH(AC) - VREF)
VDD/VDDQ
mV
VIL,diff(AC)
VSS/VSSQ
2 (VIL(AC)-VREF)
mV
VIX
VREF(DC) - 150
VREF(DC) + 150
mV
4, 7
VIX (175)
VREF(DC) - 175
VREF(DC) + 175
mV
4, 7, 8
VSEH
VDDQ/2 + 175
VDDQ
mV
VDD/2 + 175
VDD
mV
VSSQ
VDDQ/2 - 175
mV
VSS
VDD/2 - 175
mV
VSEL
1.
2.
3.
4.
5.
6.
7.
8.
9.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Clock is referenced to VDD and VSS. Data strobe is referenced to VDDQ and VSSQ.
Reference is VREFCA(DC) for clock and VREFDQ(DC) for strobe.
Differential input slew rate = 2 V/ns
Defines slew rate reference points, relative to input crossing voltages.
Minimum DC limit is relative to single-ended signals; overshoot specifications are applicable.
Maximum DC limit is relative to single-ended signals; undershoot specifications are applicable.
The typical value of VIX(AC) is expected to be about 0.5 VDD of the transmitting device,
and VIX(AC) is expected to track variations in VDD. VIX(AC) indicates the voltage at which
differential input signals must cross.
The VIX extended range (175mV) is allowed only for the clock; this VIX extended range
is only allowed when the following conditions are met: The single-ended input signals
are monotonic, have the single-ended swing VSEL, VSEH of at least VDD/2 250mV, and
the differential slew rate of CK, CK# is greater than 3 V/ns.
VIX must provide 25mV (single-ended) of the voltages separation.
46
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
1.50V
VDDQ
0.925V
0.850V
VIH(AC)
VIH(DC)
0.575V
VIH(AC)
0.850V
VIH(DC)
0.780V
0.765V
0.750V
0.735V
0.720V
0.780V
0.765V
0.750V
0.735V
0.720V
0.650V
0.925V
VIL(DC)
VIL(AC)
VREF + AC noise
VREF + DC error
VREF - DC error
VREF - AC noise
0.650V
VIL(DC)
0.575V
VIL(AC)
0.0V
VSS
0.40V
Note:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
47
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
DDR3-1866
DDR3-2133
0.4V
0.4V
0.4V
0.4V
0.4V
0.4V
0.4V
0.4V
0.4V
0.4V
0.4V
0.4V
0.67 Vns
0.5 Vns
0.4 Vns
0.33 Vns
0.28 Vns
0.25 Vns
0.67 Vns
0.5 Vns
0.4 Vns
0.33 Vns
0.28 Vns
0.25 Vns
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
DDR3-1866
DDR3-2133
0.4V
0.4V
0.4V
0.4V
0.4V
0.4V
0.4V
0.4V
0.4V
0.4V
0.4V
0.4V
0.25 Vns
0.19 Vns
0.15 Vns
0.13 Vns
0.11 Vns
0.10 Vns
0.25 Vns
0.19 Vns
0.15 Vns
0.13 Vns
0.11 Vns
0.10 Vns
Volts (V)
VDD/VDDQ
Time (ns)
Volts (V)
Undershoot area
Maximum amplitude
Time (ns)
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
48
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
VDD, VDDQ
CK#, DQS#
CK#, DQS#
VIX
VIX
VDD/2, VDDQ/2
VDD/2, VDDQ/2
VIX
VIX
CK, DQS
CK, DQS
VSS, VSSQ
VSS, VSSQ
VSEH,min
VDD/2 or VDDQ/2
VSEH
CK or DQS
VSEL,max
VSEL
VSS or VSSQ
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
49
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
VIH,diff,min
CK - CK#
DQS - DQS#
0.0
VIL,diff,max
VIL,diff(AC)max
tDVAC
Half cycle
Table 27: Allowed Time Before Ringback (tDVAC) for CK - CK# and DQS DQS#
tDVAC
Note:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
350mV
300mV
>4.0
75
175
4.0
57
170
3.0
50
167
2.0
38
163
1.9
34
162
1.6
29
161
1.4
22
159
1.2
13
155
1.0
150
<1.0
150
1. Below VIL(AC)
50
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Measured
Input
Edge
From
To
Calculation
Setup
Rising
VREF
VIH(AC)min
VIH(AC),min - VREF
TRSse
Falling
VREF
VIL(AC)max
VREF - VIL(AC),max
TFSse
Hold
Rising
VIL(DC)max
VREF
VREF - VIL(DC),max
TFHse
Falling
VIH(DC)min
VREF
VIH(DC),min - VREF
TRSHse
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
51
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Setup
Single-ended input voltage (DQ, CMD, ADDR)
VIH(AC)min
VIH(DC)min
VREFDQ or
VREFCA
VIL(DC)max
VIL(AC)max
TFSse
TRHse
Hold
Single-ended input voltage (DQ, CMD, ADDR)
VIH(AC)min
VIH(DC)min
VREFDQ or
VREFCA
VIL(DC)max
VIL(AC)max
TFHse
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
52
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Measured
Input
Edge
From
To
Calculation
CK and
DQS
reference
Rising
VIL,diff,max
VIH,diff,min
VIH,diff,min - VIL,diff,max
TRdiff
Falling
VIH,diff,min
VIL,diff,max
VIH,diff,min - VIL,diff,max
TFdiff
Figure 20: Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK#
TRdiff
VIH,diff,min
VIL,diff,max
TFdiff
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
53
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
ODT Characteristics
The ODT effective resistance RTT is defined by MR1[9, 6, and 2]. ODT is applied to the
DQ, DM, DQS, DQS#, and TDQS, TDQS# balls (x8 devices only). The ODT target values
and a functional representation are listed in Table 30 and Table 31 (page 55). The individual pull-up and pull-down resistors (RTT(PU) and RTT(PD)) are defined as follows:
RTT(PU) = (VDDQ - VOUT)/|IOUT|, under the condition that RTT(PD) is turned off
RTT(PD) = (VOUT)/|IOUT|, under the condition that RTT(PU) is turned off
Figure 21: ODT Levels and I-V Characteristics
Chip in termination mode
ODT
VDDQ
IPU
IOUT = IPD - IPU
RTT(PU)
To
other
circuitry
such as
RCV, . . .
DQ
IOUT
RTT(PD)
VOUT
IPD
VSSQ
Symbol
RTT(EFF)
VM
Min
Nom
Max
Unit
Notes
1, 2
1, 2, 3
1. Tolerance limits are applicable after proper ZQ calibration has been performed at a
stable temperature and voltage (VDDQ = VDD, VSSQ = VSS). Refer to ODT Sensitivity
(page 56) if either the temperature or voltage changes after calibration.
2. Measurement definition for RTT: Apply VIH(AC) to pin under test and measure current
I[VIH(AC)], then apply VIL(AC) to pin under test and measure current I[VIL(AC)]:
VIH(AC) - VIL(AC)
RTT =
I(VIH(AC)) - I(VIL(AC))
3. Measure voltage (VM) at the tested pin with no load:
VM =
2 VM
1 100
VDDQ
4. For IT and AT devices, the minimum values are derated by 6% when the device operates
between 40C and 0C (TC).
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
54
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
RTT
Resistor
VOUT
Min
Nom
Max
Unit
0, 1, 0
RTT120(PD240)
0.2 VDDQ
0.6
1.0
1.1
RZQ/1
0.5 VDDQ
0.9
1.0
1.1
RZQ/1
0.8 VDDQ
0.9
1.0
1.4
RZQ/1
RTT120(PU240)
0, 0, 1
RTT60(PD120)
RTT60(PU120)
0, 1, 1
RTT40(PD80)
RTT40(PU80)
1, 0, 1
RTT30(PD60)
RTT30(PU60)
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
0.2 VDDQ
0.9
1.0
1.4
RZQ/1
0.5 VDDQ
0.9
1.0
1.1
RZQ/1
0.8 VDDQ
0.6
1.0
1.1
RZQ/1
VIL(AC) to VIH(AC)
0.9
1.0
1.6
RZQ/2
0.2 VDDQ
0.6
1.0
1.1
RZQ/2
0.5 VDDQ
0.9
1.0
1.1
RZQ/2
0.8 VDDQ
0.9
1.0
1.4
RZQ/2
0.2 VDDQ
0.9
1.0
1.4
RZQ/2
0.5 VDDQ
0.9
1.0
1.1
RZQ/2
0.8 VDDQ
0.6
1.0
1.1
RZQ/2
VIL(AC) to VIH(AC)
0.9
1.0
1.6
RZQ/4
0.2 VDDQ
0.6
1.0
1.1
RZQ/3
0.5 VDDQ
0.9
1.0
1.1
RZQ/3
0.8 VDDQ
0.9
1.0
1.4
RZQ/3
0.2 VDDQ
0.9
1.0
1.4
RZQ/3
0.5 VDDQ
0.9
1.0
1.1
RZQ/3
0.8 VDDQ
0.6
1.0
1.1
RZQ/3
VIL(AC) to VIH(AC)
0.9
1.0
1.6
RZQ/6
0.2 VDDQ
0.6
1.0
1.1
RZQ/4
0.5 VDDQ
0.9
1.0
1.1
RZQ/4
0.8 VDDQ
0.9
1.0
1.4
RZQ/4
0.2 VDDQ
0.9
1.0
1.4
RZQ/4
0.5 VDDQ
0.9
1.0
1.1
RZQ/4
0.8 VDDQ
0.6
1.0
1.1
RZQ/4
VIL(AC) to VIH(AC)
0.9
1.0
1.6
RZQ/8
55
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
RTT
Resistor
VOUT
Min
Nom
Max
Unit
1, 0, 0
RTT20(PD40)
0.2 VDDQ
0.6
1.0
1.1
RZQ/6
0.5 VDDQ
0.9
1.0
1.1
RZQ/6
0.8 VDDQ
0.9
1.0
1.4
RZQ/6
RTT20(PU40)
Note:
0.2 VDDQ
0.9
1.0
1.4
RZQ/6
0.5 VDDQ
0.9
1.0
1.1
RZQ/6
0.8 VDDQ
0.6
1.0
1.1
RZQ/6
VIL(AC) to VIH(AC)
0.9
1.0
1.6
RZQ/12
ODT Sensitivity
If either the temperature or voltage changes after I/O calibration, then the tolerance
limits listed in Table 30 (page 54) and Table 31 can be expected to widen according to
Table 32 and Table 33 (page 56).
Table 32: ODT Sensitivity Definition
Symbol
Min
Max
Unit
RTT
RZQ/(2, 4, 6, 8, 12)
Note:
Note:
Change
Min
Max
Unit
dRTTdT
1.5
%/C
dRTTdV
0.15
%/mV
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
56
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
VREF
VDDQ/2
RTT = 25
DQ, DM
DQS, DQS#
TDQS, TDQS#
ZQ
VTT = VSSQ
Timing reference point
RZQ = 240
VSSQ
Figure
tAON
tAOF
tAONPD
Rising edge of CK - CK# with ODT first being Extrapolated point at VSSQ
registered HIGH
tAOFPD
Rising edge of CK - CK# with ODT first being Extrapolated point at VRTT,nom
registered LOW
Rising edge of CK - CK# defined by the end Extrapolated points at VRTT(WR) and
point of ODTLcnw, ODTLcwn4, or ODTLcwn8 VRTT,nom
tADC
RTT,nom Setting
RTT(WR) Setting
VSW1
VSW2
tAON
RZQ/4 (60
n/a
50mV
100mV
RZQ/12 (20
n/a
100mV
200mV
RZQ/4 (60
n/a
50mV
100mV
RZQ/12 (20
n/a
100mV
200mV
RZQ/4 (60
n/a
50mV
100mV
RZQ/12 (20
n/a
100mV
200mV
RZQ/4 (60
n/a
50mV
100mV
RZQ/12 (20
n/a
100mV
200mV
RZQ/12 (20
RZQ/2 (120
200mV
300mV
tAOF
tAONPD
tAOFPD
tADC
Note:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
1. Assume an RZQ of 240 (1%) and that proper ZQ calibration has been performed at a
stable temperature and voltage (VDDQ = VDD, VSSQ = VSS).
57
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
tAON
tAOF
Begin point: Rising edge of CK - CK#
defined by the end point of ODTLoff
CK
VDDQ/2
CK#
CK#
tAON
tAOF
End point: Extrapolated point at VRTT,nom
TSW2
TSW1
TSW1
DQ, DM
DQS, DQS#
TDQS, TDQS#
VSW2
TSW1
VSW2
VSW1
VSW1
VSSQ
VRTT,nom
VSSQ
tAOFPD
Begin point: Rising edge of CK - CK#
with ODT first registered low
CK
CK
VDDQ/2
CK#
CK#
tAONPD
tAOFPD
End point: Extrapolated point at VRTT,nom
TSW2
TSW2
TSW1
DQ, DM
DQS, DQS#
TDQS, TDQS#
TSW1
VSW2
VSSQ
VRTT,nom
VSW2
VSW1
VSW1
VSSQ
End point: Extrapolated point at VSSQ
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
58
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
CK
VDDQ/2
CK#
tADC
VRTT,nom
DQ, DM
DQS, DQS#
TDQS, TDQS#
End point:
Extrapolated
point at VRTT,nom
tADC
VRTT,nom
TSW21
TSW11
VSW2
VSW1
TSW22
TSW12
VRTT(WR)
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
59
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
VDDQ
IPU
To
other
circuitry
such as
RCV, . . .
RON(PU)
DQ
IOUT
RON(PD)
VOUT
IPD
VSSQ
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
60
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
RON
Resistor
VOUT
Min
Nom
Max
Unit
0,1
RON34(PD)
0.2/VDDQ
0.6
1.0
1.1
RZQ/7
RON34(PU)
0.5/VDDQ
0.9
1.0
1.1
RZQ/7
0.8/VDDQ
0.9
1.0
1.4
RZQ/7
0.2/VDDQ
0.9
1.0
1.4
RZQ/7
0.5/VDDQ
0.9
1.0
1.1
RZQ/7
0.8/VDDQ
0.6
1.0
1.1
RZQ/7
0.5/VDDQ
10%
n/a
10
Notes
1. Tolerance limits assume RZQ of 240 1% and are applicable after proper ZQ calibration has been performed at a stable temperature and voltage: VDDQ = VDD; VSSQ = VSS).
Refer to 34 Ohm Output Driver Sensitivity (page 63) if either the temperature or the
voltage changes after calibration.
2. Measurement definition for mismatch between pull-up and pull-down (MMPUPD). Measure both RON(PU) and RON(PD) at 0.5 VDDQ:
RON(PU) - RON(PD)
MMPUPD =
100
RON,nom
3. For IT and AT (1Gb only) devices, the minimum values are derated by 6% when the device operates between 40C and 0C (TC).
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
61
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Min
Nom
Max
Unit
RZQ = 240
237.6
240
242.4
33.9
34.3
34.6
MR1[5,1]
RON
Resistor
VOUT
Min
Nom
Max
Unit
0, 1
RON34(PD)
0.2 VDDQ
20.4
34.3
38.1
0.5 VDDQ
30.5
34.3
38.1
0.8 VDDQ
30.5
34.3
48.5
0.2 VDDQ
30.5
34.3
48.5
0.5 VDDQ
30.5
34.3
38.1
0.8 VDDQ
20.4
34.3
38.1
RZQ/7 = (240
RON34(PU)
RON
Resistor
VOUT
Max
Nom
Min
Unit
0, 1
RON34(PD)
14.7
8.8
7.9
mA
24.6
21.9
19.7
mA
39.3
35.0
24.8
mA
39.3
35.0
24.8
mA
24.6
21.9
19.7
mA
14.7
8.8
7.9
mA
Min
Unit
RON34(PU)
RON
Resistor
0, 1
RON34(PD)
RON34(PU)
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
VOUT
Max
Nom
15.5
9.2
8.3
mA
25.8
23
20.7
mA
41.2
36.8
26
mA
41.2
36.8
26
mA
25.8
23
20.7
mA
15.5
9.2
8.3
mA
62
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
RON
Resistor
VOUT
Max
Nom
Min
Unit
0, 1
RON34(PD)
14.0
8.3
7.5
mA
23.3
20.8
18.7
mA
37.3
33.3
23.5
mA
RON34(PU)
37.3
33.3
23.5
mA
23.3
20.8
18.7
mA
14.0
8.3
7.5
mA
Min
Max
Unit
RZQ/7
RZQ/7
RZQ/7
RZQ/7
RZQ/7
RZQ/7
Note:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Change
Min
Max
Unit
dRONdTM
1.5
%/C
dRONdVM
0.13
%/mV
dRONdTL
1.5
%/C
dRONdVL
0.13
%/mV
dRONdTH
1.5
%/C
dRONdVH
0.13
%/mV
63
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
RON
Resistor
VOUT
Min
Nom
Max
Unit
0,0
RON40(PD)
0.2 VDDQ
0.6
1.0
1.1
RZQ/6
0.5 VDDQ
0.9
1.0
1.1
RZQ/6
0.8 VDDQ
0.9
1.0
1.4
RZQ/6
RON40(PU)
0.2 VDDQ
0.9
1.0
1.4
RZQ/6
0.5 VDDQ
0.9
1.0
1.1
RZQ/6
0.8 VDDQ
0.6
1.0
1.1
RZQ/6
0.5 VDDQ
10%
n/a
10
1. Tolerance limits assume RZQ of 240 1% and are applicable after proper ZQ calibration has been performed at a stable temperature and voltage (VDDQ = VDD; VSSQ = VSS).
Refer to 40 Ohm Output Driver Sensitivity (page 64) if either the temperature or the
voltage changes after calibration.
2. Measurement definition for mismatch between pull-up and pull-down (MMPUPD). Measure both RON(PU) and RON(PD) at 0.5 VDDQ:
RON(PU) - RON(PD)
MMPUPD =
100
RON,nom
Notes:
3. For IT and AT (1Gb only) devices, the minimum values are derated by 6% when the device operates between 40C and 0C (TC).
Min
Max
Unit
RZQ/6
RZQ/6
RZQ/6
RZQ/6
RZQ/6
Note:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
RZQ/6
64
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Change
Min
Max
Unit
dRONdTM
1.5
%/C
dRONdVM
0.15
%/mV
dRONdTL
1.5
%/C
dRONdVL
0.15
%/mV
dRONdTH
1.5
%/C
dRONdVH
0.15
%/mV
65
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Symbol
Min
Max
Unit
Notes
IOZ
SRQse
2.5
V/ns
1, 2, 3, 4
VOH(DC)
0.8 VDDQ
1, 2, 5
VOM(DC)
0.5 VDDQ
1, 2, 5
VOL(DC)
0.2 VDDQ
1, 2, 5
VOH(AC)
1, 2, 3, 6
1, 2, 3, 6
1, 7
VOL(AC)
MMPUPD
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
10
1. RZQ of 240 1% with RZQ/7 enabled (default 34 driver) and is applicable after proper ZQ calibration has been performed at a stable temperature and voltage (VDDQ = VDD;
VSSQ = VSS).
2. VTT = VDDQ/2.
3. See Figure 29 (page 68) for the test load configuration.
4. The 6 V/ns maximum is applicable for a single DQ signal when it is switching either from
HIGH to LOW or LOW to HIGH while the remaining DQ signals in the same byte lane are
either all static or all switching in the opposite direction. For all other DQ signal switching combinations, the maximum limit of 6 V/ns is reduced to 5 V/ns.
5. See Table 36 (page 61) for IV curve linearity. Do not use AC test load.
6. See Table 48 (page 69) for output slew rate.
7. See Table 36 (page 61) for additional information.
8. See Figure 27 (page 67) for an example of a single-ended output signal.
66
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Symbol
Min
Max
Unit
Notes
IOZ
SRQdiff
12
V/ns
VOX(AC)
VREF - 150
VREF + 150
mV
1, 2, 3
VOH,diff(AC)
1, 4
VOL,diff(AC)
1, 4
1, 5
MMPUPD
0.2 VDDQ
10
10
+0.2 VDDQ
1. RZQ of 240 1% with RZQ/7 enabled (default 34 driver) and is applicable after proper ZQ calibration has been performed at a stable temperature and voltage (VDDQ = VDD;
VSSQ = VSS).
2. VREF = VDDQ/2; slew rate @ 5 V/ns, interpolate for faster slew rate.
3. See Figure 29 (page 68) for the test load configuration.
4. See Table 49 (page 70) for the output slew rate.
5. See Table 36 (page 61) for additional information.
6. See Figure 28 (page 68) for an example of a differential output signal.
VOH(AC)
VOL(AC)
MIN output
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
67
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
VOH
VOX(AC)max
X
X
VOX(AC)min
VOL
MIN output
VDDQ/2
DUT
VREF
DQ
DQS
DQS#
RTT = 25
VTT = VDDQ/2
RZQ = 240
VSS
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
68
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Measured
Output
Edge
From
To
Calculation
DQ
Rising
VOL(AC)
VOH(AC)
VOH(AC) - VOL(AC)
TRse
Falling
VOH(AC)
VOL(AC)
VOH(AC) - VOL(AC)
TFse
Figure 30: Nominal Slew Rate Definition for Single-Ended Output Signals
TRse
VOH(AC)
VTT
VOL(AC)
TFse
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
69
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Measured
Output
Edge
From
To
Calculation
DQS, DQS#
Rising
VOL,diff(AC)
VOH,diff(AC)
VOH,diff(AC) - VOL,diff(AC)
TRdiff
Falling
VOH,diff(AC)
VOL,diff(AC)
VOH,diff(AC) - VOL,diff(AC)
TFdiff
Figure 31: Nominal Differential Output Slew Rate Definition for DQS, DQS#
TRdiff
VOH,diff(AC)
VOL,diff(AC)
TFdiff
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
70
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
-187E
-187
CL-tRCD-tRP
7-7-7
8-8-8
Parameter
Symbol
Min
Max
Min
Max
Unit
tAA
13.125
15
ns
tRCD
13.125
15
ns
tRP
13.125
15
ns
tRC
50.625
52.5
ns
tRAS
37.5
9 x tREFI
37.5
9 x tREFI
ns
3.0
3.3
3.0
3.3
ns
ns
CWL = 5
tCK
(AVG)
CWL = 6
tCK
(AVG)
CWL = 5
tCK
(AVG)
ns
CWL = 6
tCK
(AVG)
Reserved
Reserved
ns
CWL = 5
tCK
(AVG)
Reserved
Reserved
ns
CWL = 6
tCK
(AVG)
Reserved
ns
2, 3
CWL = 5
tCK
(AVG)
CWL = 6
tCK
(AVG)
Reserved
2.5
<2.5
Reserved
1.875
3.3
1.875
Supported CL settings
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Notes
<2.5
Reserved
2.5
3.3
Reserved
1.875
<2.5
ns
ns
5, 6, 7, 8
5, 6, 8
CK
5, 6
5, 6
CK
71
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
-15E1
-152
CL-tRCD-tRP
9-9-9
10-10-10
Parameter
Symbol
Min
Max
Min
Max
Unit
tAA
13.5
15
ns
tRCD
13.5
15
ns
tRP
13.5
15
ns
tRC
49.5
51
ns
tRAS
36
9 x tREFI
36
9 x tREFI
ns
3.0
3.3
3.0
3.3
ns
ns
CL = 7
CL = 8
CL = 9
CL = 10
CWL = 5
tCK
(AVG)
CWL = 6, 7
tCK
(AVG)
CWL = 5
tCK
(AVG)
ns
CWL = 6
tCK
(AVG)
Reserved
Reserved
ns
CWL = 7
tCK
(AVG)
Reserved
Reserved
ns
CWL = 5
tCK
(AVG)
Reserved
Reserved
ns
CWL = 6
tCK
(AVG)
Reserved
ns
4, 5
CWL = 7
tCK
(AVG)
Reserved
Reserved
ns
CWL = 5
tCK
(AVG)
Reserved
Reserved
ns
CWL = 6
tCK
(AVG)
ns
CWL = 7
tCK
(AVG)
Reserved
Reserved
ns
CWL = 5, 6
tCK
(AVG)
Reserved
Reserved
ns
CWL = 7
tCK
(AVG)
Reserved
ns
4, 5
CWL = 5, 6
tCK
(AVG)
Reserved
ns
CWL = 7
tCK
(AVG)
ns
Reserved
2.5
<2.5
1.875
1.5
<2.5
<1.875
Reserved
1.5
3.3
1.875
Supported CL settings
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Notes
<1.875
Reserved
2.5
3.3
1.875
1.5
<2.5
<1.875
5, 6, 7, 8, 9, 10
5, 6, 8, 10
CK
5, 6, 7
5, 6, 7
CK
1.
2.
3.
4.
72
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
11-11-11
Parameter
Symbol
Min
Max
Unit
tAA
13.75
ns
tRCD
13.75
ns
tRP
13.75
ns
tRC
48.75
ns
tRAS
35
9 x tREFI
ns
3.0
3.3
ns
ns
CL = 7
CL = 8
CL = 9
CL = 10
CL = 11
CWL = 5
tCK
(AVG)
CWL = 6, 7, 8
tCK
(AVG)
CWL = 5
tCK
(AVG)
ns
CWL = 6
tCK
(AVG)
Reserved
ns
CWL = 7, 8
tCK
(AVG)
Reserved
ns
CWL = 5
tCK
(AVG)
Reserved
ns
CWL = 6
tCK
(AVG)
ns
CWL = 7
tCK
(AVG)
Reserved
ns
CWL = 8
tCK
(AVG)
Reserved
ns
CWL = 5
tCK
(AVG)
Reserved
ns
CWL = 6
tCK
(AVG)
ns
CWL = 7
tCK
(AVG)
Reserved
ns
CWL = 8
tCK
(AVG)
Reserved
ns
CWL = 5, 6
tCK
(AVG)
Reserved
ns
CWL = 7
tCK
(AVG)
ns
CWL = 8
tCK
(AVG)
Reserved
ns
CWL = 5, 6
tCK
(AVG)
Reserved
ns
CWL = 7
tCK
(AVG)
ns
CWL = 8
tCK
(AVG)
Reserved
ns
CWL = 5, 6, 7
tCK
(AVG)
Reserved
ns
CWL = 8
tCK
(AVG)
ns
Supported CL settings
Supported CWL settings
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Notes
Reserved
2.5
3.3
1.875
<2.5
1.875
1.5
1.5
<2.5
<1.875
<1.875
1.25
<1.5
5, 6, 7, 8, 9, 10, 11
CK
5, 6, 7, 8
CK
1. The -125 speed grade is backward compatible with 1333, CL = 9 (-15E) and 1066, CL = 7
(-187E).
2. tREFI depends on TOPER.
3. The CL and CWL settings result in tCK requirements. When making a selection of tCK,
both CL and CWL requirement settings need to be fulfilled.
4. Reserved settings are not allowed.
73
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
13-13-13
Parameter
Symbol
Min
Max
tAA
13.91
20
tRCD
13.91
ns
tRP
13.91
ns
tRC
47.91
ns
tRAS
34
9 x tREFI
ns
3.0
3.3
ns
ns
CL = 9
CL = 10
CL = 11
CL = 12
CL = 13
CWL = 5
(AVG)
CWL = 6, 7, 8, 9
tCK
(AVG)
CWL = 5
tCK
(AVG)
ns
CWL = 6, 7, 8, 9
tCK
(AVG)
Reserved
ns
CWL = 5, 7, 8, 9
tCK
(AVG)
Reserved
ns
CWL = 6
tCK
(AVG)
ns
CWL = 5, 8, 9
tCK
(AVG)
ns
CWL = 6
tCK
(AVG)
ns
CWL = 7
tCK
(AVG)
Reserved
ns
CWL = 5, 6, 8, 9
tCK
(AVG)
Reserved
ns
CWL = 7
tCK
(AVG)
CWL = 5, 6, 9
tCK
(AVG)
CWL = 7
tCK
(AVG)
CWL = 8
tCK
(AVG)
CWL = 5, 6, 7
tCK
(AVG)
CWL = 8
tCK
(AVG)
CWL = 9
tCK
(AVG)
CWL = 5, 6, 7, 8
tCK
(AVG)
CWL = 9
tCK
CWL = 5, 6, 7, 8
tCK
CWL = 9
tCK
(AVG)
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Notes
tCK
Supported CL settings
Notes:
Unit
Reserved
2.5
3.3
1.875
<2.5
Reserved
1.875
1.5
<2.5
<1.875
Reserved
1.5
<1.875
Reserved
Reserved
ns
ns
ns
ns
ns
ns
Reserved
ns
Reserved
ns
(AVG)
Reserved
ns
(AVG)
Reserved
ns
ns
1.25
1.07
<1.5
<1.25
5, 6, 7, 8, 9, 10, 11, 13
CK
5, 6, 7, 8, 9
CK
1. The -107 speed grade is backward compatible with 1600, CL = 11 (-125); 1333, CL = 9
(-15E); and 1066, CL = 7 (-187E).
2. tREFI depends on TOPER.
3. The CL and CWL settings result in tCK requirements. When making a selection of tCK,
both CL and CWL requirement settings need to be fulfilled.
4. Reserved settings are not allowed.
74
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
14-14-14
Parameter
Symbol
Min
Max
tAA
13.09
20
tRCD
13.09
ns
tRP
13.09
ns
tRC
46.09
ns
tRAS
33
9 x tREFI
ns
3.0
3.3
ns
ns
CL = 9
CL = 10
CL = 11
CL = 12
CL = 13
CL = 14
CWL = 5
(AVG)
CWL = 6, 7, 8, 9
tCK
(AVG)
CWL = 5
tCK
(AVG)
ns
CWL = 6, 7, 8, 9
tCK
(AVG)
Reserved
ns
CWL = 5, 7, 8, 9
tCK
(AVG)
Reserved
ns
CWL = 6
tCK
(AVG)
ns
CWL = 5, 8, 9
tCK
(AVG)
ns
CWL = 6
tCK
(AVG)
ns
CWL = 7
tCK
(AVG)
Reserved
ns
CWL = 5, 6, 8, 9
tCK
(AVG)
Reserved
ns
CWL = 7
tCK
(AVG)
CWL = 5, 6, 9
tCK
(AVG)
CWL = 7
tCK
(AVG)
CWL = 8
tCK
(AVG)
CWL = 5, 6, 7
tCK
(AVG)
CWL = 8
tCK
(AVG)
CWL = 9
tCK
(AVG)
CWL = 5, 6, 7, 8
tCK
(AVG)
CWL = 9
tCK
CWL = 5, 6, 7, 8
tCK
CWL = 9
tCK
(AVG)
1.07
CWL = 5, 6, 7, 8, 9
tCK
(AVG)
CWL = 10
tCK
(AVG)
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Notes
tCK
Supported CL settings
Notes:
Unit
Reserved
2.5
3.3
1.875
<2.5
Reserved
1.875
1.5
<2.5
<1.875
Reserved
1.5
<1.875
Reserved
Reserved
ns
ns
ns
ns
ns
ns
Reserved
ns
Reserved
ns
(AVG)
Reserved
ns
(AVG)
Reserved
ns
<1.25
ns
Reserved
Reserved
ns
0.938
<1.07
ns
1.25
<1.5
CK
5, 6, 7, 8, 9
CK
1. The -093 speed grade is backward compatible with 1866, CL = 13 (-107); 1600, CL = 11
(-125); 1333, CL = 9 (-15E); and 1066, CL = 7 (-187E).
2. tREFI depends on TOPER.
3. The CL and CWL settings result in tCK requirements. When making a selection of tCK,
both CL and CWL requirement settings need to be fulfilled.
4. Reserved settings are not allowed.
75
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
TC 85C
76
147
175
194
209
222
232
241
249
257
263
269
tERR3per
tERR4per
tERR5per
tERR6per
tERR7per
tERR8per
tERR9per
tERR10per
tERR11per
tERR12per
tERRnper
3 cycles
4 cycles
5 cycles
6 cycles
7 cycles
8 cycles
9 cycles
10 cycles
11 cycles
12 cycles
n = 13, 14 . . . 49, 50
cycles
180
tERR2per
200
tJITcc,lck
DLL locking
0.43
tJITcc
(ABS)
DLL locked
tCL
Cycle-to-cycle jitter
0.43
tERRnper
180
160
242
237
231
224
217
209
200
188
175
157
132
215
210
205
200
193
186
177
168
155
140
118
0.43
0.43
140
160
215
210
205
200
193
186
177
168
155
140
118
188
184
180
175
169
163
155
147
136
122
103
0.43
0.43
242
237
231
224
217
209
200
188
175
157
132
0.43
0.43
tERRnper
269
263
257
249
241
232
222
209
194
175
147
140
120
70
188
184
180
175
169
163
155
147
136
122
103
60
(ABS)
60
tCH
70
70
0.53
70
80
0.47
0.53
MIN = tCK (AVG) MIN + tJITper MIN; MAX = tCK (AVG) MAX + tJITper
MAX
80
80
0.53
0.47
range allowed
0.53
(ABS)
80
90
0.47
0.47
tCK
90
90
0.53
0.53
7800
3900
0.47
0.47
tCK
8
8
90
0.53
0.53
7800
3900
100
0.47
8
8
tJITper,lck
7800
3900
Max
DDR3-1600
Min
DLL locked
(AVG)
tCL
0.47
8
8
Max
DDR3-1333
Min
DLL locking
(AVG)
3900
7800
Clock Timing
Max
DDR3-1066
Min
tJITper
(AVG)
tCH
(DLL_DIS)
TC = >85C to 95C
tCK
Max
DDR3-800
Min
Symbol
tCK
Parameter
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
(AVG)
tCK
(AVG)
tCK
ps
ps
ps
CK
CK
ns
ns
ns
Unit
17
17
17
17
17
17
17
17
17
17
17
17
16
16
15
14
13
13
12
12
10, 11
42
9, 42
Notes
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
VREF @ 1 V/ns
Base (specification)
VREF @ 1 V/ns
Base (specification)
VREF @ 1 V/ns
Base (specification)
VREF @ 1 V/ns
Base (specification)
77
490
200
100
250
75
200
25
0.25
0.45
0.45
0.2
tDQSS
tDQSL
tDQSH
tDSS
400
400
200
600
0.38
0.9
0.3
400
1
tWPRE
tWPST
tDQSCK
tDQSCK
0.3
0.9
0.2
0.2
0.45
0.45
0.25
10
400
300
0.2
tDSH
0.55
0.55
0.25
800
tLZDQ
0.38
tQH
tHZDQ
(DLL_DIS)
Min
DQ Output Timing
600
250
150
275
125
250
75
Max
10
300
0.55
0.55
0.25
300
300
150
Max
DDR3-1066
DQ Input Timing
Min
tDQSQ
tDIPW
(DC100)
tDH
(AC135)
tDS
(AC150)
tDS
(AC175)
tDS
Symbol
DDR3-800
Parameter
255
0.3
0.9
0.2
0.2
0.45
0.45
0.25
500
0.38
400
165
65
180
30
Min
10
255
0.55
0.55
0.25
250
250
125
Max
DDR3-1333
225
0.3
0.9
0.18
0.18
0.45
0.45
0.27
450
0.38
360
145
45
160
10
Min
10
225
0.55
0.55
0.27
225
225
100
Max
DDR3-1600
ns
ps
CK
CK
CK
CK
CK
CK
CK
ps
ps
(AVG)
tCK
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Unit
26
23
25
25
25
22, 23
22, 23
21
41
19, 20
18, 19
19, 20
18, 19
19, 20
18, 19,
44
19, 20
18, 19,
44
Notes
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
0.3
512
200
tRPST
tDLLK
tIS
78
VREF @ 1 V/ns
Base (specification)
VREF @ 1 V/ns
0.3
0.9
300
Note 27
Note 24
300
620
240
140
340
190
240
65
512
tFAW
Four ACTIVATE
windows
Note 27
Note 24
225
225
45
30
tWTR
50
37.5
40
30
50
40
560
220
120
320
170
220
45
512
0.3
0.9
450
0.40
0.40
Max
DDR3-1600
Min
tWR
tRRD
tRC
tRC
tRCD
780
300
200
425
275
300
tRAS
125
512
Note 27
Note 24
250
250
Max
900
375
275
500
350
375
0.3
0.9
500
0.40
0.40
Min
Note 27
Note 24
600
Max
tRP
tRCD
400
400
0.38
0.38
Min
DDR3-1333
tIPW
(DC100)
tIH
(AC150)
tIS
0.9
tRPRE
(AC175)
Base (specification)
800
tHZDQS
Max
DDR3-1066
0.38
0.38
tQSH
tQSL
Min
Symbol
DDR3-800
Parameter
CK
ns
ns
ns
CK
CK
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
CK
CK
CK
ps
ps
CK
CK
Unit
31, 34
31, 32,
33,34
31
31
31
31
31, 43
31, 32
31
31
41
20, 30
29, 30
20, 30
29, 30,
44
20, 30
29, 30,
44
28
23, 27
23, 24
22, 23
22, 23
21
21
Notes
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
79
tRPS
tIOZ
Maximum average
periodic refresh
Maximum refresh
period
2Gb
4Gb
8Gb
tRFC
tRFC
tRFC
TC > 85C
Self Refresh Timing
3.9 (32ms/8192)
32 (2X)
7.8 (64ms/8192)
tREFI
64 (1X)
Refresh Timing
TC > 85C
1Gb
tRFC
TC 85C
TC 85C
REFRESH-to-ACTIVATE or REFRESH
command period
64
64
256
tVDDPR
tXPR
64
256
64
256
256
512
tZQCS
512
tZQoper
512
tZQinit
512
tMPRR
Calibration Timing
tMRD
tMOD
MIN = WR +
tRP/tCK
Max
DDR3-1600
Min
Max
Min
tDAL
Max
Min
tCCD
Max
DDR3-1333
Min
DDR3-1066
tRTP
Symbol
DDR3-800
READ-to-PRECHARGE time
Parameter
ms
ms
ns
ns
ns
ns
ns
ms
ms
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
Unit
36
36
36
36
35
31, 32
Notes
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
80
tANPD
+ tXPDLL
MIN = 1
MIN = 1
MIN = 1
MIN = tMOD (MIN)
MIN = RL + 4 + 1
MIN = WL + 4 + tWR/tCK (AVG)
MIN = WL + 2 + tWR/tCK (AVG)
tACTPDEN
tPRPDEN
tREFPDEN
tMRSPDEN
tRDPDEN
tWRPDEN
tWRPDEN
WRITE command to
power-down entry
PDX
Greater of 3CK
or 5ns
Max
WL - 1CK
tANPD
PDE
Greater of 3CK
or 5.625ns
tPD
Greater of 3CK
or 5.625ns
Power-Down Timing
Greater of 3CK
or 7.5ns
tCPDED
tCKSRX
tCKSRE
Min
Max
Min
tCKESR
Max
Minimum CKE low pulse width for self refresh entry to self refresh exit timing
Min
DDR3-1600
tXSDLL
Max
DDR3-1333
Min
DDR3-1066
Symbol
DDR3-800
tXS
Parameter
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
Unit
37
28
Notes
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
81
ODTLcwn8
0.7
0.3
40
25
325
tWLDQSEN
tWLS
245
25
40
0.3
0.7
195
25
40
0.3
6CK + ODTLoff
4CK + ODTLoff
WL - 2CK
tWLMRD
tADC
ODTLcnw
ODTLcwn4
ODTH4
ODTH8
0.3
tAOFPD
0.7
250
0.3
300
CWL + AL - 2CK
0.7
300
CWL + AL - 2CK
0.3
tAOF
400
ODT Timing
tAONPD
400
ODTLoff
ODTLon
Max
Min
Max
DDR3-1600
0.7
0.7
250
165
25
40
0.3
0.3
225
0.7
0.7
225
Min
tXPDLL
tXP
Max
MIN = WL + 2 + WR + 1
DEN
DEN
Min
tWRAP-
Max
MIN = WL + 4 + WR + 1
Min
tWRAP-
DDR3-1333
Symbol
DDR3-1066
DDR3-800
Parameter
ps
CK
CK
CK
CK
CK
CK
CK
CK
ns
ns
CK
ps
CK
CK
CK
CK
CK
CK
Unit
39
40
38
39, 40
23, 38
40
38
28
Notes
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Min
325
0
0
Symbol
tWLH
tWLO
tWLOE
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Max
DDR3-800
Parameter
245
Min
Max
DDR3-1066
195
Min
Max
DDR3-1333
165
Min
7.5
Max
DDR3-1600
ns
ns
ps
Unit
Notes
82
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
83
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
84
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
38.
39.
40.
41.
42.
43.
44.
(MIN) is satisfied, there are cases where additional time such as tXPDLL (MIN)
is required.
ODT turn-on time MIN is when the device leaves High-Z and ODT resistance begins to
turn on. ODT turn-on time maximum is when the ODT resistance is fully on. The ODT
reference load is shown in Figure 21 (page 54). Designs that were created prior to JEDEC
tightening the maximum limit from 9ns to 8.5ns will be allowed to have a 9ns maximum.
Half-clock output parameters must be derated by the actual tERR10per and tJITdty when
input clock jitter is present. This results in each parameter becoming larger. The parameters tADC (MIN) and tAOF (MIN) are each required to be derated by subtracting both
tERR10per (MAX) and tJITdty (MAX). The parameters tADC (MAX) and tAOF (MAX) are
required to be derated by subtracting both tERR10per (MAX) and tJITdty (MAX).
ODT turn-off time minimum is when the device starts to turn off ODT resistance. ODT
turn-off time maximum is when the DRAM buffer is in High-Z. The ODT reference load is
shown in Figure 22 (page 57). This output load is used for ODT timings (see Figure 29
(page 68)).
Pulse width of a input signal is defined as the width between the first crossing of
VREF(DC) and the consecutive crossing of VREF(DC).
Should the clock rate be larger than tRFC (MIN), an AUTO REFRESH command should
have at least one NOP command between it and another AUTO REFRESH command. Additionally, if the clock rate is slower than 40ns (25 MHz), all REFRESH commands should
be followed by a PRECHARGE ALL command.
DRAM devices should be evenly addressed when being accessed. Disproportionate accesses to a particular row address may result in a reduction of REFRESH characteristics or
product lifetime.
When two VIH(AC) values (and two corresponding VIL(AC) values) are listed for a specific
speed bin, the user may choose either value for the input AC level. Whichever value is
used, the associated setup time for that AC level must also be used. Additionally, one
VIH(AC) value may be used for address/command inputs and the other VIH(AC) value may
be used for data inputs.
For example, for DDR3-800, two input AC levels are defined: VIH(AC175),min and
VIH(AC150),min (corresponding VIL(AC175),min and VIL(AC150),min). For DDR3-800, the address/
command inputs must use either VIH(AC175),min with tIS(AC175) of 200ps or VIH(AC150),min
with tIS(AC150) of 350ps; independently, the data inputs must use either VIH(AC175),min
with tDS(AC175) of 75ps or VIH(AC150),min with tDS(AC150) of 125ps.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
85
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
86
120
100
tJITcc
tJITcc,lck
DLL locking
0.43
0.43
3900
7800
Max
50
60
tCK
40
50
0.47
0.47
0.43
0.43
3900
7800
Max
120
100
40
50
0.53
0.53
range allowed ns
MIN =
(AVG) MIN +
tJITper MIN; MAX =
tCK (AVG) MAX +
tJITper MAX ps
0.53
0.53
DDR3-2133
tCK
Min
DLL locked
(ABS)
tCL
Cycle-to-cycle jitter
(ABS)
tCH
(ABS)
tCK
60
50
tJITper,lck
0.47
0.47
DLL locked
8
8
DLL locking
(AVG)
tCL
(AVG)
DDR3-1866
Clock Timing
Min
tJITper
(AVG)
tCH
(DLL_DIS)
TC = >85C to 95C
TC = 0C to 85C
tCK
Symbol
tCK
Parameter
Table 56: Electrical Characteristics and AC Operating Conditions for Speed Extensions
ps
ps
(AVG)
tCK
(AVG)
tCK
ps
ps
CK
CK
ns
ns
Unit
16
16
15
14
13
13
12
12
10, 11
42
9, 42
Notes
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
tERR9per
tERR10per
8 cycles
9 cycles
10 cycles
11 cycles
87
0.38
tDQSS
0.27
134
132
128
125
121
116
111
105
97
87
74
Max
195
195
85
0.27
ps
0.27
360
0.38
280
105
55
120.5
53
0.27
180
180
75
390
tLZDQ
tHZDQ
tQH
DQ Output Timing
tDQSQ
320
120
70
135
68
(DC100)
tDH
(AC135)
tERRnper
-134
-132
-128
-125
-121
-116
-111
-105
-97
-87
-74
Min
DDR3-2133
161
158
154
150
145
139
133
126
117
105
88
Max
tERRnper
DDR3-1866
DQ Input Timing
VREF @ 2 V/ns
Base (specification)
@ 2 V/ns
VREF @ 2 V/ns
Base (specification)
@ 2 V/ns
tDS
tDIPW
tERR8per
7 cycles
161
150
154
tERR7per
tERRnper
139
145
tERR6per
6 cycles
12 cycles
133
tERR5per
4 cycles
5 cycles
n = 13, 14 . . . 49, 50
cycles
117
126
tERR4per
3 cycles
158
105
tERR3per
tERR12per
88
tERR11per
Min
Symbol
tERR2per
Parameter
Table 56: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
CK
ps
ps
(AVG)
tCK
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Unit
25
22, 23
22, 23
21
41
19, 20
18, 19
19, 20
18, 19
17
17
17
17
17
17
17
17
17
17
17
17
Notes
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
0.45
0.45
0.18
0.18
0.9
0.3
195
1
0.40
0.40
tDQSL
tDQSH
tDSS
tDSH
tWPRE
tWPST
tDQSCK
tDQSCK
(DLL_DIS)
tQSH
tQSL
88
0.9
tHZDQS
tRPRE
VREF @ 1 V/ns
Base (specification)
tRAS
tRCD
tRP
tIPW
(DC100)
tIH
(AC125)
tIS
65
tIS
(AC135)
512
tDLLK
0.55
0.55
Max
Note 27
Note 24
195
195
10
195
535
200
100
275
150
200
470
195
95
260
135
195
60
512
0.3
0.9
360
0.40
0.40
180
0.3
0.9
0.18
0.18
0.45
0.45
Min
tRAS
tRP
180
180
10
180
0.55
0.55
Max
Note 27
Note 24
DDR3-2133
tRPST
390
tLZDQS
DDR3-1866
Min
Symbol
Parameter
Table 56: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
CK
CK
CK
ps
ps
CK
CK
ns
ps
CK
CK
CK
CK
CK
CK
Unit
31, 32
31
31
41
20, 30
29, 30
20, 30
29, 30,
44
20, 30
29, 30,
44
28
23, 27
23, 24
22, 23
22, 23
21
21
26
23
25
25
Notes
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
25
89
MIN = n/a
MAX = max(512nCK, 640ns)
MIN = n/a
MAX = max(256nCK, 320ns)
tMPRR
tZQinit
tZQoper
tVDDPR
tRPS
tIOZ
MIN = n/a
MAX = max(64nCK, 80ns) tZQCS
tXPR
tMOD
Calibration Timing
tMRD
tDAL
READ-to-PRECHARGE time
tCCD
tWTR
35
tWR
27
ns
ms
ms
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
ns
ns
ns
tFAW
Four ACTIVATE
windows
35
CK
CK
ns
Unit
Max
Min
tRRD
Max
See Speed Bin Tables (page 71) for tRC
Min
DDR3-2133
tRC
Symbol
DDR3-1866
Parameter
Table 56: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
35
31, 32
31, 34
31, 32,
33
31
31
31
31
31, 43
Notes
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
TC 85C
4Gb
8Gb
tRFC
tRFC
Min
90
tCKSRX
PDX
+ tXPDLL
CK
tANPD
CK
WL - 1CK
tANPD
CK
CK
tPD
CK
CK
CK
CK
CK
CK
CK
ms
ms
ns
ns
ns
ns
Unit
MIN = 2;
MAX = n/a
Max
tCPDED
Power-Down Timing
tCKSRE
(MIN)
tCKESR
Minimum CKE low pulse width for self refresh entry to self refresh exit timing
tCKE
3.9 (32ms/8192)
7.8 (64ms/8192)
32 (2X)
64 (1X)
Max
tREFI
2Gb
tRFC
Refresh Timing
Min
DDR3-2133
TC > 85C
TC 85C
TC > 85C
1Gb
tRFC
Symbol
DDR3-1866
tXS
Maximum average
periodic refresh
Maximum refresh
period
REFRESH-to-ACTIVATE or REFRESH
command period
Parameter
Table 56: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
28
36
36
36
36
Notes
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Min
Max
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
MIN = WL + 4 + WR + 1
tWRAP-
BC4MRS
91
ODTH8
tAOFPD
0.3
MIN = 2; MAX = 8.5
0.7
180
0.3
tAOF
195
CWL + AL - 2CK
CWL + AL - 2CK
tAONPD
195
tAON
ODTL off
ODT Timing
tXPDLL
ODTL on
MIN = WL + 2 + WR + 1
DDR3-2133
tXP
DEN
tWRAP-
BC4MRS
DEN
MIN = WL + 2 +
tWR/tCK (AVG)
tWRPDEN
WRITE command to
power-down entry
MIN = WL + 4 +
tWR/tCK (AVG)
tWRPDEN
MIN = RL + 4 + 1
tRDPDEN
tMOD
MIN =
MIN = 2
tREFPDEN
MIN = 2
tPRPDEN
Min
MIN = 2
tACTPDEN
Symbol
DDR3-1866
Parameter
0.7
180
Max
Table 56: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
CK
ns
ns
CK
ps
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
Unit
40
38
39, 40
23, 38
40
38
28
37
Notes
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
0.3
40
25
140
140
tWLS
tWLH
92
0
0
tWLO
tWLOE
Min
0.7
7.5
25
40
0.3
125
125
6CK + ODTLoff
4CK + ODTLoff
WL - 2CK
Max
DDR3-1866
Min
tWLMRD
ODTLcwn8
ODTLcnw
ODTLcwn4
ODTH4
Symbol
Parameter
0.7
Max
Table 56: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
ns
ns
ps
ps
CK
CK
CK
CK
CK
CK
CK
Unit
39
Notes
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
93
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
94
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
95
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
800
1066
1333
1600
1866
2133
Unit
Reference
AC175)
200
125
65
45
ps
VIH(AC)/VIL(AC)
AC150)
350
275
190
170
ps
VIH(AC)/VIL(AC)
AC135)
65
60
ps
VIH(AC)/VIL(AC)
tIS(base,
AC125)
150
135
ps
VIH(AC)/VIL(AC)
tIH(base,
DC100)
275
200
140
120
100
95
ps
VIH(DC)/VIL(DC)
tIS(base,
tIS(base,
tIS(base,
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
96
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
tIS
tIH
tIS
tIH
tIS
tIH
tIS
tIH
tIS
2.0
88
50
88
50
88
50
96
58
1.5
59
34
59
34
59
34
67
42
1.0
0.9
0.8
10
10
0.7
11
16
11
16
0.6
17
26
17
0.5
35
40
0.4
62
60
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
tIH
tIH
104
66
75
50
16
10
11
16
26
17
35
40
62
60
1.2 V/ns
tIH
tIS
112
74
83
58
16
24
14
12
10
26
35
40
62
60
1.0 V/ns
tIH
tIS
tIH
120
84
128
100
91
68
99
84
24
32
34
40
50
22
20
30
30
38
46
18
14
26
24
34
40
13
21
18
29
34
18
10
15
23
24
27
32
19
24
11
16
10
54
52
46
44
38
36
30
26
22
10
tIS
tIH
tIS
tIH
tIS
tIH
tIS
tIH
tIS
tIH
tIH
tIH
tIS
tIH
tIS
tIH
2.0
75
50
75
50
75
50
83
58
91
66
99
74
107
84
115
100
1.5
50
34
50
34
50
34
58
42
66
50
74
58
82
68
90
84
1.0
16
16
24
24
32
34
40
50
0.9
16
12
24
20
32
30
40
46
0.8
10
10
10
16
24
14
32
24
40
40
0.7
16
16
16
16
24
32
18
40
34
0.6
26
26
26
18
15
10
23
31
39
24
0.5
10
40
10
40
10
40
32
24
14
16
22
30
10
0.4
25
60
25
60
25
60
17
52
44
36
26
15
10
4.0 V/ns
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
3.0 V/ns
2.0 V/ns
1.8 V/ns
97
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
tIS
tIH
tIS
tIH
tIS
tIH
tIS
tIH
tIS
tIH
tIH
tIH
tIS
tIH
tIS
tIH
2.0
68
50
68
50
68
50
76
58
84
66
92
74
100
84
108
100
1.5
45
34
45
34
45
34
53
42
61
50
69
58
77
68
85
84
1.0
16
16
24
24
32
34
40
50
0.9
10
18
12
26
20
34
30
42
46
0.8
10
10
10
11
19
27
14
35
24
43
40
0.7
16
16
16
14
22
30
38
18
46
34
0.6
26
26
26
17
18
25
10
33
41
49
24
0.5
40
40
40
13
32
21
24
29
16
37
45
10
0.4
60
60
60
52
14
44
22
36
30
26
38
10
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
tIS
tIH
tIS
tIH
tIS
tIH
tIS
tIH
tIS
tIH
tIH
tIH
tIS
tIH
tIS
tIH
2.0
63
50
63
50
63
50
71
58
79
66
87
74
95
84
103
100
1.5
42
34
42
34
42
34
50
42
58
50
66
58
74
68
82
84
1.0
16
16
24
24
32
34
40
50
0.9
12
20
12
28
20
36
30
44
46
0.8
10
10
10
14
22
30
14
38
24
45
40
0.7
11
16
11
16
11
16
19
27
35
43
18
51
34
0.6
16
26
16
26
16
26
24
18
32
10
40
48
56
24
0.5
15
40
15
40
15
40
23
32
31
24
39
16
47
55
10
0.4
13
60
13
60
13
60
21
52
29
44
37
36
45
26
53
10
4.0 V/ns
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
3.0 V/ns
2.0 V/ns
1.8 V/ns
98
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Table 62: Minimum Required Time tVAC Above VIH(AC) or Below VIL(AC)for Valid Transition
Slew Rate (V/ns)
tVAC
at 175mV (ps)
tVAC
at 150mV (ps)
tVAC
at 135mV (ps)
tVAC
at 125mV (ps)
>2.0
75
175
168
173
2.0
57
170
168
173
1.5
50
167
145
152
1.0
38
130
100
110
0.9
34
113
85
96
0.8
29
93
66
79
0.7
22
66
42
56
0.6
Note 1
30
10
27
0.5
Note 1
Note 1
Note 1
Note 1
<0.5
Note 1
Note 1
Note 1
Note 1
Note:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
1. Rising input signal shall become equal to or greater than VIH(ac) level and Falling input
signal shall become equal to or less than VIL(ac) level.
99
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
tIH
tIS
tIH
CK
CK#
DQS#
DQS
VDDQ
tVAC
VIH(AC)min
VREF to AC
region
VIH(DC)min
Nominal
slew rate
VREF(DC)
Nominal
slew rate
VIL(DC)max
VREF to AC
region
VIL(DC)max
tVAC
VSS
TF
Note:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
TR
VREF(DC) - VIL(AC)max
TF
VIH(AC)min - VREF(DC)
TR
1. The clock and the strobe are drawn on different time scales.
100
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
tIS
tIH
tIH
CK
CK#
DQS#
DQS
VDDQ
VIH(AC)min
VIH(DC)min
Nominal
slew rate
DC to VREF
region
VREF(DC)
Nominal
slew rate
DC to VREF
region
VIL(DC)max
VIL(AC)max
VSS
TF
TR
VREF(DC) - VIL(DC)max
Hold slew rate
rising signal =
TR
Note:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
VIH(DC)min - VREF(DC)
Hold slew rate
falling signal =
TF
1. The clock and the strobe are drawn on different time scales.
101
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
tIS
tIH
tIH
CK
CK#
DQS#
DQS
VDDQ
Nominal
line
tVAC
VIH(AC)min
VREF to AC
region
VIH(DC)min
Tangent
line
VREF(DC)
Tangent
line
VIL(DC)max
VREF to AC
region
VIL(DC)max
Nominal
line
tVAC
TR
VSS
Tangent line (VIH(DC)min - VREF(DC))
Setup slew rate
rising signal =
TR
TF
Note:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
1. The clock and the strobe are drawn on different time scales.
102
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
tIS
tIH
tIS
tIH
CK
CK#
DQS#
DQS
VDDQ
VIH(AC)min
Nominal
line
VIH(DC)min
DC to VREF
region
Tangen t
line
VREF(DC)
DC to VREF
region
Tangen t
line
Nominal
line
VIL( DC)max
VIL( AC)max
VSS
TR
TR
Note:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
1. The clock and the strobe are drawn on different time scales.
103
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
800
1066
1333
1600
1866
2133
Unit
Reference
(base) AC175
75
25
ps
VIH(AC)/VIL(AC)
(base) AC150
125
75
30
10
ps
VIH(AC)/VIL(AC)
(base) AC135
165
115
60
40
68
53
ps
VIH(AC)/VIL(AC)
(base) DC100
150
100
65
45
70
55
ps
VIH(DC)/VIL(DC)
V/ns
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
104
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
DQ Slew
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Rate V/ns DS DH DS DH DS DH DS DH DS DH DS DH DS DH DS tDH
2.0
88
50
88
50
88
50
1.5
59
34
59
34
59
34
67
42
1.0
16
16
14
12
22
20
10
10
18
14
26
24
13
21
18
29
34
10
15
23
24
11
16
10
30
26
22
10
0.9
0.8
0.7
0.6
0.5
0.4
3.0 V/ns
2.0 V/ns
DQ Slew
Rate V/ns
tDS
tDH
tDS
tDH
tDS
tDH
2.0
75
50
75
50
75
50
1.5
50
34
50
34
50
1.0
0.9
0.8
0.7
1.8 V/ns
tDS
tDH
34
58
42
10
tDH
16
16
16
16
0.6
0.5
0.4
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
1.6 V/ns
tDS
105
1.4 V/ns
tDS
tDH
12
24
20
24
14
1.2 V/ns
tDS
tDH
32
24
1.0 V/ns
tDS
tDH
16
24
32
18
40
34
15
10
23
31
39
24
14
16
22
30
10
26
15
10
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
3.0 V/ns
2.0 V/ns
DQ Slew
Rate V/ns
tDS
tDH
tDS
tDH
tDS
tDH
2.0
68
50
68
50
68
50
1.5
45
34
45
34
45
1.0
0.9
0.8
0.7
1.8 V/ns
tDS
tDH
34
53
42
10
tDH
16
16
10
18
11
19
14
0.6
0.5
0.4
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
1.6 V/ns
tDS
106
1.4 V/ns
tDS
tDH
12
26
20
27
14
1.2 V/ns
tDS
tDH
35
24
1.0 V/ns
tDS
tDH
22
30
38
18
46
34
25
19
33
41
49
24
29
16
37
45
10
30
26
38
10
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
29
23
3.5
3.0
107
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.5
2.0
2.5
34
4.0
17
21
25
tDH
tDS
8.0 V/ns
14
23
29
34
tDS
10
17
21
25
tDH
7.0 V/ns
14
23
29
34
tDS
10
17
21
25
tDH
6.0 V/ns
23
14
23
29
tDS
17
10
17
21
tDH
5.0 V/ns
68
23
14
23
tDS
50
17
10
17
tDH
4.0 V/ns
66
68
23
14
tDS
54
50
17
10
tDH
3.0 V/ns
64
66
68
23
tDS
60
54
50
17
tDH
2.0 V/ns
53
56
58
60
15
tDS
59
52
46
42
19
tDH
1.8 V/ns
43
45
48
50
52
tDS
61
51
40
38
34
tDH
1.6 V/ns
39
35
37
40
42
tDS
66
53
43
36
30
tDH
1.4 V/ns
38
31
27
29
32
tDS
76
56
43
33
26
tDH
1.2 V/ns
30
23
19
21
tDS
60
40
27
17
tDH
1.0 V/ns
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Table 68: Required Minimum Time tVAC Above VIH(AC) (Below VIL(AC)) for Valid DQ Transition
Slew
Rate
(V/ns)
tVAC
at 175mV (ps)
DDR3-800/1066
tVAC
tVAC
at 150mV (ps)
at 135mV (ps)
>2.0
75
105
113
2.0
57
105
113
93
73
1.5
50
80
90
70
50
1.0
38
30
45
25
0.9
34
13
30
Note 1
Note 1
0.8
29
Note 1
11
Note 1
Note 1
0.7
Note 1
Note 1
Note 1
Note 1
Note 1
0.6
Note 1
Note 1
Note 1
Note 1
Note 1
0.5
Note 1
Note 1
Note 1
Note 1
Note 1
<0.5
Note 1
Note 1
Note 1
Note 1
Note 1
Note:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
93
DDR3-2133
73
1. Rising input signal shall become equal to or greater than VIH(ac) level and Falling input
signal shall become equal to or less than VIL(ac) level.
108
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
CK#
DQS#
DQS
tDS
tDH
tDS
tDH
VDDQ
tVAC
VIH(AC)min
VREF to AC
region
VIH(DC)min
Nominal
slew rate
VREF(DC)
Nominal
slew rate
VIL(DC)max
VREF to AC
region
VIL(AC)max
tVAC
VSS
TF
Setup slew rate
=
falling signal
Note:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
TR
VIH(AC)min - VREF(DC)
Setup slew rate
=
rising signal
TR
VREF(DC) - VIL(AC)max
TF
1. The clock and the strobe are drawn on different time scales.
109
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
CK#
DQS#
DQS
tDS
tDH
tDS
tDH
VDDQ
VIH(AC)min
VIH(DC)min
Nominal
slew rate
DC to VREF
region
VREF(DC)
Nominal
slew rate
DC to VREF
region
VIL(DC)max
VIL(AC)max
VSS
TR
VREF(DC) - VIL(DC)max
Hold slew rate
rising signal =
TR
Note:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
TF
VIL(DC)min - VREF(DC)
Hold slew rate
falling signal =
TF
1. The clock and the strobe are drawn on different time scales.
110
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
CK#
DQS#
DQS
tDS
tDH
tDS
tDH
VDDQ
Nominal
line
tVAC
VIH(AC)min
VREF to AC
region
VIH(DC)min
Tangent
line
VREF(DC)
Tangent
line
VIL(DC)max
VREF to AC
region
VIL(AC)max
Nominal
line
TR
tVAC
VSS
Note:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
1. The clock and the strobe are drawn on different time scales.
111
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
CK#
DQS#
DQS
tDS
tDH
tDS
tDH
VDDQ
VIH(AC)min
Nominal
line
VIH(DC)min
DC to VREF
region
Tangent
line
VREF(DC)
DC to VREF
region
Tangent
line
Nominal
line
VIL(DC)max
VIL(AC)max
VSS
TR
Note:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
TF
TR
TF
1. The clock and the strobe are drawn on different time scales.
112
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Prev.
Cycle
MRS
BA
REFRESH
REF
SRE
SRX
6, 7
H
V
Function
Single-bank PRECHARGE
Next
BA
Cycle CS# RAS# CAS# WE# [2:0]
An
A12
A10
A[11,
9:0] Notes
OP code
PRE
BA
PREA
Bank ACTIVATE
ACT
BA
WRITE
BL8MRS,
BC4MRS
WR
BA
RFU
CA
BC4OTF
WRS4
BA
RFU
CA
BL8OTF
WRS8
BA
RFU
CA
BL8MRS,
BC4MRS
WRAP
BA
RFU
CA
BC4OTF
WRAPS4
BA
RFU
CA
BL8OTF
WRAPS8
BA
RFU
CA
BL8MRS,
BC4MRS
RD
BA
RFU
CA
BC4OTF
RDS4
BA
RFU
CA
BL8OTF
RDS8
BA
RFU
CA
BL8MRS,
BC4MRS
RDAP
BA
RFU
CA
BC4OTF
RDAPS4
BA
RFU
CA
BL8OTF
BA
RFU
CA
WRITE
with auto
precharge
READ
READ
with auto
precharge
RDAPS8
NO OPERATION
NOP
Device DESELECTED
DES
10
Power-down entry
PDE
Power-down exit
PDX
6, 11
12
ZQ CALIBRATION LONG
ZQCL
ZQ CALIBRATION SHORT
ZQCS
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
1. Commands are defined by the states of CS#, RAS#, CAS#, WE#, and CKE at the rising
edge of the clock. The MSB of BA, RA, and CA are device-, density-, and configurationdependent.
113
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
114
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
State3
Power-down
Action5
Dont Care
Maintain power-down
DES or NOP
Power-down exit
Self refresh
Dont Care
DES or NOP
Bank(s) active
DES or NOP
Reading
DES or NOP
Power-down entry
Writing
DES or NOP
Power-down entry
Precharging
DES or NOP
Power-down entry
Refreshing
DES or NOP
DES or NOP
REFRESH
Self refresh
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Notes
1. All states and sequences not shown are illegal or reserved unless explicitly described
elsewhere in this document.
2. tCKE (MIN) means CKE must be registered at multiple consecutive positive clock edges.
CKE must remain at the valid input level the entire time it takes to achieve the required
number of registration clocks. Thus, after any CKE transition, CKE may not transition
from its valid level during the time period of tIS + tCKE (MIN) + tIH.
3. Current state = The state of the DRAM immediately prior to clock edge n.
4. CKE (n) is the logic state of CKE at clock edge n; CKE (n - 1) was the state of CKE at the
previous clock edge.
5. COMMAND is the command registered at the clock edge (must be a legal command as
defined in Table 69 (page 113)). Action is a result of COMMAND. ODT does not affect
the states described in this table and is not listed.
6. Idle state = All banks are closed, no data bursts are in progress, CKE is HIGH, and all timings from previous operations are satisfied. All self refresh exit and power-down exit parameters are also satisfied.
115
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Commands
DESELECT
The DESELT (DES) command (CS# HIGH) prevents new commands from being executed by the DRAM. Operations already in progress are not affected.
NO OPERATION
The NO OPERATION (NOP) command (CS# LOW) prevents unwanted commands from
being registered during idle or wait states. Operations already in progress are not affected.
ZQ CALIBRATION LONG
The ZQ CALIBRATION LONG (ZQCL) command is used to perform the initial calibration during a power-up initialization and reset sequence (see Figure 48 (page 132)).
This command may be issued at any time by the controller, depending on the system
environment. The ZQCL command triggers the calibration engine inside the DRAM. After calibration is achieved, the calibrated values are transferred from the calibration engine to the DRAM I/O, which are reflected as updated RON and ODT values.
The DRAM is allowed a timing window defined by either tZQinit or tZQoper to perform
a full calibration and transfer of values. When ZQCL is issued during the initialization
sequence, the timing parameter tZQinit must be satisfied. When initialization is complete, subsequent ZQCL commands require the timing parameter tZQoper to be satisfied.
ZQ CALIBRATION SHORT
The ZQ CALIBRATION SHORT (ZQCS) command is used to perform periodic calibrations to account for small voltage and temperature variations. A shorter timing window
is provided to perform the reduced calibration and transfer of values as defined by timing parameter tZQCS. A ZQCS command can effectively correct a minimum of 0.5% RON
and RTT impedance error within 64 clock cycles, assuming the maximum sensitivities
specified in Table 41 (page 63) and Table 42 (page 63).
ACTIVATE
The ACTIVATE command is used to open (or activate) a row in a particular bank for a
subsequent access. The value on the BA[2:0] inputs selects the bank, and the address
provided on inputs A[n:0] selects the row. This row remains open (or active) for accesses
until a PRECHARGE command is issued to that bank.
A PRECHARGE command must be issued before opening a different row in the same
bank.
READ
The READ command is used to initiate a burst read access to an active row. The address
provided on inputs A[2:0] selects the starting column address, depending on the burst
length and burst type selected (see Burst Order table for additional information). The
value on input A10 determines whether auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst. If auto
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
116
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
READ with
auto
precharge
Symbol
Prev.
Cycle
Next
BA
Cycle CS# RAS# CAS# WE# [2:0]
An
A12
A10
A[11,
9:0]
BL8MRS,
BC4MRS
RD
BA
RFU
CA
BC4OTF
RDS4
BA
RFU
CA
BL8OTF
RDS8
BA
RFU
CA
BL8MRS,
BC4MRS
RDAP
BA
RFU
CA
BC4OTF
RDAPS4
BA
RFU
CA
BL8OTF
RDAPS8
BA
RFU
CA
WRITE
The WRITE command is used to initiate a burst write access to an active row. The value
on the BA[2:0] inputs selects the bank. The value on input A10 determines whether auto
precharge is used. The value on input A12 (if enabled in the MR) when the WRITE command is issued determines whether BC4 (chop) or BL8 is used.
Input data appearing on the DQ is written to the memory array subject to the DM input
logic level appearing coincident with the data. If a given DM signal is registered LOW,
the corresponding data will be written to memory. If the DM signal is registered HIGH,
the corresponding data inputs will be ignored and a WRITE will not be executed to that
byte/column location.
Table 72: WRITE Command Summary
CKE
Function
WRITE
WRITE with
auto
precharge
Symbol
Prev.
Cycle
Next
BA
Cycle CS# RAS# CAS# WE# [2:0]
An
A12
A10
A[11,
9:0]
BL8MRS,
BC4MRS
WR
BA
RFU
CA
BC4OTF
WRS4
BA
RFU
CA
BL8OTF
WRS8
BA
RFU
CA
BL8MRS,
BC4MRS
WRAP
BA
RFU
CA
BC4OTF
WRAPS4
BA
RFU
CA
BL8OTF
WRAPS8
BA
RFU
CA
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
117
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
REFRESH
The REFRESH command is used during normal operation of the DRAM and is analogous to CAS#-before-RAS# (CBR) refresh or auto refresh. This command is nonpersistent, so it must be issued each time a refresh is required. The addressing is generated by
the internal refresh controller. This makes the address bits a Dont Care during a REFRESH command. The DRAM requires REFRESH cycles at an average interval of 7.8s
(maximum when T C 85C or 3.9s maximum when T C 95C). The REFRESH period
begins when the REFRESH command is registered and ends tRFC (MIN) later.
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight REFRESH commands can be posted to any given DRAM, meaning that the maximum absolute interval
between any REFRESH command and the next REFRESH command is nine times the
maximum average interval refresh rate. Self refresh may be entered with up to eight REFRESH commands being posted. After exiting self refresh (when entered with posted
REFRESH commands), additional posting of REFRESH commands is allowed to the extent that the maximum number of cumulative posted REFRESH commands (both preand post-self refresh) does not exceed eight REFRESH commands.
At any given time, a maximum of 16 REFRESH commands can be issued within
2 x tREFI.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
118
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
T2
T1
CK#
CK
tCK
T3
tCH
T4
Ta1
Valid 5
NOP1
PRE
Tb0
Tb1
Valid 5
Valid 5
NOP5
NOP5
Tb2
tCL
CKE
Command
Ta0
NOP1
NOP1
REF
NOP5
REF2
Address
ACT
RA
All banks
A10
RA
One bank
Bank(s)3
BA[2:0]
BA
DQS, DQS#4
DQ4
DM4
tRP
tRFC
(MIN)
tRFC2
Indicates break
in time scale
Notes:
Dont Care
1. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. CKE must be active during the PRECHARGE, ACTIVATE, and REFRESH
commands, but may be inactive at other times (see Power-Down Mode (page 180)).
2. The second REFRESH is not required, but two back-to-back REFRESH commands are
shown.
3. Dont Care if A10 is HIGH at this point; however, A10 must be HIGH if more than one
bank is active (must precharge all active banks).
4. For operations shown, DM, DQ, and DQS signals are all Dont Care/High-Z.
5. Only NOP and DES commands are allowed after a REFRESH command and until tRFC
(MIN) is satisfied.
SELF REFRESH
The SELF REFRESH command is used to retain data in the DRAM, even if the rest of the
system is powered down. When in self refresh mode, the DRAM retains data without external clocking. Self refresh mode is also a convenient method used to enable/disable
the DLL as well as to change the clock frequency within the allowed synchronous operating range (see Input Clock Frequency Change (page 124)). All power supply inputs
(including V REFCA and V REFDQ) must be maintained at valid levels upon entry/exit and
during self refresh mode operation. V REFDQ may float or not drive V DDQ/2 while in self
refresh mode under the following conditions:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
119
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
120
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
T1
Ta0
Ta1
Tb0
Tc0
Td0
Td1
Te0
Te1
Tf0
CK#
CK
Valid1
CKE
MRS2
Command
SRE3
NOP
SRX4
NOP
7
tCKSRE
tMOD
tCKSRX8
NOP
tXS
MRS5
NOP
Valid1
tMOD
tCKESR
ODT9
Valid1
Indicates break
in time scale
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Dont Care
A similar procedure is required for switching from the DLL disable mode back to the
DLL enable mode. This also requires changing the frequency during self refresh mode
(see Figure 42 (page 122)).
1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT
is turned off, and RTT,nom and RTT(WR) are High-Z), enter self refresh mode.
2. After tCKSRE is satisfied, change the frequency to the new clock rate.
3. Self refresh may be exited when the clock is stable with the new frequency for
tCKSRX. After tXS is satisfied, update the mode registers with the appropriate values. At a minimum, set MR1[0] to 0 to enable the DLL. Wait tMRD, then set MR0[8]
to 1 to enable DLL RESET.
4. After another tMRD delay is satisfied, update the remaining mode registers with
the appropriate values.
5. The DRAM will be ready for its next command in the DLL enable mode after the
greater of tMRD or tMOD has been satisfied. However, before applying any command or function requiring a locked DLL, a delay of tDLLK after DLL RESET must
be satisfied. A ZQCL command should be issued with the appropriate timings met.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
121
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
T0
Ta0
Ta1
Tb0
Tc0
Tc1
Td0
Te0
Tf0
Tg0
Th0
CK#
CK
CKE
Valid
tDLLK
Command
SRE1
NOP
SRX2
NOP
tCKSRE
tCKSRX9
MRS3
tXS
MRS4
tMRD
MRS5
Valid 6
tMRD
ODTLoff + 1 tCK
tCKESR
ODT10
Indicates break
in time scale
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Dont Care
The clock frequency range for the DLL disable mode is specified by the parameter tCK
(DLL_DIS). Due to latency counter and timing restrictions, only CL = 6 and CWL = 6 are
supported.
DLL disable mode will affect the read data clock to data strobe relationship (tDQSCK)
but not the data strobe to data relationship (tDQSQ, tQH). Special attention is needed to
line up read data to the controller time domain.
Compared to the DLL on mode where tDQSCK starts from the rising clock edge AL + CL
cycles after the READ command, the DLL disable mode tDQSCK starts AL + CL - 1 cycles
after the READ command.
WRITE operations function similarly between the DLL enable and DLL disable modes;
however, ODT functionality is not allowed with DLL disable mode.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
122
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
Command
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Address
Valid
CK#
CK
RL = AL + CL = 6 (CL = 6, AL = 0)
CL = 6
DQS, DQS# DLL on
DI
b
DQ BL8 DLL on
RL (DLL_DIS) = AL + (CL - 1) = 5
DI
b+1
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
DI
b+1
tDQSCK
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
DI
b+3
DI
b+4
DI
b+5
DI
b+6
(DLL_DIS) MAX
DI
b+1
DI
b+2
DI
b+7
Transitioning Data
Dont Care
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Symbol
tDQSCK
123
(DLL_DIS)
Min
Max
Unit
10
ns
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
124
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
T1
T2
Tb0
Tc1
Tc0
Td0
Td1
Te0
Te1
CK#
CK
tCH
tCH
b
tCL
tCKSRE
tIS
tCL
b
tCH
b
tCK
b
tCL
b
tCK
b
tCKSRX
tCKE
tIH
CKE
tIS
tCPDED
Command
tCH
b
tCK
b
tCK
tIH
tCL
b
NOP
NOP
NOP
NOP
NOP
Address
MRS
NOP
Valid
DLL RESET
tAOFPD/tAOF
tXP
Valid
tIH
tIS
ODT
DQS, DQS#
High-Z
DQ
High-Z
DM
tDLLK
Enter precharge
power-down mode
Frequency
change
Exit precharge
power-down mode
Indicates break
in time scale
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Dont Care
125
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Write Leveling
For better signal integrity, DDR3 SDRAM memory modules have adopted fly-by topology for the commands, addresses, control signals, and clocks. Write leveling is a scheme
for the memory controller to adjust or de-skew the DQS strobe (DQS, DQS#) to CK relationship at the DRAM with a simple feedback feature provided by the DRAM. Write leveling is generally used as part of the initialization process, if required. For normal
DRAM operation, this feature must be disabled. This is the only DRAM operation where
the DQS functions as an input (to capture the incoming clock) and the DQ function as
outputs (to report the state of the clock). Note that nonstandard ODT schemes are required.
The memory controller using the write leveling procedure must have adjustable delay
settings on its DQS strobe to align the rising edge of DQS to the clock at the DRAM pins.
This is accomplished when the DRAM asynchronously feeds back the CK status via the
DQ bus and samples with the rising edge of DQS. The controller repeatedly delays the
DQS strobe until a CK transition from 0 to 1 is detected. The DQS delay established by
this procedure helps ensure tDQSS, tDSS, and tDSH specifications in systems that use
fly-by topology by de-skewing the trace length mismatch. A conceptual timing of this
procedure is shown in Figure 45.
Figure 45: Write Leveling Concept
T0
T1
T2
T3
T4
T5
T6
T7
CK#
CK
Source
Differential DQS
Tn
T0
T1
T2
T3
T4
T5
T6
T4
T5
T6
CK#
CK
Destination
Differential DQS
DQ
Destination
Tn
T0
T1
T2
T3
CK#
CK
DQ
Dont Care
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
126
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
MR1[12]
MR1[2, 6, 9]
Write
Leveling
Output
Buffers
RTT,nom
Value
Disabled
Enabled
(1)
DRAM
RTT,nom
DRAM
ODT Ball DQS
DQ
Low
Off
, or
120
High
On
n/a
Low
Off
, or
120
High
On
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Case Notes
n/a
Enabled
(0)
Off
DRAM State
1. Expected usage if used during write leveling: Case 1 may be used when DRAM are on a
dual-rank module and on the rank not being leveled or on any rank of a module not
being leveled on a multislot system. Case 2 may be used when DRAM are on any rank of
a module not being leveled on a multislot system. Case 3 is generally not used. Case 4 is
generally used when DRAM are on the rank that is being leveled.
2. Since the DRAM DQS is not being driven (MR1[12] = 1), DQS ignores the input strobe,
and all RTT,nom values are allowed. This simulates a normal standby state to DQS.
3. Since the DRAM DQS is being driven (MR1[12] = 0), DQS captures the input strobe, and
only some RTT,nom values are allowed. This simulates a normal write state to DQS.
127
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
128
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
T2
tWLS
tWLH
CK#
CK
Command
MRS1
NOP2
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tMOD
ODT
tWLDQSEN
tDQSL3
tDQSH3
tDQSL3
tDQSH3
Differential DQS4
tWLMRD
tWLO
tWLO
Prime DQ5
tWLO
tWLOE
Early remaining DQ
tWLO
Late remaining DQ
Indicates break
in time scale
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Dont Care
129
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
T1
T2
Ta0
Tb0
Tc0
Tc1
Tc2
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MRS
Td0
Td1
Te0
Te1
NOP
Valid
NOP
Valid
CK#
CK
Command
tMRD
Address
MR1
tIS
Valid
Valid
tMOD
ODT
t
ODTLoff AOF (MIN)
RTT,nom
AOF (MAX)
DQS, DQS#
RTT(DQ)
tWLO
DQ
+ tWLOE
CK = 1
Indicates break
in time scale
Note:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Transitioning
Dont Care
1. The DQ result, = 1, between Ta0 and Tc0, is a result of the DQS, DQS# signals capturing
CK HIGH just after the T0 state.
130
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Initialization
The following sequence is required for power-up and initialization, as shown in Figure 48 (page 132):
1. Apply power. RESET# is recommended to be below 0.2 V DDQ during power ramp
to ensure the outputs remain disabled (High-Z) and ODT off (RTT is also High-Z).
All other inputs, including ODT, may be undefined.
During power-up, either of the following conditions may exist and must be met:
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Condition A:
VDD and V DDQ are driven from a single-power converter output and are
ramped with a maximum delta voltage between them of V 300mV. Slope reversal of any power supply signal is allowed. The voltage levels on all balls other than V DD, V DDQ, V SS, V SSQ must be less than or equal to V DDQ and V DD on
one side, and must be greater than or equal to V SSQ and V SS on the other side.
Both V DD and V DDQ power supplies ramp to V DD,min and V DDQ,min within
tV
DDPR = 200ms.
VREFDQ tracks V DD 0.5, V REFCA tracks V DD 0.5.
VTT is limited to 0.95V when the power ramp is complete and is not applied
directly to the device; however, tVTD should be greater than or equal to 0 to
avoid device latchup.
Condition B:
VDD may be applied before or at the same time as V DDQ.
VDDQ may be applied before or at the same time as V TT, V REFDQ, and V REFCA.
No slope reversals are allowed in the power supply ramp for this condition.
Until stable power, maintain RESET# LOW to ensure the outputs remain disabled
(High-Z). After the power is stable, RESET# must be LOW for at least 200s to begin the initialization process. ODT will remain in the High-Z state while RESET# is
LOW and until CKE is registered HIGH.
CKE must be LOW 10ns prior to RESET# transitioning HIGH.
After RESET# transitions HIGH, wait 500s (minus one clock) with CKE LOW.
After the CKE LOW time, CKE may be brought HIGH (synchronously) and only
NOP or DES commands may be issued. The clock must be present and valid for at
least 10ns (and a minimum of five clocks) and ODT must be driven LOW at least
tIS prior to CKE being registered HIGH. When CKE is registered HIGH, it must be
continuously registered HIGH until the full initialization process is complete.
After CKE is registered HIGH and after tXPR has been satisfied, MRS commands
may be issued. Issue an MRS (LOAD MODE) command to MR2 with the applicable
settings (provide LOW to BA2 and BA0 and HIGH to BA1).
Issue an MRS command to MR3 with the applicable settings.
Issue an MRS command to MR1 with the applicable settings, including enabling
the DLL and configuring ODT.
Issue an MRS command to MR0 with the applicable settings, including a DLL RESET command. tDLLK (512) cycles of clock input are required to lock the DLL.
Issue a ZQCL command to calibrate RTT and RON values for the process voltage
temperature (PVT). Prior to normal operation, tZQinit must be satisfied.
When tDLLK and tZQinit have been satisfied, the DDR3 SDRAM will be ready for
normal operation.
131
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
See power-up
conditions
in the
initialization
sequence text,
set up 1
VREF
Power-up
ramp
tVTD
Stable and
valid clock
T0
T1
tCK
Tc0
Tb0
Ta0
Td0
CK#
CK
tCKSRX
tIOZ
tCL
tCL
= 20ns
RESET#
tIS
T (MIN) = 10ns
CKE
Valid
ODT
Valid
tIS
Command
NOP
MRS
MRS
MRS
MRS
Address
Code
Code
Code
Code
A10
Code
Code
Code
Code
BA0 = L
BA1 = H
BA2 = L
BA0 = H
BA1 = H
BA2 = L
BA0 = H
BA1 = L
BA2 = L
BA0 = L
BA1 = L
BA2 = L
ZQCL
Valid
DM
BA[2:0]
Valid
Valid
A10 = H
Valid
DQS
DQ
RTT
T = 200s (MIN)
T = 500s (MIN)
tXPR
MR2
All voltage
supplies valid
and stable
tMRD
tMRD
MR3
tMRD
MR1 with
DLL enable
tMOD
MR0 with
DLL reset
tZQinit
ZQ calibration
tDLLK
Normal
operation
Indicates break
in time scale
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
132
Dont Care
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Mode Registers
Mode registers (MR0MR3) are used to define various modes of programmable operations of the DDR3 SDRAM. A mode register is programmed via the mode register set
(MRS) command during initialization, and it retains the stored information (except for
MR0[8], which is self-clearing) until it is reprogrammed, RESET# goes LOW, the device
loses power.
Contents of a mode register can be altered by re-executing the MRS command. Even if
the user wants to modify only a subset of the mode registers variables, all variables
must be programmed when the MRS command is issued. Reprogramming the mode
register will not alter the contents of the memory array, provided it is performed correctly.
The MRS command can only be issued (or re-issued) when all banks are idle and in the
precharged state (tRP is satisfied and no data bursts are in progress). After an MRS command has been issued, two parameters must be satisfied: tMRD and tMOD. The controller must wait tMRD before initiating any subsequent MRS commands.
Figure 49: MRS to MRS Command Timing (tMRD)
T0
T1
T2
Ta0
Ta1
Ta2
MRS1
NOP
NOP
NOP
NOP
MRS2
CK#
CK
Command
tMRD
Address
Valid
Valid
CKE3
Indicates break
in time scale
Notes:
Dont Care
1. Prior to issuing the MRS command, all banks must be idle and precharged, tRP (MIN)
must be satisfied, and no data bursts can be in progress.
2. tMRD specifies the MRS to MRS command minimum cycle time.
3. CKE must be registered HIGH from the MRS command until tMRSPDEN (MIN) (see Power-Down Mode (page 180)).
4. For a CAS latency change, tXPDLL timing must be met before any non-MRS command.
The controller must also wait tMOD before initiating any non-MRS commands (excluding NOP and DES). The DRAM requires tMOD in order to update the requested features,
with the exception of DLL RESET, which requires additional time. Until tMOD has been
satisfied, the updated features are to be assumed unavailable.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
133
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
T1
T2
Ta0
Ta1
Ta2
MRS
NOP
NOP
NOP
NOP
non
MRS
CK#
CK
Command
tMOD
Address
Valid
Valid
Valid
CKE
Old
setting
New
setting
Updating setting
Indicates break
in time scale
Notes:
Dont Care
1. Prior to issuing the MRS command, all banks must be idle (they must be precharged, tRP
must be satisfied, and no data bursts can be in progress).
2. Prior to Ta2 when tMOD (MIN) is being satisfied, no commands (except NOP/DES) may be
issued.
3. If RTT was previously enabled, ODT must be registered LOW at T0 so that ODTL is satisfied prior to Ta1. ODT must also be registered LOW at each rising CK edge from T0 until
tMODmin is satisfied at Ta2.
4. CKE must be registered HIGH from the MRS command until tMRSPDEN (MIN), at which
time power-down may occur (see Power-Down Mode (page 180)).
Burst Length
Burst length is defined by MR0[1: 0]. Read and write accesses to the DDR3 SDRAM are
burst-oriented, with the burst length being programmable to 4 (chop mode), 8 (fixed),
or selectable using A12 during a READ/WRITE command (on-the-fly). The burst length
determines the maximum number of column locations that can be accessed for a given
READ or WRITE command. When MR0[1:0] is set to 01 during a READ/WRITE command, if A12 = 0, then BC4 (chop) mode is selected. If A12 = 1, then BL8 mode is selected. Specific timing diagrams, and turnaround between READ/WRITE, are shown in the
READ/WRITE sections of this document.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a boundary is reached. The block is
uniquely selected by A[i:2] when the burst length is set to 4 and by A[i:3] when the burst
length is set to 8 (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the start-
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
134
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
M15 M14
Address bus
18 17 16 15 - 13 12 11 10
01
PD
WR
01 0 0
8 7 6 5 4 3 2
DLL 01 CAS# latency BT CL
1 0
BL
M1 M0
Mode Register
M12
Precharge PD
Note:
Burst Length
Fixed BL8
No
Yes
Reserved
M8 DLL Reset
CAS Latency
M3
16
M6 M5 M4 M2
0
Reserved
Sequential (nibble)
Interleaved
10
12
10
14
11
12
13
14
1. MR0[18, 15:13, 7] are reserved for future use and must be programmed to 0.
Burst Type
Accesses within a given burst may be programmed to either a sequential or an interleaved order. The burst type is selected via MR0[3] (see Figure 51 (page 135)). The ordering of accesses within a burst is determined by the burst length, the burst type, and the
starting column address. DDR3 only supports 4-bit burst chop and 8-bit burst access
modes. Full interleave address ordering is supported for READs, while WRITEs are restricted to nibble (BC4) or word (BL8) boundaries.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
135
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
READ/
WRITE
Starting
Column Address
(A[2, 1, 0])
Notes
4 chop
READ
000
0, 1, 2, 3, Z, Z, Z, Z
0, 1, 2, 3, Z, Z, Z, Z
1, 2
001
1, 2, 3, 0, Z, Z, Z, Z
1, 0, 3, 2, Z, Z, Z, Z
1, 2
010
2, 3, 0, 1, Z, Z, Z, Z
2, 3, 0, 1, Z, Z, Z, Z
1, 2
011
3, 0, 1, 2, Z, Z, Z, Z
3, 2, 1, 0, Z, Z, Z, Z
1, 2
100
4, 5, 6, 7, Z, Z, Z, Z
4, 5, 6, 7, Z, Z, Z, Z
1, 2
101
5, 6, 7, 4, Z, Z, Z, Z
5, 4, 7, 6, Z, Z, Z, Z
1, 2
110
6, 7, 4, 5, Z, Z, Z, Z
6, 7, 4, 5, Z, Z, Z, Z
1, 2
WRITE
8
READ
WRITE
Notes:
111
7, 4, 5, 6, Z, Z, Z, Z
7, 6, 5, 4, Z, Z, Z, Z
1, 2
0VV
0, 1, 2, 3, X, X, X, X
0, 1, 2, 3, X, X, X, X
1, 3, 4
1VV
4, 5, 6, 7, X, X, X, X
4, 5, 6, 7, X, X, X, X
1, 3, 4
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 0, 5, 6, 7, 4
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 0, 1, 6, 7, 4, 5
2, 3, 0, 1, 6, 7, 4, 5
011
3, 0, 1, 2, 7, 4, 5, 6
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 4, 1, 2, 3, 0
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 4, 5, 2, 3, 0, 1
6, 7, 4, 5, 2, 3, 0, 1
111
7, 4, 5, 6, 3, 0, 1, 2
7, 6, 5, 4, 3, 2, 1, 0
VVV
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
1, 3
1. Internal READ and WRITE operations start at the same point in time for BC4 as they do
for BL8.
2. Z = Data and strobe output drivers are in tri-state.
3. V = A valid logic level (0 or 1), but the respective input buffer ignores level-on input
pins.
4. X = Dont Care.
DLL RESET
DLL RESET is defined by MR0[8] (see Figure 51 (page 135)). Programming MR0[8] to 1
activates the DLL RESET function. MR0[8] is self-clearing, meaning it returns to a value
of 0 after the DLL RESET function has been initiated.
Anytime the DLL RESET function is initiated, CKE must be HIGH and the clock held
stable for 512 (tDLLK) clock cycles before a READ command can be issued. This is to
allow time for the internal clock to be synchronized with the external clock. Failing to
wait for synchronization to occur may result in invalid output timing specifications,
such as tDQSCK timings.
Write Recovery
WRITE recovery time is defined by MR0[11:9] (see Figure 51 (page 135)). Write recovery
values of 5, 6, 7, 8, 10, or 12 may be used by programming MR0[11:9]. The user is rePDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
136
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
T1
T2
T3
T4
T5
T6
T7
T8
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command
AL = 0, CL = 6
DQS, DQS#
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
n+4
T0
T1
T2
T3
T4
T5
T6
T7
T8
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command
AL = 0, CL = 8
DQS, DQS#
DI
n
DQ
Transitioning Data
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Dont Care
1. For illustration purposes, only CL = 6 and CL = 8 are shown. Other CL values are possible.
2. Shown with nominal tDQSCK and nominal tDSDQ.
137
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
A1 A0
Address bus
16 15 14 13 12 11 10 9 8 7 6 5
01 0 1 01 Q Off TDQS 01 RTT 01 WL RTT ODS
M15 M14
4 3 2
1 0
AL RTT ODS DLL
Mode Register
M12
Q Off
M11
TDQS
Enabled
Disabled
Disabled
Enabled
(ODT) 2
M0
DLL Enable
Enable (normal)
Disable
(ODT) 3
M7
M9 M6 M2
Non-Writes
Writes
0 0 0
R TT,nom disabled
R TT,nom disabled
0 0 1
Write Leveling
Disable (normal)
Enable
Reserved
Reserved
n/a
Disabled (AL = 0)
1 0 1
n/a
AL = CL - 1
1 1 0
Reserved
Reserved
AL = CL - 2
1 1 1
Reserved
Reserved
Reserved
1. MR1[16, 13, 10, 8] are reserved for future use and must be programmed to 0.
2. During write leveling, if MR1[7] and MR1[12] are 1, then all RTT,nom values are available
for use.
3. During write leveling, if MR1[7] is a 1, but MR1[12] is a 0, then only RTT,nom write values
are available for use.
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
138
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
OUTPUT ENABLE/DISABLE
The OUTPUT ENABLE function is defined by MR1[12], as shown in Figure 53
(page 138). When enabled (MR1[12] = 0), all outputs (DQ, DQS, DQS#) function when in
the normal mode of operation. When disabled (MR1[12] = 1), all DDR3 SDRAM outputs
(DQ and DQS, DQS#) are tri-stated. The output disable feature is intended to be used
during IDD characterization of the READ current and during tDQSS margining (write
leveling) only.
TDQS Enable
Termination data strobe (TDQS) is a feature of the x8 DDR3 SDRAM configuration that
provides termination resistance (RTT) and may be useful in some system configurations.
TDQS is not supported in x4 or x16 configurations. When enabled via the mode register
(MR1[11]), the RTT that is applied to DQS and DQS# is also applied to TDQS and TDQS#.
In contrast to the RDQS function of DDR2 SDRAM, DDR3s TDQS provides the termination resistance RTT only. The OUTPUT DATA STROBE function of RDQS is not provided
by TDQS; thus, R ON does not apply to TDQS and TDQS#. The TDQS and DM functions
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
139
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
On-Die Termination
ODT resistance RTT,nom is defined by MR1[9, 6, 2] (see Figure 53 (page 138)). The R TT
termination value applies to the DQ, DM, DQS, DQS#, and TDQS, TDQS# balls. DDR3
supports multiple RTT termination values based on RZQ/n where n can be 2, 4, 6, 8, or
12 and RZQ is 240
Unlike DDR2, DDR3 ODT must be turned off prior to reading data out and must remain
off during a READ burst. RTT,nom termination is allowed any time after the DRAM is initialized, calibrated, and not performing read access, or when it is not in self refresh
mode. Additionally, write accesses with dynamic ODT enabled (RTT(WR)) temporarily replaces RTT,nom with RTT(WR).
The actual effective termination, RTT(EFF), may be different from the RTT targeted due to
nonlinearity of the termination. For RTT(EFF) values and calculations (see On-Die Termination (ODT) (page 190)).
The ODT feature is designed to improve signal integrity of the memory channel by enabling the DDR3 SDRAM controller to independently turn on/off ODT for any or all devices. The ODT input control pin is used to determine when R TT is turned on (ODTL on)
and off (ODTL off), assuming ODT has been enabled via MR1[9, 6, 2].
Timings for ODT are detailed in On-Die Termination (ODT) (page 190).
WRITE LEVELING
The WRITE LEVELING function is enabled by MR1[7], as shown in Figure 53 (page 138).
Write leveling is used (during initialization) to deskew the DQS strobe to clock offset as
a result of fly-by topology designs. For better signal integrity, DDR3 SDRAM memory
modules adopted fly-by topology for the commands, addresses, control signals, and
clocks.
The fly-by topology benefits from a reduced number of stubs and their lengths. However, fly-by topology induces flight time skews between the clock and DQS strobe (and
DQ) at each DRAM on the DIMM. Controllers will have a difficult time maintaining
tDQSS, tDSS, and tDSH specifications without supporting write leveling in systems
which use fly-by topology-based modules. Write leveling timing and detailed operation
information is provided in Write Leveling (page 126).
140
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
READ or WRITE command is held for the time of the AL before it is released
internally to the DDR3 SDRAM device. READ latency (RL) is controlled by the sum of
the AL and CAS latency (CL), RL = AL + CL. WRITE latency (WL) is the sum of CAS
WRITE latency and AL, WL = AL + CWL (see Mode Register 2 (MR2) (page 141)). Examples of READ and WRITE latencies are shown in Figure 54 (page 141) and Figure 56
(page 142).
Figure 54: READ Latency (AL = 5, CL = 6)
BC4
T0
T1
T2
T6
T11
T12
T13
T14
ACTIVE n
READ n
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command
tRCD
(MIN)
DQS, DQS#
AL = 5
CL = 6
DO
n
DQ
DO
n+1
DO
n+2
DO
n+3
RL = AL + CL = 11
Indicates break
in time scale
Transitioning Data
Dont Care
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
141
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Address bus
16 15 14 13 12 11 10 9 8 7
6
0 01 01 01 RTT(WR) 01 SRT ASR
01 1
M15 M14
Mode Register
M5 M4 M3
2 1 0
01 01 01
Reserved
Reserved
Dynamic ODT
(R TT(WR) )
M10 M9
0
Note:
CWL
RTT(WR) disabled
1 Enabled: Automatic
RZQ/4
RZQ/2
Reserved
Disabled: Manual
1. MR2[16, 13:11, 8, and 2:0] are reserved for future use and must all be programmed to 0.
T0
T1
ACTIVE n
WRITE n
T2
T6
T11
T12
T13
T14
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command
tRCD
(MIN)
DQS, DQS#
AL = 5
CWL = 6
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
WL = AL + CWL = 11
Indicates break
in time scale
Transitioning Data
Dont Care
142
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
DYNAMIC ODT
The dynamic ODT (RTT(WR)) feature is defined by MR2[10, 9]. Dynamic ODT is enabled
when a value is selected. This new DDR3 SDRAM feature enables the ODT termination
value to change without issuing an MRS command, essentially changing the ODT termination on-the-fly.
With dynamic ODT (RTT(WR)) enabled, the DRAM switches from normal ODT (RTT,nom)
to dynamic ODT (RTT(WR)) when beginning a WRITE burst and subsequently switches
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
143
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
16
01
A4 A3
A2
A1 A0
15 14 13 12 11 10 9
8 7
6
5
4
3
2
1 0
1
1 01 01 01 01 01 01 01 01 01 01 01 MPR MPR_RF
MPR Enable
Normal DRAM operations2
M15 M14
Notes:
A7 A6 A5
Mode Register
M2
M1 M0
Address bus
Reserved
Reserved
Reserved
1. MR3[16 and 13:3] are reserved for future use and must all be programmed to 0.
2. When MPR control is set for normal DRAM operation, MR3[1, 0] will be ignored.
3. Intended to be used for READ synchronization.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
144
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Memory core
Multipurpose register
predefined data for READs
MR3[2] = 1 (MPR on)
DQ, DM, DQS, DQS#
Notes:
1. A predefined data pattern can be read out of the MPR with an external READ command.
2. MR3[2] defines whether the data flow comes from the memory core or the MPR. When
the data flow is defined, the MPR contents can be read out continuously with a regular
READ or RDAP command.
MR3[1:0]
MPR
Function
Dont Care
A[1:0]
(see Table 77 (page 146))
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
145
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
A2 = 0; burst order = 0, 1, 2, 3
A2 = 1; burst order = 4, 5, 6, 7
Burst order bit 0 (the first bit) is assigned to LSB, and burst order bit 7 (the last bit) is
assigned to MSB
A[9:3] are a Dont Care
A10 is a Dont Care
A11 is a Dont Care
A12: Selects burst chop mode on-the-fly, if enabled within MR0
A13 is a Dont Care
BA[2:0] are a Dont Care
MR3[1:0]
Function
00
01
10
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
RFU
RFU
Burst
Length
Read
A[2:0]
BL8
000
Burst order: 0, 1, 2, 3, 4, 5, 6, 7
Predefined pattern: 0, 1, 0, 1, 0, 1, 0, 1
BC4
000
Burst order: 0, 1, 2, 3
Predefined pattern: 0, 1, 0, 1
BC4
100
Burst order: 4, 5, 6, 7
Predefined pattern: 0, 1, 0, 1
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
146
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
MR3[1:0]
Function
Burst
Length
Read
A[2:0]
11
RFU
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Note:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
1. Burst order bit 0 is assigned to LSB, and burst order bit 7 is assigned to MSB of the selected MPR agent.
147
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
148
DQ
DQS, DQS#
A[15:13]
tMOD
Notes:
A12/BC#
A10/AP
00
A[9:3]
A11
A2
A[1:0]
tRP
MRS
Ta0
PREA
T0
Bank address
Command
CK#
CK
NOP
Tc4
NOP
Tc5
NOP
Tc6
tMPRR
MRS
Tc7
Valid 1
Valid
00
Valid
Valid
Valid
NOP
Tc3
02
NOP
Tc2
Valid
NOP
Tc1
02
RL
NOP
Tc0
NOP
Tb1
Valid
READ1
Tb0
Figure 59: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout
tMOD
Indicates break
in time scale
NOP
Tc8
NOP
Tc9
Dont Care
Valid
Tc10
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
149
DQ
tMOD
Notes:
A[15:13]
DQS, DQS#
A12/BC#
A10/AP
00
A[9:3]
A11
A2
MRS
A[1:0]
tRP
Ta
PREA
T0
Bank address
Command
CK#
CK
RL
NOP
Tc6
NOP
Tc7
NOP
Tc8
tMPRR
Indicates break
in time scale
NOP
Tc9
00
Valid
MRS
Tc10
RL
Valid
Valid
NOP
Tc5
Valid 1
NOP
Tc4
Valid
NOP
Tc3
NOP
Tc2
Valid
Valid
NOP
Tc1
Valid
Valid
Valid
12
02
Valid
02
02
READ1
Valid
tCCD
Tc0
Valid
READ1
Tb
Figure 60: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout
Valid
Dont Care
tMOD
Td
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
150
DQ
tMOD
Notes:
A[15:13]
DQS, DQS#
A12/BC#
A10/AP
00
A[9:3]
A11
A2
A[1:0]
tRF
MRS
Ta
PREA
T0
Bank address
Command
CK#
CK
14
03
1.
2.
3.
4.
NOP
Tc1
NOP
Tc2
RL
NOP
Tc3
RL
Valid
Valid 1
Valid 1
Valid
Valid
Valid
Valid
Valid
Valid
02
02
Valid
Valid
tCCD
READ1
Tc0
Valid
READ1
Tb
NOP
Tc4
NOP
Tc5
NOP
Tc6
Figure 61: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble
NOP
Tc7
tMPRR
00
Valid
MRS
Tc8
tMOD
NOP
Tc10
Indicates break
in time scale
NOP
Tc9
Dont Care
Valid
Td
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
151
DQ
tMOD
Notes:
A[15:13]
DQS, DQS#
A12/BC#
A10/AP
00
A[9:3]
A11
A2
A[1:0]
tRF
MRS
Ta
PREA
T0
Bank address
Command
CK#
CK
04
13
1.
2.
3.
4.
NOP
Tc1
NOP
Tc2
RL
NOP
Tc3
RL
Valid
Valid 1
Valid 1
Valid
Valid
Valid
Valid
Valid
Valid
02
02
Valid
Valid
tCCD
READ1
Tc0
Valid
READ1
Tb
NOP
Tc4
NOP
Tc5
NOP
Tc6
Figure 62: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble
NOP
Tc7
tMPRR
00
Valid
MRS
Tc8
tMOD
Indicates break
in time scale
NOP
Tc9
NOP
Tc10
Dont Care
Valid
Td
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
5.
6.
7.
8.
The MRS command can only be issued (or re-issued) when all banks are idle and in the
precharged state (tRP is satisfied and no data bursts are in progress). The controller
must wait the specified time tMRD before initiating a subsequent operation such as an
ACTIVATE command (see Figure 49 (page 133)). There is also a restriction after issuing
an MRS command with regard to when the updated functions become available. This
parameter is specified by tMOD. Both tMRD and tMOD parameters are shown in Figure 49 (page 133) and Figure 50 (page 134). Violating either of these requirements will
result in unspecified operation.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
152
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
ZQ CALIBRATION Operation
The ZQ CALIBRATION command is used to calibrate the DRAM output drivers (RON)
and ODT values (RTT) over process, voltage, and temperature, provided a dedicated
240 (1%) external resistor is connected from the DRAMs ZQ ball to V SSQ.
DDR3 SDRAM require a longer time to calibrate RON and ODT at power-up initialization
and self refresh exit, and a relatively shorter time to perform periodic calibrations.
DDR3 SDRAM defines two ZQ CALIBRATION commands: ZQCL and ZQCS. An example
of ZQ calibration timing is shown below.
All banks must be precharged and tRP must be met before ZQCL or ZQCS commands
can be issued to the DRAM. No other activities (other than issuing another ZQCL or
ZQCS command) can be performed on the DRAM channel by the controller for the duration of tZQinit or tZQoper. The quiet time on the DRAM channel helps accurately calibrate RON and ODT. After DRAM calibration is achieved, the DRAM should disable the
ZQ balls current consumption path to reduce power.
ZQ CALIBRATION commands can be issued in parallel to DLL RESET and locking time.
Upon self refresh exit, an explicit ZQCL is required if ZQ calibration is desired.
In dual-rank systems that share the ZQ resistor between devices, the controller must not
enable overlap of tZQinit, tZQoper, or tZQCS between ranks.
Figure 63: ZQ CALIBRATION Timing (ZQCL and ZQCS)
T0
T1
Ta0
Ta1
Ta2
Ta3
Tb0
Tb1
Tc0
Tc1
Tc2
ZQCL
NOP
NOP
NOP
Valid
Valid
ZQCS
NOP
NOP
NOP
Valid
Address
Valid
Valid
Valid
A10
Valid
Valid
Valid
CK#
CK
Command
CKE
Valid
Valid
Valid
ODT
Valid
Valid
Valid
DQ
Activities
High-Z
tZQinit
or tZQoper
High-Z
tZQCS
Indicates break
in time scale
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Activities
Dont Care
153
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
ACTIVATE Operation
Before any READ or WRITE commands can be issued to a bank within the DRAM, a row
in that bank must be opened (activated). This is accomplished via the ACTIVATE command, which selects both the bank and the row to be activated.
After a row is opened with an ACTIVATE command, a READ or WRITE command may
be issued to that row, subject to the tRCD specification. However, if the additive latency
is programmed correctly, a READ or WRITE command may be issued prior to tRCD
(MIN). In this operation, the DRAM enables a READ or WRITE command to be issued
after the ACTIVATE command for that bank, but prior to tRCD (MIN) with the requirement that (ACTIVATE-to-READ/WRITE) + AL tRCD (MIN) (see Posted CAS Additive
Latency). tRCD (MIN) should be divided by the clock period and rounded up to the next
whole number to determine the earliest clock edge after the ACTIVATE command on
which a READ or WRITE command can be entered. The same procedure is used to convert other specification limits from time units to clock cycles.
When at least one bank is open, any READ-to-READ command delay or WRITE-toWRITE command delay is restricted to tCCD (MIN).
A subsequent ACTIVATE command to a different row in the same bank can only be issued after the previous active row has been closed (precharged). The minimum time interval between successive ACTIVATE commands to the same bank is defined by tRC.
A subsequent ACTIVATE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVATE commands to different banks is defined by tRRD. No more than four bank ACTIVATE commands may be issued in a given
tFAW (MIN) period, and the tRRD (MIN) restriction still applies. The tFAW (MIN) parameter applies, regardless of the number of banks already opened or closed.
Figure 64: Example: Meeting tRRD (MIN) and tRCD (MIN)
T0
T1
T2
T3
T4
T5
T8
T9
T10
T11
Command
ACT
NOP
NOP
ACT
NOP
NOP
NOP
NOP
NOP
RD/WR
Address
Row
Row
Col
BA[2:0]
Bank x
Bank y
Bank y
CK#
CK
tRRD
tRCD
Indicates break
in time scale
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
154
Dont Care
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
CK#
T0
T1
T4
T5
T8
T9
T10
T11
T19
T20
ACT
NOP
ACT
NOP
ACT
NOP
ACT
NOP
NOP
ACT
CK
Command
Address
BA[2:0]
Row
Row
Row
Row
Row
Bank a
Bank b
Bank c
Bank d
Bank ey
tRRD
tFAW
Indicates break
in time scale
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
155
Dont Care
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
READ Operation
READ bursts are initiated with a READ command. The starting column and bank addresses are provided with the READ command and auto precharge is either enabled or
disabled for that burst access. If auto precharge is enabled, the row being accessed is
automatically precharged at the completion of the burst. If auto precharge is disabled,
the row will be left open after the completion of the burst.
During READ bursts, the valid data-out element from the starting column address is
available READ latency (RL) clocks later. RL is defined as the sum of posted CAS additive
latency (AL) and CAS latency (CL) (RL = AL + CL). The value of AL and CL is programmable in the mode register via the MRS command. Each subsequent data-out element is
valid nominally at the next positive or negative clock edge (that is, at the next crossing
of CK and CK#). Figure 66 shows an example of RL based on a CL setting of 8 and an AL
setting of 0.
Figure 66: READ Latency
T0
T7
T8
T9
T10
T11
T12
T12
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command
Address
Bank a,
Col n
CL = 8, AL = 0
DQS, DQS#
DO
n
DQ
Indicates break
in time scale
Notes:
Transitioning Data
Dont Care
DQS, DQS# is driven by the DRAM along with the output data. The initial LOW state on
DQS and HIGH state on DQS# is known as the READ preamble (tRPRE). The LOW state
on DQS and the HIGH state on DQS#, coincident with the last data-out element, is
known as the READ postamble (tRPST). Upon completion of a burst, assuming no other
commands have been initiated, the DQ goes High-Z. A detailed explanation of tDQSQ
(valid data-out skew), tQH (data-out window hold), and the valid data window are depicted in Figure 77 (page 164). A detailed explanation of tDQSCK (DQS transition skew
to CK) is also depicted in Figure 77 (page 164).
Data from any READ burst may be concatenated with data from a subsequent READ
command to provide a continuous flow of data. The first data element from the new
burst follows the last element of a completed burst. The new READ command should be
issued tCCD cycles after the first READ command. This is shown for BL8 in Figure 67
(page 158). If BC4 is enabled, tCCD must still be met, which will cause a gap in the data
output, as shown in Figure 68 (page 158). Nonconsecutive READ data is reflected in
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
156
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
157
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Bank,
Col n
Address2
NOP
T1
Notes:
RL = 5
NOP
T3
Bank,
Col b
READ
T4
158
Bank,
Col n
Address2
DQ3
DQS, DQS#
READ
T0
Command1
CK
CK#
NOP
T1
Notes:
tCCD
NOP
T2
tRPRE
NOP
T5
DO
n
DO
n+1
NOP
T6
DO
n+3
RL = 5
DO
n+2
DO
n+4
NOP
T7
DO
n+5
NOP
T8
DO
n+6
DO
n+7
NOP
T9
DO
b
DO
b+1
NOP
T10
DO
b+2
DO
b+3
NOP
T11
DO
b+4
DO
b+5
NOP
T12
DO
b+7
Transitioning Data
DO
b+6
tRPST
NOP
T13
Dont Care
NOP
T14
Bank,
Col b
READ
T4
tRPRE
NOP
DO
n
DO
n+1
NOP
T6
RL = 5
DO
n+2
DO
n+3
tRPST
NOP
T7
NOP
T8
tRPRE
NOP
T9
DO
b
DO
b+1
NOP
T10
DO
b+2
DO
b+3
tRPST
NOP
T11
NOP
T13
Transitioning Data
NOP
T12
Dont Care
NOP
T14
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BC4 setting is activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during READ command at T0
and T4.
3. DO n (or b) = data-out from column n (or column b).
4. BC4, RL = 5 (CL = 5, AL = 0).
RL = 5
NOP
T3
T5
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ command at T0
and T4.
3. DO n (or b) = data-out from column n (or column b).
4. BL8, RL = 5 (CL = 5, AL = 0).
tCCD
NOP
T2
DQ3
DQS, DQS#
READ
T0
Command1
CK
CK#
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
NOP
T1
Notes:
NOP
T2
1.
2.
3.
4.
CL = 8
NOP
T4
159
DQ3
DQS, DQS#
Address2
Command1
CK
CK#
Bank,
Col n
READ
T0
NOP
T2
NOP
T3
NOP
T4
NOP
T5
Notes:
NOP
T6
NOP
T7
NOP
T8
DO
n
CL = 8
NOP
T9
NOP
T10
NOP
T11
NOP
T12
NOP
T13
DO
b
NOP
T14
DO
n
DO
n+1
DO
n+2
Bank,
Col b
WRITE
T6
DO
n+3
DO
n+4
NOP
T7
DO
n+5
NOP
T9
DO
n+7
tRPST
WL = 5
DO
n+6
NOP
T8
NOP
T10
tWPRE
DI
n
NOP
T11
DI
n+1
tBL
DI
DI
n+2 n+3
NOP
T12
DI
n+5
NOP
T16
DI
n+6
NOP
Dont Care
DI
n+7
tWPST
tWR
tWR
NOP
T15
Transitioning Data
T14
Transitioning Data
DI
n+4
= 4 clocks
NOP
T13
NOP
T15
Dont Care
NOP
T17
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the READ command at
T0, and the WRITE command at T6.
3. DO n = data-out from column, DI b = data-in for column b.
4. BL8, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
RL = 5
tRPRE
NOP
T1
Bank a,
Col b
READ
T5
AL = 0, RL = 8.
DO n (or b) = data-out from column n (or column b).
Seven subsequent elements of data-out appear in the programmed order following DO n.
Seven subsequent elements of data-out appear in the programmed order following DO b.
NOP
T3
DQ
DQS, DQS#
READ
Bank a,
Col n
Address
T0
Command
CK
CK#
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
160
NOP
T1
NOP
T2
NOP
T3
WRITE
Bank,
Col n
DQ
DQS, DQS#
READ
Bank a,
Col n
Address
T0
Command
CK
CK#
T4
Notes:
NOP
T1
tRTP
tRAS
NOP
T2
NOP
T5
DO
n
DO
n+ 1
NOP
T7
DO
n+3
tRPST
WL = 5
DO
n+ 2
NOP
T6
NOP
T8
tWPRE
DI
n
NOP
T9
DI
n+ 1
DI
n+2
NOP
T10
= 4 clocks
DI
n+ 3
tWPST
tBL
NOP
T11
NOP
T12
tWR
tWTR
NOP
T14
Transitioning Data
NOP
T13
Dont Care
NOP
T15
NOP
T3
NOP
T4
Bank a,
(or all)
PRE
T5
NOP
T6
NOP
T7
NOP
T8
DO
n
DO
n+1
tRP
DO
n+2
NOP
T9
DO
n+3
DO
n+4
NOP
T10
DO
n+5
DO
n+6
NOP
T11
DO
n+7
NOP
T12
Bank a,
Row b
ACT
T13
NOP
T14
NOP
T15
Transitioning Data
NOP
T16
Dont Care
NOP
T17
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BC4 OTF setting is activated by MR0[1:0] and A12 = 0 during READ command at T0 and WRITE command at
T4.
3. DO n = data-out from column n; DI n = data-in from column b.
4. BC4, RL = 5 (AL - 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
RL = 5
tRPRE
Bank,
Col b
READ
T0
DQ3
DQS, DQS#
Address2
Command1
CK
CK#
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Address
NOP
T1
tRTP
tRAS
NOP
T2
NOP
T3
NOP
T4
Bank a,
(or all)
PRE
T5
NOP
T6
Address
161
NOP
T1
NOP
T2
AL = 5
NOP
T3
NOP
T4
tRAS
NOP
T5
NOP
T6
Address
DQ
DQS, DQS#
READ
Bank a,
Col n
T0
Command
CK
CK#
NOP
T1
AL = 4
NOP
T2
NOP
T3
NOP
T4
NOP
T5
tRTP
tRAS
(MIN)
NOP
T6
T7
NOP
DQ
DQS, DQS#
READ
Bank a,
Col n
T0
Command
CK
CK#
DQ
DQS, DQS#
READ
Bank a,
Col n
T0
Command
CK
CK#
(MIN)
DO
n
CL = 6
NOP
T7
tRTP
NOP
T7
NOP
T8
T8
T10
NOP
T9
Bank a,
(or all)
PRE
T9
NOP
DO
n+3
CL = 6
DO
n+2
NOP
T8
NOP
DO
n+1
tRP
NOP
T9
NOP
T10
NOP
T10
NOP
T11
DO
n
T11
NOP
DO
n
DO
n+2
T11
NOP
DO
n+1
NOP
T12
DO
n+3
DO
n+1
Bank a,
Row b
ACT
T13
DO
n+2
DO
n+3
NOP
T13
NOP
T13
Indicates break
in time scale
NOP
T12
tRP
NOP
T12
NOP
T14
tRP
NOP
Transitioning Data
NOP
T14
Transitioning Data
NOP
T16
Transitioning Data
NOP
T15
Dont Care
Bank a,
Row b
ACT
Ta0
Dont Care
Bank a,
Row b
ACT
T15
Dont Care
NOP
T17
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
162
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
All DQ collectively
Notes:
Bank,
Col n
Address2
DQS, DQS#
READ
T0
Command1
CK
CK#
NOP
T2
RL = AL + CL
NOP
T3
tRPRE
(MAX)
tLZDQ (MIN)
tDQSQ
NOP
T4
NOP
T6
tDQSQ
(MAX)
NOP
T7
NOP
T8
tRPST
NOP
T9
DO
n+1
DO
n+2
Data valid
DO
n+3
DO
n+4
DO
n+5
DO
n+6
DO
n+7
tQH
DO
DO
DO
DO
DO
DO
DO
n+1
n+2
n+3
n+4
n+5
n+6
n+7
DO
DO
DO
DO
DO
DO
DO
n+3
n+1
n+2
n+4
n+5
n+6
n+7
Data valid
DO
n
DO
n
tQH
DO
n
NOP
T5
tHZDQ
Dont Care
(MAX)
NOP
T10
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BL8 setting is activated by either MR0[1, 0] = 0, 0 or MR0[0, 1] = 0, 1 and A12 = 1 during READ command at
T0.
3. DO n = data-out from column n.
4. BL8, RL = 5 (AL = 0, CL = 5).
5. Output timings are referenced to VDDQ/2 and DLL on and locked.
6. tDQSQ defines the skew between DQS, DQS# to data and does not define DQS, DQS# to CK.
7. Early data transitions may not always happen at the same DQ. Data transitions of a DQ can be early or late within
a burst.
NOP
T1
Figure 76: Data Output Timing tDQSQ and Data Valid Window
163
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
and tLZ transitions occur in the same access time as valid data transitions. These
parameters are referenced to a specific voltage level that specifies when the device output is no longer driving tHZDQS and tHZDQ, or begins driving tLZDQS, tLZDQ. Figure 78 (page 165) shows a method of calculating the point when the device is no longer
driving tHZDQS and tHZDQ, or begins driving tLZDQS, tLZDQ, by measuring the signal
at two different voltages. The actual voltage measurement points are not critical as long
as the calculation is consistent. The parameters tLZDQS, tLZDQ, tHZDQS, and tHZDQ
are defined as single-ended.
RL measured
to this point
T0
T1
T2
T3
T4
T5
T6
CK
CK#
tDQSCK
tLZDQS
tDQSCK
(MIN)
(MIN)
tQSH
tDQSCK
(MIN)
tQSL
tQSH
tDQSCK
(MIN)
tHZDQS
(MIN)
(MIN)
tQSL
DQS, DQS#
early strobe
tRPST
tRPRE
Bit 0
tLZDQS
Bit 1
tDQSCK
(MAX)
Bit 2
Bit 3
tDQSCK
(MAX)
Bit 4
Bit 5
tDQSCK
(MAX)
Bit 6
Bit 7
tDQSCK
(MAX)
tHZDQS
(MAX)
(MAX)
tRPST
DQS, DQS#
late strobe
tRPRE
tQSH
Bit 0
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
tQSL
Bit 1
tQSH
Bit 2
164
tQSL
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
VOH - xmV
VTT + 2xmV
VOH - 2xmV
VTT + xmV
tLZDQS, tLZDQ
tHZDQS, tHZDQ
T2
T1
tHZDQS, tHZDQ
VOL + 2xmV
VTT - xmV
VOL + xmV
VTT - 2xmV
T1
T2
tLZDQS, tLZDQ
end point = 2 T1 - T2
begin point = 2 T1 - T2
1. Within a burst, the rising strobe edge is not necessarily fixed at tDQSCK (MIN) or tDQSCK
(MAX). Instead, the rising strobe edge can vary between tDQSCK (MIN) and tDQSCK
(MAX).
2. The DQS HIGH pulse width is defined by tQSH, and the DQS LOW pulse width is defined
by tQSL. Likewise, tLZDQS (MIN) and tHZDQS (MIN) are not tied to tDQSCK (MIN) (early
strobe case), and tLZDQS (MAX) and tHZDQS (MAX) are not tied to tDQSCK (MAX) (late
strobe case); however, they tend to track one another.
3. The minimum pulse width of the READ preamble is defined by tRPRE (MIN). The minimum pulse width of the READ postamble is defined by tRPST (MIN).
Notes:
tB
DQS
VTT
tD
VTT
DQS#
Single-ended signal provided
as background information
T1
begins
tRPRE
DQS - DQS#
tRPRE
T2
ends
Resulting differential
signal relevant for
tRPRE specification
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
0V
tRPRE
165
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
tA
DQS
Single-ended signal, provided
as background information
VTT
tC
tD
DQS#
VTT
tRPST
DQS - DQS#
Resulting differential
signal relevant for
tRPST specification
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
T1
begins
tRPST
0V
T2
ends
tRPST
166
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
WRITE Operation
WRITE bursts are initiated with a WRITE command. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or
disabled for that access. If auto precharge is selected, the row being accessed is precharged at the end of the WRITE burst. If auto precharge is not selected, the row will
remain open for subsequent accesses. After a WRITE command has been issued, the
WRITE burst may not be interrupted. For the generic WRITE commands used in Figure 83 (page 169) through Figure 91 (page 174), auto precharge is disabled.
During WRITE bursts, the first valid data-in element is registered on a rising edge of
DQS following the WRITE latency (WL) clocks later and subsequent data elements will
be registered on successive edges of DQS. WRITE latency (WL) is defined as the sum of
posted CAS additive latency (AL) and CAS WRITE latency (CWL): WL = AL + CWL. The
values of AL and CWL are programmed in the MR0 and MR2 registers, respectively. Prior
to the first valid DQS edge, a full cycle is needed (including a dummy crossover of DQS,
DQS#) and specified as the WRITE preamble shown in Figure 83 (page 169). The half
cycle on DQS following the last data-in element is known as the WRITE postamble.
The time between the WRITE command and the first valid edge of DQS is WL clocks
tDQSS. Figure 84 (page 170) through Figure 91 (page 174) show the nominal case
where tDQSS = 0ns; however, Figure 83 (page 169) includes tDQSS (MIN) and tDQSS
(MAX) cases.
Data may be masked from completing a WRITE using data mask. The data mask occurs
on the DM ball aligned to the WRITE data. If DM is LOW, the WRITE completes normally. If DM is HIGH, that bit of data is masked.
Upon completion of a burst, assuming no other commands have been initiated, the DQ
will remain High-Z, and any additional input data will be ignored.
Data for any WRITE burst may be concatenated with a subsequent WRITE command to
provide a continuous flow of input data. The new WRITE command can be tCCD clocks
following the previous WRITE command. The first data element from the new burst is
applied after the last element of a completed burst. Figure 84 (page 170) and Figure 85
(page 170) show concatenated bursts. An example of nonconsecutive WRITEs is shown
in Figure 86 (page 171).
Data for any WRITE burst may be followed by a subsequent READ command after tWTR
has been met (see Figure 87 (page 171), Figure 88 (page 172), and Figure 89
(page 173)).
Data for any WRITE burst may be followed by a subsequent PRECHARGE command,
providing tWR has been met, as shown in Figure 90 (page 174) and Figure 91
(page 174).
Both tWTR and tWR starting time may vary, depending on the mode register settings
(fixed BC4, BL8 versus OTF).
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
167
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
CK#
T1
begins
tWPRE
DQS - DQS#
0V
tWPRE
T2
Resulting differential
signal relevant for
tWPRE specification
tWPRE
ends
CK#
tWPST
DQS - DQS#
Resulting differential
signal relevant for
tWPST specification
0V
T1
begins
tWPST
T2
ends
tWPST
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
168
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command1
WL = AL + CWL
Address2
Bank,
Col n
tDQSS
tWPRE
(MIN)
tDQSS tDSH
tDSH
tDSH
tDSH tWPST
DQS, DQS#
tDQSH
tDQSL
tDQSH
DI
n
DQ3
tDQSS
DI
n+1
tWPRE
(NOM)
tDQSL
tDQSH
DI
n+2
tDQSL
DI
n+3
tDSH
tDQSH
DI
n+4
tDQSL
DI
n+5
tDSH
tDQSH
DI
n+6
tDQSL
DI
n+7
tDSH
tDSH
tWPST
tDQSH
tDQSL
DQS, DQS#
tDQSH
tDQSL
tDQSH
tDSS
tDQSH
tDSS
DI
n
DQ3
tDQSL
DI
n+1
tDQSL
tDQSH
tDQSL
tDSS
DI
n+2
DI
n+3
tDSS
DI
n+4
DI
n+5
tDSS
DI
n+6
DI
n+7
tDQSS
tDQSS
tWPRE
(MAX)
tWPST
DQS, DQS#
tDQSH
tDQSL
tDQSH
tDSS
DI
n
DQ3
tDQSL
tDQSH
tDSS
DI
n+1
tDQSL
tDQSH
tDSS
DI
n+2
DI
n+3
tDQSL
tDQSH
tDSS
DI
n+4
DI
n+5
tDQSL
tDSS
DI
n+6
DI
n+7
Transitioning Data
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Dont Care
1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
the WRITE command at T0.
3. DI n = data-in for column n.
4. BL8, WL = 5 (AL = 0, CWL = 5).
5. tDQSS must be met at each rising clock edge.
6. tWPST is usually depicted as ending at the crossing of DQS, DQS#; however, tWPST actually ends when DQS no longer drives LOW and DQS# no longer drives HIGH.
169
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Valid
Address2
NOP
T1
Notes:
tCCD
NOP
T2
Valid
WRITE
T4
tWPRE
DI
n
NOP
T5
DI
n+1
DI
n+2
NOP
T6
170
Valid
Address2
DQ3
DQS, DQS#
WRITE
T0
Command1
CK
CK#
NOP
T1
Notes:
tCCD
1.
2.
3.
4.
5.
NOP
T2
WL = 5
DI
n+3
DI
n+4
NOP
T7
DI
n+5
DI
n+6
NOP
T8
DI
n+7
DI
b
NOP
T9
DI
b+1
DI
b+2
NOP
T10
tBL
DI
b+3
DI
b+4
= 4 clocks
NOP
T11
DI
b+5
DI
b+6
NOP
T12
Transitioning Data
DI
b+7
tWPST
NOP
T13
NOP
Dont Care
tWTR
tWR
T14
Valid
WRITE
T4
tWPRE
DI
n
NOP
T5
DI
n+1
DI
n+2
NOP
T6
WL = 5
DI
n+3
tWPST
NOP
NOP
T8
tWPRE
DI
b
NOP
T9
DI
b+1
DI
b+2
NOP
T10
DI
b+3
tWPST
tBL
= 4 clocks
NOP
T11
NOP
T12
Transitioning Data
NOP
T13
NOP commands are shown for ease of illustration; other commands may be valid at these times.
BC4, WL = 5 (AL = 0, CWL = 5).
DI n (or b) = data-in for column n (or column b).
The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0 and T4.
If set via MRS (fixed) tWR and tWTR would start T11 (2 cycles earlier).
WL = 5
NOP
T3
T7
NOP
Dont Care
tWTR
tWR
T14
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the WRITE commands at
T0 and T4.
3. DI n (or b) = data-in for column n (or column b).
4. BL8, WL = 5 (AL = 0, CWL = 5).
WL = 5
NOP
T3
DQ3
DQS, DQS#
WRITE
T0
Command1
CK
CK#
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Valid
Address
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
NOP
T1
Notes:
NOP
T2
NOP
T4
1.
2.
3.
4.
171
DQ4
DQS, DQS#
Address3
Command1
CK
CK#
Valid
WRITE
T0
Notes:
NOP
T1
Valid
WRITE
T5
NOP
T6
DI
n
NOP
T7
DI
n+1
NOP
T9
DI
n+2
DI
n+3
DI
n+4
WL = CWL + AL = 7
NOP
T8
DI
n+5
DI
n+6
NOP
T10
DI
n+7
NOP
T11
DI
b
NOP
T12
DI
b+1
DI
b+2
NOP
T13
DI
b+3
DI
b+4
NOP
T14
DI
b+5
WL = 5
NOP
T3
NOP
tWPRE
DI
n
NOP
T5
DI
n+1
DI
n+2
NOP
T6
DI
n+3
DI
n+4
NOP
T7
DI
n+5
DI
n+6
NOP
T8
DI
n+7
tWPST
NOP
T10
Indicates break
in time scale
NOP
T9
NOP
T11
Transitioning Data
tWTR2
DI
b+7
NOP
T16
Transitioning Data
DI
b+6
NOP
T15
Dont Care
Valid
READ
Ta0
Don't Care
NOP
T17
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. tWTR controls the WRITE-to-READ delay to the same device and starts with the first rising clock edge after the last
write data shown at T9.
3. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and MR0[12] = 1 during the WRITE command
at T0. The READ command at Ta0 can be either BC4 or BL8, depending on MR0[1:0] and the A12 status at Ta0.
4. DI n = data-in for column n.
5. RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
NOP
T2
T4
WL = CWL + AL = 7
NOP
T3
DM
DQ
DQS, DQS#
WRITE
T0
Command
CK
CK#
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Valid
Address3
DQ4
DQS, DQS#
WRITE
T0
Command1
CK
CK#
Notes:
NOP
T1
WL = 5
NOP
T3
NOP
T4
tWPRE
DI
n
NOP
T5
DI
n+1
DI
n+2
NOP
T6
DI
n+3
tWPST
NOP
T7
Indicates break
in time scale
NOP
T8
Transitioning Data
tWTR2
NOP
T9
Dont Care
Valid
READ
Ta0
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. tWTR controls the WRITE-to-READ delay to the same device and starts with the first rising clock edge after the last
write data shown at T7.
3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0 and the READ command at
Ta0.
4. DI n = data-in for column n.
5. BC4 (fixed), WL = 5 (AL = 0, CWL = 5), RL = 5 (AL = 0, CL = 5).
NOP
T2
172
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Valid
Address3
DQ4
DQS, DQS#
WRITE
T0
Command1
CK
CK#
Notes:
NOP
T1
WL = 5
NOP
T3
NOP
T4
tWPRE
DI
n
NOP
T5
DI
n+1
DI
n+2
NOP
T6
NOP
= 4 clocks
DI
n+3
tWPST
tBL
T7
NOP
T8
NOP
T9
Indicates break
in time scale
tWTR2
NOP
T10
Transitioning Data
NOP
T11
RL = 5
Dont Care
Valid
READ
Tn
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. tWTR controls the WRITE-to-READ delay to the same device and starts after tBL.
3. The BC4 OTF setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0 and the READ
command at Tn.
4. DI n = data-in for column n.
5. BC4, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
NOP
T2
173
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
Ta0
Ta1
Command
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
PRE
Address
Valid
CK#
CK
Valid
tWR
WL = AL + CWL
DQS, DQS#
DI
n
DQ BL8
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
Indicates break
in time scale
Notes:
Transitioning Data
Dont Care
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
Ta0
Ta1
Command
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
PRE
Address
Valid
CK#
CK
Valid
tWR
WL = AL + CWL
DQS, DQS#
DI
n
DQ BC4
DI
n+1
DI
n+2
DI
n+3
Indicates break
in time scale
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Transitioning Data
Dont Care
1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. The write recovery time (tWR) is referenced from the first rising clock edge after the last
write data is shown at T7. tWR specifies the last burst WRITE cycle until the PRECHARGE
command can be issued to the same bank.
3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0.
4. DI n = data-in for column n.
5. BC4 (fixed), WL = 5, RL = 5.
174
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
T1
T2
T3
T4
T5
T6
T7
T8
T9
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Tn
CK#
CK
Command1
PRE
tWR2
Address3
Bank,
Col n
Valid
tWPRE
tWPST
DQS, DQS#
DI
n
DQ4
DI
n+1
DI
n+2
DI
n+3
WL = 5
Indicates break
in time scale
Notes:
Transitioning Data
Dont Care
1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. The write recovery time (tWR) is referenced from the rising clock edge at T9. tWR specifies the last burst WRITE cycle until the PRECHARGE command can be issued to the same
bank.
3. The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command
at T0.
4. DI n = data-in for column n.
5. BC4 (OTF), WL = 5, RL = 5.
DQ Input Timing
Figure 83 (page 169) shows the strobe-to-clock timing during a WRITE burst. DQS,
DQS# must transition within 0.25tCK of the clock transitions, as limited by tDQSS. All
data and data mask setup and hold timings are measured relative to the DQS, DQS#
crossing, not the clock crossing.
The WRITE preamble and postamble are also shown in Figure 83 (page 169). One clock
prior to data input to the DRAM, DQS must be HIGH and DQS# must be LOW. Then for
a half clock, DQS is driven LOW (DQS# is driven HIGH) during the WRITE preamble,
tWPRE. Likewise, DQS must be kept LOW by the controller after the last data is written
to the DRAM during the WRITE postamble, tWPST.
Data setup and hold times are also shown in Figure 83 (page 169). All setup and hold
times are measured from the crossing points of DQS and DQS#. These setup and hold
values pertain to data input and data mask input.
Additionally, the half period of the data input strobe is specified by tDQSH and tDQSL.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
175
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
DQ
tDQSH
tWPST
tDQSL
DI
b
DM
tDS
tDH
tDS
tDH
Transitioning Data
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
176
Dont Care
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PRECHARGE Operation
Input A10 determines whether one bank or all banks are to be precharged and, in the
case where only one bank is to be precharged, inputs BA[2:0] select the bank.
When all banks are to be precharged, inputs BA[2:0] are treated as Dont Care. After a
bank is precharged, it is in the idle state and must be activated prior to any READ or
WRITE commands being issued.
The DRAM must be idle with all banks in the precharge state (tRP is satisfied and no
bursts are in progress) before a self refresh entry command can be issued. ODT must
also be turned off before self refresh entry by registering the ODT ball LOW prior to the
self refresh entry command (see On-Die Termination (ODT) (page 190) for timing requirements). If RTT,nom and RTT(WR) are disabled in the mode registers, ODT can be a
Dont Care. After the self refresh entry command is registered, CKE must be held LOW
to keep the DRAM in self refresh mode.
After the DRAM has entered self refresh mode, all external control signals, except CKE
and RESET#, are Dont Care. The DRAM initiates a minimum of one REFRESH command internally within the tCKE period when it enters self refresh mode.
The requirements for entering and exiting self refresh mode depend on the state of the
clock during self refresh mode. First and foremost, the clock must be stable (meeting
tCK specifications) when self refresh mode is entered. If the clock remains stable and
the frequency is not altered while in self refresh mode, then the DRAM is allowed to exit
self refresh mode after tCKESR is satisfied (CKE is allowed to transition HIGH tCKESR
later than when CKE was registered LOW). Since the clock remains stable in self refresh
mode (no frequency change), tCKSRE and tCKSRX are not required. However, if the
clock is altered during self refresh mode (if it is turned-off or its frequency changes),
then tCKSRE and tCKSRX must be satisfied. When entering self refresh mode, tCKSRE
must be satisfied prior to altering the clock's frequency. Prior to exiting self refresh
mode, tCKSRX must be satisfied prior to registering CKE HIGH.
When CKE is HIGH during self refresh exit, NOP or DES must be issued for tXS time. tXS
is required for the completion of any internal refresh already in progress and must be
satisfied before a valid command not requiring a locked DLL can be issued to the device. tXS is also the earliest time self refresh re-entry may occur. Before a command requiring a locked DLL can be applied, a ZQCL command must be issued, tZQOPER timing must be met, and tXSDLL must be satisfied. ODT must be off during tXSDLL.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
177
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
T1
T2
Ta0
Tb0
Tc0
Tc1
Td0
Te0
Tf0
Valid
Valid
CK#
CK
tCKSRX1
tCKSRE1
tIS
tIH
tCPDED
tIS
CKE
tCKESR
(MIN)1
tIS
ODT2
Valid
ODTL
RESET#2
Command
NOP
SRE (REF)3
NOP4
SRX (NOP)
NOP5
Address
tRP8
Valid 6
Valid 7
Valid
Valid
tXS6, 9
tXSDLL7, 9
Indicates break
in time scale
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Dont Care
1. The clock must be valid and stable, meeting tCK specifications at least tCKSRE after entering self refresh mode, and at least tCKSRX prior to exiting self refresh mode, if the
clock is stopped or altered between states Ta0 and Tb0. If the clock remains valid and
unchanged from entry and during self refresh mode, then tCKSRE and tCKSRX do not
apply; however, tCKESR must be satisfied prior to exiting at SRX.
2. ODT must be disabled and RTT off prior to entering self refresh at state T1. If both
RTT,nom and RTT(WR) are disabled in the mode registers, ODT can be a Dont Care.
3. Self refresh entry (SRE) is synchronous via a REFRESH command with CKE LOW.
4. A NOP or DES command is required at T2 after the SRE command is issued prior to the
inputs becoming Dont Care.
5. NOP or DES commands are required prior to exiting self refresh mode until state Te0.
6. tXS is required before any commands not requiring a locked DLL.
7. tXSDLL is required before any commands requiring a locked DLL.
8. The device must be in the all banks idle state prior to entering self refresh mode. For
example, all banks must be precharged, tRP must be met, and no data bursts can be in
progress.
9. Self refresh exit is asynchronous; however, tXS and tXSDLL timings start at the first rising
clock edge where CKE HIGH satisfies tISXR at Tc1. tCKSRX timing is also measured so that
tISXR is satisfied at Tc1.
178
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
MR2 Bits
Description
If ASR is disabled (MR2[6] = 0), SRT must be programmed to indicate TOPER during self refresh:
*MR2[7] = 0: Normal operating temperature range (0C to 85C)
*MR2[7] = 1: Extended operating temperature range (0C to 95C)
If ASR is enabled (MR2[7] = 1), SRT must be set to 0, even if the extended temperature range is
supported
*MR2[7] = 0: SRT is disabled
When ASR is enabled, the DRAM automatically provides SELF REFRESH power management functions, (refresh rate for all supported operating temperature values)
* MR2[6] = 1: ASR is enabled (M7 must = 0)
When ASR is not enabled, the SRT bit must be programmed to indicate TOPER during SELF REFRESH
operation
* MR2[6] = 0: ASR is disabled; must use manual self refresh temperature (SRT)
Self refresh mode is supported in normal and extended temper- Normal and extended (0C to 95C)
ature ranges; When SRT is enabled, it increases self refresh
power consumption
Self refresh mode is supported in normal and extended temper- Normal and extended (0C to 95C)
ature ranges; Self refresh power consumption may be temperature-dependent
Illegal
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
179
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Power-Down Mode
Power-down is synchronously entered when CKE is registered LOW coincident with a
NOP or DES command. CKE is not allowed to go LOW while an MRS, MPR, ZQCAL,
READ, or WRITE operation is in progress. CKE is allowed to go LOW while any of the
other legal operations (such as ROW ACTIVATION, PRECHARGE, auto precharge, or REFRESH) are in progress. However, the power-down IDD specifications are not applicable
until such operations have completed. Depending on the previous DRAM state and the
command issued prior to CKE going LOW, certain timing constraints must be satisfied
(as noted in Table 80). Timing diagrams detailing the different power-down mode entry
and exits are shown in Figure 95 (page 182) through Figure 104 (page 186).
Table 80: Command to Power-Down Entry Parameters
DRAM Status
Parameter (Min)
Parameter Value
Figure
Idle or active
ACTIVATE
tACTPDEN
1tCK
Idle or active
PRECHARGE
tPRPDEN
1tCK
READ or READAP
tRDPDEN
Active
tWRPDEN
Active
WRITE: BC4MRS
Active
Active
Active
WRITEAP: BC4MRS
tWRAPDEN
tWR/tCK
WL + 2tCK + tWR/tCK
RL +
WL +
4tCK
4tCK
1tCK
WL + 2tCK + WR + 1tCK
WL +
4tCK
+ WR +
Idle
REFRESH
tREFPDEN
Power-down
REFRESH
tXPDLL
Idle
tMRSPDEN
tMOD
Note:
1tCK
1. If slow-exit mode precharge power-down is enabled and entered, ODT becomes asynchronous tANPD prior to CKE going LOW and remains asynchronous until tANPD +
tXPDLL after CKE goes HIGH.
Entering power-down disables the input and output buffers, excluding CK, CK#, ODT,
CKE, and RESET#. NOP or DES commands are required until tCPDED has been satisfied, at which time all specified input/output buffers are disabled. The DLL should be in
a locked state when power-down is entered for the fastest power-down exit timing. If
the DLL is not locked during power-down entry, the DLL must be reset after exiting
power-down mode for proper READ operation as well as synchronous ODT operation.
During power-down entry, if any bank remains open after all in-progress commands are
complete, the DRAM will be in active power-down mode. If all banks are closed after all
in-progress commands are complete, the DRAM will be in precharge power-down
mode. Precharge power-down mode must be programmed to exit with either a slow exit
mode or a fast exit mode. When entering precharge power-down mode, the DLL is
turned off in slow exit mode or kept on in fast exit mode.
The DLL also remains on when entering active power-down. ODT has special timing
constraints when slow exit mode precharge power-down is enabled and entered. Refer
to Asynchronous ODT Mode (page 203) for detailed ODT usage requirements in slow
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
180
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
DLL State
PowerDown Exit
Dont Care
On
Fast
tXP
Precharged
(all banks precharged)
On
Fast
tXP
Slow
tXPDLL
DRAM State
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Off
181
Relevant Parameters
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
NOP
NOP
NOP
Valid
CK#
CK
Command
tCK
tCH
tCL
NOP
Valid
NOP
tPD
tIS
CKE
Address
tIH
tIH
tCKE
tIS
(MIN)
Valid
Valid
tXP
tCPDED
Enter power-down
mode
Exit power-down
mode
Indicates break
in time scale
Dont Care
T1
T2
T3
T4
T5
NOP
NOP
Ta0
Ta1
NOP
Valid
CK#
CK
CK
CH
Command
NOP
CL
NOP
CPDED
IS
CKE (MIN)
IH
CKE
IS
PD
Enter power-down
mode
XP
Exit power-down
mode
Indicates break
in time scale
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
182
Dont Care
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
T1
T2
T3
T4
Ta
NOP
NOP
Ta1
Tb
CK#
CK
tCK
Command
tCH
tCL
NOP
PRE
NOP
tCKE
tCPDED
Valid 1
Valid 2
(MIN)
tXP
tIH
tIS
CKE
tXPDLL
tIS
tPD
Enter power-down
mode
Exit power-down
mode
Indicates break
in time scale
Notes:
Dont Care
Figure 98: Power-Down Entry After READ or READ with Auto Precharge (RDAP)
CK#
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
READ/
RDAP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Ta7
Ta8
Ta9
Ta10
Ta11
Ta12
CK
Command
NOP
tIS
NOP
tCPDED
CKE
Address
Valid
tPD
RL = AL + CL
DQS, DQS#
DQ BL8
DQ BC4
DI
n
DI
DI
n+1 n+2
DI
n
DI
n+1
DI
n+3
DI
n+4
DI
n+ 5
DI
n+6
DI
n+7
DI
DI
n+2 n+3
tRDPDEN
Power-down or
self refresh entry
Indicates break
in time scale
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
183
Transitioning Data
Dont Care
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Tb0
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Tb1
Tb2
Tb3
Tb4
CK
Command
NOP
tIS
NOP
tCPDED
CKE
Address
Valid
tWR
WL = AL + CWL
tPD
DQS, DQS#
DQ BL8
DI
n
DI
DI
n+1 n+2
DI
n+3
DQ BC4
DI
n
DI
n+1
DI
n+3
DI
n+2
DI
n+4
DI
DI
n+5 n+6
DI
n+7
tWRPDEN
Power-down or
self refresh entry1
Indicates break
in time scale
Note:
Transitioning Data
Dont Care
Figure 100: Power-Down Entry After WRITE with Auto Precharge (WRAP)
CK#
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Tb0
Tb1
Tb2
WRAP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Tb3
Tb4
CK
Command
tIS
tCPDED
CKE
Address
Valid
A10
WR1
WL = AL + CWL
tPD
DQS, DQS#
DQ BL8
DI
n
DI
n+1
DI
DI
DI
n+2 n+3 n+4
DQ BC4
DI
n
DI
n+1
DI
DI
n+2 n+3
DI
n+5
DI
n+6
DI
n+7
tWRAPDEN
Start internal
precharge
Power-down or
self refresh entry2
Indicates break
in time scale
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Transitioning Data
Dont Care
184
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
T1
T2
T3
Ta0
NOP
NOP
Ta1
Ta2
Tb0
CK#
CK
tCK
Command
tCH
tCL
REFRESH
NOP
tCPDED
NOP
tCKE
Valid
(MIN)
tPD
tIS
CKE
tREFPDEN
tXP
tRFC
(MIN)
(MIN)1
Indicates break
in time scale
Note:
Dont Care
1. After CKE goes HIGH during tRFC, CKE must remain HIGH until tRFC is satisfied.
T1
T2
T3
NOP
NOP
T4
T5
T6
T7
CK#
CK
tCK
Command
Address
tCH
tCL
ACTIVE
Valid
tCPDED
tIS
tPD
CKE
tACTPDEN
Dont Care
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
185
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
T1
T2
T3
NOP
NOP
T4
T5
T6
T7
CK#
CK
tCK
Command
tCH
tCL
PRE
All/single
bank
Address
tCPDED
tIS
tPD
CKE
tPREPDEN
Dont Care
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
CK#
CK
tCK
Command
MRS
Address
Valid
tCH
NOP
tCPDED
tCL
NOP
NOP
NOP
tMRSPDEN
NOP
tPD
tIS
CKE
Indicates break
in time scale
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
186
Dont Care
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
T1
T2
T3
T4
Ta0
NOP
REFRESH
Ta1
Tb0
CK#
CK
Command
tCK
tCH
NOP
tCL
NOP
NOP
tCPDED
NOP
NOP
tXP1
tIH
tIS
CKE
tIS
tPD
tXPDLL2
Enter power-down
mode
Enter power-down
mode
Exit power-down
mode
Indicates break
in time scale
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Dont Care
187
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
RESET Operation
The RESET signal (RESET#) is an asynchronous reset signal that triggers any time it
drops LOW, and there are no restrictions about when it can go LOW. After RESET# goes
LOW, it must remain LOW for 100ns. During this time, the outputs are disabled, ODT
(RTT) turns off (High-Z), and the DRAM resets itself. CKE should be driven LOW prior to
RESET# being driven HIGH. After RESET# goes HIGH, the DRAM must be re-initialized
as though a normal power-up was executed. All refresh counters on the DRAM are reset,
and data stored in the DRAM is assumed unknown after RESET# has gone LOW.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
188
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
T0
T1
tCK
Tc0
Tb0
Ta0
Td0
CK#
CK
tCL
tCL
t CKSRX1
T = 100ns (MIN)
RESET#
tIOZ
= 20ns
T = 10ns (MIN)
tIS
Valid
CKE
tIS
tIS
Static LOW in case RTT_Nom is enabled at time Ta0, otherwise static HIGH or LOW
ODT
Valid
tIS
MRS
MRS
MRS
MRS
Address
Code
Code
Code
Code
A10
Code
Code
Code
Code
BA0 = L
BA1 = H
BA2 = L
BA0 = H
BA1 = H
BA2 = L
BA0 = H
BA1 = L
BA2 = L
BA0 = L
BA1 = L
BA2 = L
Command
NOP
Valid
ZQCL
DM
BA[2:0]
DQS
DQ
RTT
Valid
Valid
A10 = H
Valid
High-Z
High-Z
High-Z
T = 500s (MIN)
MR2
All voltage
supplies valid
and stable
tMRD
tMRD
tXPR
MR3
DRAM ready
for external
commands
tMRD
MR1 with
DLL ENABLE
tMOD
MR0 with
DLL RESET
ZQCAL
tZQinit
tDLLK
Normal
operation
Indicates break
in time scale
Note:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Dont Care
189
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
VDDQ/2
RTT
Switch
DQ, DQS, DQS#,
DM, TDQS, TDQS#
Nominal ODT
ODT (NOM) is the base termination resistance for each applicable ball; it is enabled or
disabled via MR1[9, 6, 2] (see Mode Register 1 (MR1) Definition), and it is turned on or
off via the ODT ball.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
190
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
DRAM State
Notes
000
Any valid
000
000101
Any valid
000101
Illegal
Notes:
1. Assumes dynamic ODT is disabled (see Dynamic ODT (page 192) when enabled).
2. ODT is enabled and active during most writes for proper termination, but it is not illegal
for it to be off during writes.
3. ODT must be disabled during reads. The RTT,nom value is restricted during writes. Dynamic ODT is applicable if enabled.
Nominal ODT resistance RTT,nom is defined by MR1[9, 6, 2], as shown in Mode Register 1
(MR1) Definition. The R TT,nom termination value applies to the output pins previously
mentioned. DDR3 SDRAM supports multiple RTT,nom values based on RZQ/n where n
can be 2, 4, 6, 8, or 12 and RZQ is 240. RTT,nom termination is allowed any time after the
DRAM is initialized, calibrated, and not performing read access, or when it is not in self
refresh mode.
Write accesses use RTT,nom if dynamic ODT (RTT(WR)) is disabled. If RTT,nom is used during writes, only RZQ/2, RZQ/4, and RZQ/6 are allowed (see Table 86 (page 193)). ODT
timings are summarized in Table 83 (page 191), as well as listed in Table 55 (page 76).
Examples of nominal ODT timing are shown in conjunction with the synchronous
mode of operation in Synchronous ODT Mode (page 198).
Table 83: ODT Parameters
Symbol
Description
Begins at
Unit
tAON
CWL + AL - 2
tCK
Defined to
ODTLon
RTT(ON)
ODTLoff
RTT(OFF) tAOF
CWL + AL - 2
tCK
tAONPD
RTT(ON)
28.5
ns
tAOFPD
RTT(OFF)
28.5
ns
ODT registered
LOW
4tCK
tCK
ODTH4
ODTH8
Write registration
with ODT HIGH
ODT registered
LOW
6tCK
tCK
tAON
Completion of
ODTLon
RTT(ON)
ps
tAOF
Completion of
ODTLoff
RTT(OFF)
0.5tCK 0.2tCK
tCK
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
191
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Dynamic ODT
In certain application cases, and to further enhance signal integrity on the data bus, it is
desirable that the termination strength of the DDR3 SDRAM can be changed without
issuing an MRS command, essentially changing the ODT termination on the fly. With
dynamic ODT RTT(WR)) enabled, the DRAM switches from nominal ODT RTT,nom) to dynamic ODT RTT(WR)) when beginning a WRITE burst and subsequently switches back to
nominal ODT RTT,nom) at the completion of the WRITE burst. This requirement is supported by the dynamic ODT feature, as described below.
tAON
ODTLoff +
tAOFF
tMOD
tMOD
+ 1CK
I/Os
DQS, DQS#
DQs
No RTT,nom
DQS, DQS#
No RTT,nom
DQs
No RTT,nom
+ 1CK
Functional Description
The dynamic ODT mode is enabled if either MR2[9] or MR2[10] is set to 1. Dynamic
ODT is not supported during DLL disable mode so RTT(WR) must be disabled. The dynamic ODT function is described below:
Two RTT values are availableRTT,nom and RTT(WR).
The value for RTT,nom is preselected via MR1[9, 6, 2].
The value for RTT(WR) is preselected via MR2[10, 9].
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
192
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Unit
WL - 2
tCK
Write registration
tCK
Write registration
tCK
ODTLcnw completed
0.5tCK 0.2tCK
tCK
Symbol
Description
Begins at
Defined to
ODTLcnw
Write registration
ODTLcwn4
ODTLcwn8
tADC
M6
M2
RTT,nom (RZQ)
RTT,nom (Ohm)
Off
Off
n/a
RZQ/4
60
Self refresh
RZQ/2
120
RZQ/6
40
RZQ/12
20
RZQ/8
30
Reserved
Reserved
n/a
Reserved
Reserved
n/a
Note:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
1. RZQ = 240. If RTT,nom is used during WRITEs, only RZQ/2, RZQ/4, RZQ/6 are allowed.
193
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
M9
RTT(WR) (RZQ)
RTT(WR) (Ohm)
RZQ/4
RZQ/2
120
Reserved
Reserved
60
Title
Dynamic ODT: ODT Asserted Before and After the WRITE, BC4
Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8
Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4
Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
194
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
NOP
T0
NOP
T1
Notes:
NOP
T3
Valid
WRS4
T4
ODTH4
NOP
T6
RTT,nom
ODTLcnw
(MAX)
(MIN)
tAON
tAON
NOP
T5
WL
195
DQ
DQS, DQS#
RTT
ODT
Address
Command
CK#
CK
Valid
T0
Notes:
Valid
T1
tADC
tADC
(MAX)
(MIN)
NOP
T8
ODTLcwn4
NOP
T7
DI
n
NOP
T9
DI
n+ 1
RTT(WR)
DI
n+ 2
NOP
T10
DI
n+ 3
NOP
T11
(MAX)
(MIN)
tADC
tADC
NOP
T12
NOP
T13
T15
NOP
NOP
T16
Transitioning
ODTLoff
RTT,nom
NOP
T14
Dont Care
(MAX)
(MIN)
tAOF
tAOF
NOP
T17
Valid
T3
(MIN)
(MAX)
Valid
T4
Valid
T5
Valid
RTT,nom
Valid
T7
T9
(MAX)
Valid
T10
Transitioning
tAOF
tAOF
(MIN)
Valid
ODTLoff
Valid
T8
Dont Care
Valid
T11
tAON
tAON
ODTH4
ODTLon
Valid
T2
T6
ODTH4
ODTLon
NOP
T2
DQ
DQS, DQS#
RTT
ODT
Address
Command
CK#
CK
Figure 108: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
DQ
DQS, DQS#
RTT
ODT
Address
Command
CK
CK#
NOP
T0
Notes:
Valid
WRS8
T1
196
ODTLon
ODTLcnw
NOP
T3
WL
ODTH8
NOP
T4
tAON
(MAX)
(MIN)
tADC
NOP
T5
ODTLcwn8
DI
b
NOP
T6
DI
b+1
DI
b+2
RTT(WR)
NOP
T7
DI
b+3
DI
b+ 4
NOP
T8
DI
b+5
ODTLoff
DI
b+6
NOP
T9
DI
b+ 7
(MAX)
tAOF
Transitioning
tAOF
NOP
T10
(MIN)
Dont Care
NOP
T11
1. Via MRS or OTF; AL = 0, CWL = 5. If RTT,nom can be either enabled or disabled, ODT can be HIGH. RTT(WR) is enabled.
2. In this example, ODTH8 = 6 is satisfied exactly.
NOP
T2
Figure 110: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
T1
T2
NOP
WRS4
NOP
T3
T4
T5
T6
T7
T8
T9
T10
T11
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command
ODTLcnw
Address
Valid
ODTH4
ODTLoff
ODT
ODTLon
tADC
tADC
(MAX)
RTT(WR)
RTT
tAON
tADC
(MIN)
tAOF
(MIN)
RTT,nom
tAOF
(MAX)
(MIN)
(MAX)
ODTLcwn4
DQS, DQS#
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
WL
Transitioning
Notes:
Dont Care
Figure 112: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4
T0
T1
T2
NOP
WRS4
NOP
T3
T4
T5
T6
T7
T8
T9
T10
T11
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command
ODTLcnw
Address
Valid
ODTLoff
ODTH4
ODT
tADC
ODTLon
tAOF
(MAX)
(MIN)
RTT(WR)
RTT
tAON
tAOF
(MIN)
(MAX)
ODTLcwn4
DQS, DQS#
WL
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
Transitioning
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Dont Care
1. Via MRS or OTF. AL = 0, CWL = 5. RTT,nom can be either enabled or disabled. If disabled,
ODT can remain HIGH. RTT(WR) is enabled.
2. In this example ODTH4 = 4 is satisfied exactly.
197
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Timing Parameters
Synchronous ODT mode uses the following timing parameters: ODTLon, ODTLoff,
ODTH4, ODTH8, tAON, and tAOF. The minimum R TT turn-on time (tAON [MIN]) is the
point at which the device leaves High-Z and ODT resistance begins to turn on. Maximum RTT turn-on time (tAON [MAX]) is the point at which ODT resistance is fully on.
Both are measured relative to ODTLon. The minimum R TT turn-off time (tAOF [MIN]) is
the point at which the device starts to turn off ODT resistance. The maximum R TT turn
off time (tAOF [MAX]) is the point at which ODT has reached High-Z. Both are measured
from ODTLoff.
When ODT is asserted, it must remain HIGH until ODTH4 is satisfied. If a WRITE command is registered by the DRAM with ODT HIGH, then ODT must remain HIGH until
ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (see Figure 114 (page 200)).
ODTH4 and ODTH8 are measured from ODT registered HIGH to ODT registered LOW
or from the registration of a WRITE command until ODT is registered LOW.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
198
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
199
RTT
ODT
CKE
CK#
CK
T0
T1
T3
T5
T6
T7
(MAX)
(MIN)
tAON
tAON
T8
Completion of ODTLoff
Completion of ODTLon
T9
AL = 3
tCK
6tCK
T11
T12
RTT,nom
ODTLoff = CWL + AL - 2
T10
RTT(OFF)
RTT(ON)
CWL - 2
T14
Transitioning
T13
(MAX)
Dont Care
tAOF
AOF (MIN)
T15
0.5tCK 0.2tCK
tCK
ps
tCK
4tCK
See Table 55
(page 76)
tCK
CWL +AL - 2
RTT(OFF) tAOF
RTT(ON)
tCK
Unit
CWL + AL - 2
tAON
Defined to
ODTLon = CWL + AL - 2
ODTH4 (MIN)
AL = 3
Note:
T2
T4
tAOF
ODT minimum HIGH time after WRITE Write registration with ODT HIGH
(BL8)
ODTH8
tAON
ODTH4
ODTLoff
Begins at
Description
ODTLon
Symbol
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
RTT
ODT
Command
CKE
CK#
CK
NOP
T0
NOP
T1
Notes:
NOP
T2
NOP
T4
NOP
T5
NOP
T6
ODTH4 (MIN)
NOP
T8
(MAX)
(MIN)
tAON
tAON
ODTH4
NOP
T9
RTT,nom
tAOF
ODTLon = WL - 2
ODTLoff = WL - 2
WRS4
T7
tAOF
(MIN)
NOP
T10
(MAX)
tAON
NOP
T11
(MIN)
tAON
(MAX)
NOP
T12
NOP
T14
RTT,nom
ODTLoff = WL - 2
NOP
T13
NOP
T16
Transitioning
NOP
T15
Dont Care
(MAX)
(MIN)
tAOF
tAOF
NOP
T17
1.
2.
3.
4.
ODTLon = WL - 2
ODTH4
NOP
T3
200
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
201
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
Valid
Address
DQ
DQS, DQS#
RTT
ODT
READ
T0
Command
CK#
CK
NOP
T1
Note:
NOP
T2
NOP
T5
NOP
T6
RL = AL + CL
RTT,nom
ODTLoff = CWL + AL - 2
NOP
T4
NOP
T7
NOP
T8
NOP
T9
(MAX)
(MIN)
tAOF
tAOF
NOP
T11
DI
b
DI
b+1
DI
b+2
NOP
T12
ODTLon = CWL + AL - 2
NOP
T10
DI
b+3
DI
b+4
NOP
T13
DI
b+5
DI
b+6
NOP
T14
tAON
NOP
T17
Dont Care
(MAX)
RTT,nom
NOP
T16
Transitioning
DI
b+7
NOP
T15
1. ODT must be disabled externally during READs by driving ODT LOW. For example, CL = 6; AL = CL - 1 = 5; RL = AL
+ CL = 11; CWL = 5; ODTLon = CWL + AL - 2 = 8; ODTLoff = CWL + AL - 2 = 8. RTT,nom is enabled. RTT(WR) is a Dont
Care.
NOP
T3
202
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
203
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
T0
T1
Note:
T2
tIS
T4
(MIN)
tAONPD
tAONPD
T5
1. AL is ignored.
tIH
T3
(MAX)
T6
T7
T8
T9
Description
Symbol
tAONPD
tAOFPD
Table 90: Asynchronous ODT Timing Parameters for All Speed Bins
RTT
ODT
CKE
CK#
CK
RTT,nom
T10
tIH
T11
tIS
T12
Min
T14
(MAX)
(MIN)
tAOFPD
tAOFPD
T13
Max
8.5
8.5
T16
Transitioning
T15
ns
ns
Unit
Dont Care
T17
204
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
205
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
206
DRAM RTT C
asynchronous
ODT C
asynchronous
DRAM RTT B
asynchronous
or synchronous
ODT B
asynchronous
or synchronous
DRAM RTT A
synchronous
ODT A
synchronous
Command
CKE
CK#
CK
NOP
T0
REF
T1
Note:
NOP
T2
RTT,nom
T5
tANPD
NOP
ODTLoff
NOP
T4
NOP
T6
NOP
T8
NOP
T9
RTT,nom
(MAX)
(MIN)
(MIN)
tAOF
tAOF
tRFC
NOP
T7
1. AL = 0; CWL = 5; ODTL(off) = WL - 2 = 3.
RTT,nom
NOP
T3
NOP
T11
(MIN)
(MAX)
NOP
T12
tAOFPD
tAOFPD
NOP
T10
NOP
Ta0
Indicates break
in time scale
NOP
T13
Figure 117: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry
tANPD
tAOFPD
NOP
Ta3
Dont Care
(MAX)
(MIN)
NOP
Ta2
tAOFPD
Transitioning
NOP
Ta1
+ tXPDLL
Max
tANPD
or
tRFC
Greater of:
tANPD
Min
Description
Table 91: ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
207
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
DRAM RTT C
synchronous
ODT C
synchronous
ODT B
asynchronous
or synchronous
RTT B
asynchronous
or synchronous
DRAM RTT A
asynchronous
ODT A
asynchronous
COMMAND
CKE
CK#
CK
T0
RTT,nom
T1
(MIN)
tANPD
Ta0
NOP
Ta1
NOP
Ta2
tAOFPD
NOP
Ta3
NOP
Ta5
(MIN)
tXPDLL
NOP
Ta6
(MAX)
RTT,nom
tAOFPD
NOP
Ta4
1. CL = 6; AL = CL - 1; CWL = 5; ODTLoff = WL - 2 = 8.
RTT,nom
(MAX)
Note:
tAOFPD
tAOFPD
T2
NOP
Tb0
NOP
Tb1
NOP
Tb2
Tc1
NOP
Indicates break
in time scale
NOP
Tc0
Figure 118: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit
Transitioning
ODTLoff
NOP
Tc2
(MIN)
(MAX)
NOP
Td1
Dont Care
tAOF
tAOF
NOP
Td0
208
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
209
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
210
Command
CK#
CK
EKC
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
REF
T0
Note:
NOP
T1
tANPD
NOP
T3
NOP
T5
NOP
T7
(MIN)
tANPD
tRFC
T8
NOP
NOP
T9
NOP
T6
NOP
T4
1. AL = 0, WL = 5, tANPD = 4.
NOP
T2
tXPDLL
NOP
Ta1
Indicates break
in time scale
NOP
Ta0
NOP
T0
Note:
NOP
T1
tANPD
NOP
T3
NOP
T4
NOP
T5
NOP
T6
tXPDLL
tANPD
NOP
T7
NOP
T8
1. AL = 0, WL = 5, tANPD = 4.
NOP
T2
NOP
T9
Ta1
NOP
Indicates break
in time scale
NOP
Ta0
Figure 120: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping
CKE
Command
CK#
CK
Figure 119: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping
Transitioning
NOP
Ta2
Ta3
NOP
Ta3
NOP
Transitioning
NOP
Ta2
Dont Care
NOP
Ta4
Dont Care
NOP
Ta4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
211
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.