CMOS transistor circuits

CMOS technology
The MOS transistor
Electrical behavior of the MOS
transistor

Contents

Importance of MOS technology

The MOS transistor
Manufacture steps of MOS technology
Electrical model of the MOS transistor
Simple circuits with MOS transistors
Noise model

Origin of the Integrated Circuits

Theory of MOS integrated circuits was developed in
1925 with the invention of MOS-transistor.
The first process of fabrication with enough robustness
only succeeded in the 60s.
Quality control problems as well as the use of some
materials only allow to develop commercial products
already in the 70s.
Due to its simplicity and low fabrication cost, MOS
technology is usually preferred rather than any other.

Moores Law
In 1965 Gordon Moore noted that the number of
transistors in a IC doubled every two years
This observation become the roadmap for every IC
manufacture leading to a doubling in the performance of
IC every two years
Sometime soon it will be impossible to continue to
reduce the size of the transistors due to physical limits

CMOS technology
There are several types of technologies available to build
IC (BiCMOS, bipolar, GaAs, etc)
A large part of the success of the MOS transistor is due
to the fact that it can be scaled to increasingly smaller
dimensions, which results in higher performance.
The ability to improve performance consistently while
decreasing power consumption has made CMOS
architecture the dominant technology for integrated
circuits.
Due to its versatility CMOS technology represents the
majority of the manufactured IC in the world.

Available elements in CMOS technology

Capacitors with a good relative accuracy (+/- 0.1 a 0.4%)
and reasonable absolute accuracy (5 a 15 %);
Poly-silicon and diffusion resistors with good linearity but
with bad absolute accuracy (+/- 25 a 50%);
NMOS e PMOS transistors. Very good performance in
terms of speed and accuracy;
Bipolar NPN or PNP transistors depending whether the
substrate is P-type or N-type. Very low current-gain and
very weak speed performance due to the existence of a
parasitic collector connected to the substrate.

A cross section of a MOS transistor

Gate
SiO2

W
n+

n+

n-channel

p- substrate

G
S

W
L
B
L

Most commonly used symbols for

MOS transistors & conventions

NMOS (symbol 1)

PMOS (symbol 1)

NMOS (symbol 2)

PMOS (symbol 2)

VSG
ID

IG=0

ID
VDS

VGS

VSD

IG=0

NMOS
S

PMOS
D

CMOS fabrication steps

The manufacture of CMOS ICs is based on the
repetition of 5 steps:
Creating patterns on the wafers using photo
lithography (patterns defined by masks)
Oxidizing the wafer in order to create a layer of SiO2
(silicon dioxide) or nitrate oxide
Etching material from the wafer (where not protected
by masks)
Implanting and diffusing impurities
Material deposition (silicon and metal)

CMOS fabrication flow (simplified)

The process starts with silicon wafer, normally lightly doped P type

Wafer (p-)

A layer of SiO2 on top is created by oxidizing the wafer at high temperature

(dry or wet oxidation can be used)
Si02

Wafer (p-)

CMOS fabrication flow (simplified)

A a layer of photoresistant material is spread on top, exposed with UV light in
areas defined by a mask and then developed, leaving exposed areas.
Photoresist
Si02

Wafer (p-)

The unprotected oxide is removed using dry or wet etching methods.

An ion beam of doping atoms is applied to the wafer, these atoms do not
penetrate the silicon crystal where it is protected by the silicon oxide.

Si02

Wafer (p-)

CMOS fabrication flow (simplified)

The oxide is etched away and the wafer is heated in a furnace (annealing) to cause
the doping atoms to diffuse and to repair crystal defects caused by the implanting ions
n-well (n-)
Wafer (p-)

A new layer of oxide is grown on top of the wafer and etched away, this oxide is
also know as field oxide and will be used to separate the transistors
Si02

n-well (n-)
Wafer (p-)

CMOS fabrication flow (simplified)

A thin layer of oxide is grown on top of the wafer, this will become the gate oxide
Thin oxide
(gate oxide)
Si02

n-well (n-)
Wafer (p-)

Polysilicon is deposited on the wafer and then the etched away, except where
defined by a mask
Si02

n-well (n-)
Wafer (p-)

CMOS fabrication flow (simplified)

The thin oxide is etched away, the opening defines the active areas where P or N
doping atoms will be implanted and diffused.
Si02

n-well (n-)
Wafer (p-)

Si02

n-well (n-)
Wafer (p-)

CMOS fabrication flow (simplified)

The process is repeated for the P+ active areas and finally the transistors are
defined.

Si02

N+

N+

P+

P+

n-well (n-)
Wafer (p-)

The next steps might apply Titanium or other metal on top of the polysilicon in
order to reduce its resistance (salicide)

The latch-up problem

Vss

Vdd

Si02

P+

N+

N+

P+

P+

n-well (n-)
Wafer (p-)

Rnwell
Rsub

P+

N-

P-

N+

N+

The latch-up problem

Vdd

IC2

Vdd

Rnwell

Rnwell

Vdd

Vdd-0.7 V

IC1

IC2

IC1

Vss

0.7 V

Rsub

Rsub
Vss

OFF State
IC1=IC2=0A

Vss

ON State
IC1and IC2 can be large !!!

The MOS capacitor behavior

VG=0V

N+

++++++++++++++++++++
++++++++++++++++++++
++++++++++++++++++++

Depletion zone

N+

VB=0V

P-

Depletion zone

VG>0V

+ + + + + + + + + + + + +
++++++++++++++++++++
++++++++++++++++++++
VB=0V

N+

N+
P-

The MOS capacitor behavior

S

N+

VG=VT

Depletion zone

++++++++++++++++++++
++++++++++++++++++++
VB=0V

N+

VG>VT

-----------------------------Depletion zone

N+
P-

N+

++++++++++++++++++++
channel

VB=0V

P-

The MOS capacitor behavior

VG < 0: Positive charges are concentrated in the channel
region under the gate terminal;
0 < VG < VT: The channel region looses carriers
becoming progressively a depletion layer
VG > VT : The electric field is strong enough to attract
electrons that create an inversion conducting layer. The
capacitance value is restored to its maximum.

The MOS transistor in the cut-off

and weak inversion
VS = 0 e 0 < VDS << 1
VGS < 0, Drain and substrate terminals form a reversed-biased p-n
junction => ID = 0;
0 < VGS < VT, The channel regions is in depletion => ID 0
The device is operating in weak inversion.

N+

VB=VT

Depletion zone

++++++++++++++++++++
++++++++++++++++++++
VB=0V

VD>0V

N+
P-

The MOS transistor in the linear

region
For VGS > VT the channel region is inverted into n-type, and
the drain becomes connected to the source. A positive
drain current occurs.
For low VDS voltages (close to 0, the channel region
behaves like a resistor and we have that ID = VDS / R, where
R is the channel resistance.
W
I D = n Cox (VGS VT ) VDS
L
VDS
1
R=
=
W
ID
n Cox (VGS VT )
L
VGS VT > "overdrive" or VDS saturation voltage (VDSsat)

The MOS transistor in the triode

region
For VGS > VT e 0 < VDS < (VGS - VT) the channel potential is not zero
anymore and the drain current becomes defined by:

VDS
W
I D = n Cox (VGS VT ) VDS

L
2
VDSsat = (VGS VT )

The MOS transistor in the

saturation (active) region
For VGS > VT e VDS > (VGS - VT) the gate-to-channel voltage close
To the drain is not enough to keep the channel formed. The channel
is then interrupted by a depletion region (is pinched-off).

N+
channel

VD>VG -VT

VG>VT

N+

Depletion zone
pinch-off
VB=0V

P-

The MOS transistor in the

saturation (active) region
ID current becomes nearly constant and defined by:

I D = I D (VDS ) I Dsat
VDSsat = (VGS
For

n Cox W

(VGS VT )

2 L
VT ) > VDS saturation voltage

VDS > VDSsat

For analogy with the BJTs, this region is also often called
active region.

Models and operating regions

Summary
ID

ID

Strong
Inversion
Weak
Inversion

Active
region
VGS=constant

Linear
region

Cut-off
VTn

Triode
region

VGS

Vdsat = Veff = (VGS - VT)

VDSsat

VDS

Models and operating regions

(channel modulation effects)
In fact, ID increases a little with VDS ! This is due to an effective
shift of the pinch-off point leading to a smaller channel length
ID becomes dependent of VDS accordingly to:

I D = I D (VDS ) I Dsat

nCox W

(VGS VTn ) (1 + VDS )

2

2 L
channel modulation constant

This effect is much more significant when short channels

(minimum L) are used! Avoid using minimum channel lengths
in analogue design whenever necessary!

Models and operating regions

(channel modulation effects)
ID

Channel
modulation

Short-channel
effects
VGS=constant

VDSsat

VDS

Models and operating regions

(body effect)
It exists whenever VS is different from zero.
The threshold voltage, VTn, becomes dependent (increases) with
VSB = VS - VB.
VTn = VTOn +

2 p + VSB 2 2 p

2 S q N imp
Cox

VTO : threshold voltage for VSB = 0;

P : 0.3 V, contact potential;

S = 0 K S ; K S = 11.7;
N imp : carrier density at the surface;

Models and operating regions

(some weak inversion details)
For 0 < VGS < VTn , ID current is not zero! In fact, the density of
carriers in the channel is not zero but it increases exponentially
with VGS.
ID (VGS ) is an exponential relationship and the MOS device
behaves as a slow bipolar transistor;

V DS >> VT = KT

I D = I D0 e

VGS
KT
n
q

25mV

; n {1,2};

This region is very useful in low-speed ultra-low power circuits;

Very high dc gains can be achieved.

Models and operating regions

(generalizing for the PMOS transistor)
2 main voltages exchange signals (source terminal at a higher
voltage);
Threshold voltage, VTp , is negative;
Mobility of holes is 1/3 a 1/2 smaller than the mobility of electrons:
p = n / 2.5;
All expressions derived are valid for all regions.

Biasing MOS transistors (DC)

(simple current-mirrors)
Vdd

MB

M1
Iout

Iin
WM1 = 10* WMB
L M1 = L MB

Iout(Iin) = ?

Small signal analysis

(saturation region)

Small signal analysis

(saturation region)

Small signal analysis

(saturation region and low-frequency)
G

vGS
gm.vGS
S

rds=1/gds
gsb.v SB
vSB

B
Neglecting the body-effect gsb = 0

MOS parasitic capacitances

VG>VT

N+

VD>VG -VT

C GD

C GS
Depletion zone

N+

C SB

P-

C DB

Small signal analysis

(saturation region and high-frequency)
G

Cgd

D
rds=1/gds

vGS
Cgs

gm.vGS
S
Csb
B

gsb.v SB
vSB

Cdb

Small signal analysis

(saturation region and high-frequency)
Cgs = 2/3 W. L . Cox + W . Lov . Cox
[Tsividis, 1987]
(Cox -> 0.002 pF / um2 , for example)
Csb = (As + Achannel) . Cjs
(Cjs -> non-linear depletion capacitance of the
source-substrate junction (voltage dependent)).
Cdb = Ad . Cjd
(Cjd -> non-linear depletion capacitance of the
drain-substrate junction (voltage dependent)).
Cgd = W . Lov . Cox

(Miller capacitance)

Small signal analysis

(linear/triode region and high-frequency)
G

Cgs

Cgd

S
Csb

D
Cdb

rds

Small signal analysis

(linear/triode region and high-frequency)

Cgs = Cgd = 1/2 W. L . Cox + W . Lov . Cox

(Cox -> 0.002 pF / um2 , for example)
Csb = Cdb = (As + Achannel/2) . Cjs
(Cjs -> non-linear depletion capacitance of the
source/drain-substrate junction (voltage dependent)).

Small signal analysis

(cut-off region and high-frequency)
G
Cgb
Cgs
S
Csb

Cgd
D
Cdb

Cgs = Cgd = W . Lov . Cox

Cgb = W . L . Cox

NOISE
Noise can be considered as any undesired signal that is
added to the desired signal.
Noise can be divided into 2 categories:
Deterministic noise: this is due to deterministic sources such as
interference from other signals. This noise can be greatly
reduced by minimizing the coupling of the offending signals (at
system level by using appropriate filters and at physical level by
using appropriate shielding).
Random noise: this is due to random effects and it is present at a
fundamental level in most electronic components, it can be
reduced by careful circuit design.

The objective is to maximize the Signal to Noise ratio

Properties of random signals

It is not possible to predict the value of a random signal at a given
time instant.
It is possible to predict its statistical properties, such as average value
and power value (standard deviation). P = lim T / 2 vN (t )2 dt
N

Signal 1 P=1 W

T T / 2

Signal 2 P=1 W

Properties of random signals

A random signal can also be characterized by its power spectral
density (PSD).
The PSD shows the average power of the signal per bandwidth.
SN ( f )

PN ( f )

The power of a random signal can be calculated using:

PN = S N ( f )df
0
The PSD of a filtered random signal can be calculated using:

S Nout ( f ) = H ( f ) S Nin ( f )df

0

Noise in electrical circuits

In electrical circuits there are 5 common noise sources:

Shot noise
Thermal noise
Flicker noise
Burst noise
Avalanche noise

Shot noise
Shot noise is always associated with current flow. Shot
noise results whenever charges cross a potential barrier,
such as a PN junction. A carrier crossing the potential
barrier is a purely random event. Thus the instantaneous
current, I, is composed of large number of random,
independent current pulses with an average value, ID.
Shot noise is independent of temperature.
Shot noise can be represented as a noise current with a
power spectral density given by: S I = 2 qe I D

Thermal noise
Arises from the thermal fluctuations in the
electron density within a conductor.
Statistical fluctuation of electric charge exists in all conductors,
producing random variation of potential between the ends of the
conductor. The electric charges in a conductor are found to be in
a state of thermal agitation, in thermodynamic equilibrium with
the heat motion of the atoms of the conductor. The manifestation
of the phenomenon is a fluctuation of potential difference
between the terminals of the conductor J.B. Johnson

Experimentally demonstrated by Johnson in

1926
Theoretically derived by Nyquist in 1928

RC output noise voltage

Flicker noise
Flicker noise is also called 1/f noise. It is present in all active devices
and has various origins.
Normally it is associated with impurity atoms in the semiconductor
crystal.
These impurities create energy states that trap and release the
carriers.
K
1
SVf =

The power spectral density is given by:

Cox W L f
Normally PMOS transistors have less flicker noise than NMOS
transistors
If the physical size of the transistor increases the corresponding
flicker noise decreases