Ec2357

EC2357
VLSI DESIGN LABORATORY
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EC2357 VLSI Design Laboratory

LIST OF EXPERIMENTS
1. Design Entry and simulation of combinational logic circuits (8 bit adders, 4 bit multipliers,
address decoders, multiplexers), Test bench creation, functional verification, and concepts of
concurrent and sequential execution to be highlighted.
2. Design Entry and simulation of sequential logic circuits (counters, PRBS generators,
accumulators). Test bench creation, functional verification, and concepts of concurrent and
sequential execution to be highlighted.
3. Synthesis, P&R and Post P&R simulation for all the blocks/codes developed in Expt. No. 1
and No. 2 given above. Concepts of FPGA floor plan, critical path, design gate count, I/O
configuration and pin assignment to be taught in this experiment.
4. Generation of configuration/fuse files for all the blocks/codes developed as part of Expt.1.
and Expt. 2. FPGA devices must be configured and hardware tested for the blocks/codes
developed as part of Expt. 1. and Expt. 2. The correctness of the inputs and outputs for each
of the blocks must be demonstrated atleast on oscilloscopes (logic analyzer preferred).
5. Schematic Entry and SPICE simulation of MOS differential amplifier. Determination of
gain, bandwidth, output impedance and CMRR.
6. Layout of a simple CMOS inverter, parasitic extraction and simulation.
7. Design of a 10 bit number controlled oscillator using standard cell approach, simulation
followed by study of synthesis reports.
8. Automatic layout generation followed by post layout extraction and simulation of the
circuit studied in Expt. No.7.
Note 1. For Expt. 1 To 4 can be carried out using Altera (Quartus) / Xilinx (Alliance)/
ACTEL (Libero) tools.
Note 2. For expt. 5-8 introduce the student to basics of IC design. These have to be
carried out using atleast 0.5u CMOS technology libraries. The S/W tools needed
Cadence / MAGMA / Tanner.
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Expt. No:
Date:
STUDY OF VERILOG HDL AND SPARTAN-3E FPGA BOARD
AIM:
To study Verilog HDL, Spartan-3E FPGA board and the related software.
SOFTWARE USED:
Xilinx 14.3
DEVICE USED:
Spartan-3E FPGA 250S
THEORY:
INTRODUCTION TO VERILOG HDL:
Verilog HDL is one of the Hardware Description Languages (HDL) used to describe a
digital system. VHDL is the other one. Verilog HDL allows a hardware designer to describe
designs at a high level of abstraction such as an the architectural or behavioral level as a set
of modules. Modules can either be specified behaviorally or structurally (for a combination of
two). A behavioral specification defines the behavior of a digital system (module) using
traditional programming language constructs. E.g. if assignment statements. A structural
specification expresses the behavior of a digital system (module) as a hierarchical
interconnection of sub modules. At the bottom of the hierarchy the components must be
primitives or specified behaviorally. Verilog provides the following gate level primitives:
And/nand
or/nor
xor/xnor
buf/not
bufif0/notif0
bufif1/notif1
logical AND/NAND
logical OR/NOR
logical XOR/XNOR
buffer/inverter
tristate with low enable
tristate with high enable
The structure of a module is the following:

Module <module name> (<port list>);
<(declares)>
<module items>
End module.
The <module name> is an identifier that uniquely names the module. The <port list> is a list
of input, in-out and output ports which are used to connect to other modules. The <declares>
section specifies data objects as registers, memories and wires as well as procedural
constructs such as functions and tasks. The <module items> may be initial constructs, always
constructs, continuous assignments or instances of modules.
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OPERATORS:
Bitwise operators:
Arithmetic:
Unary reduction:
Logical:
Equality:
Identity:
Relational:
Logical shift :
Conditional:
Concatenate:
Replicate:
~(not), &(and), |(or) and ^(xor)

+, -, *, /
&, &&, |, ~|, ^, ~ ^
!, &&, ||
==, != (0,1)
===, !== (0,1,x,z)
<,>,<=,>=
<<, >>
?:
{}
{{}}
DESIGN FLOW:
Fig. Flow chart of VLSI design flow
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DESIGN ENTRY: The designed circuit is specified either by means of a schematic diagram
or by using a hardware description language, such as Verilog or VHDL.
SYNTHESIS: The entered design is synthesized into a circuit that consists of the logic
elements (LEs) provided in the FPGA board.
FUNCTIONAL SIMULATION: The synthesized circuit is tested to verify its functional
correctness. This simulation does not take into account any timing issues. A test bench is
HDL code that allows you to provide a repeatable set of stimuli with clock and input dat for
error checking, file input and output and conditional testing.
FITTING: The CAD filter told determines the placement of LEs defined in the netlist into
the LEs in the actual FPGA chip. It also chooses routing wires in the chip to make the
required connections between specific LEs.
TIMING ANALYSIS: Propagation delays along the various paths in the fitted circuit are
analyzed to provide an indication of the expected performance of the circuit.
TIMING SIMULATION: The fitted circuit is tested to verify both its functional correctness
and timing.
PROGRAMMING AND CONFIGURATION: The designed circuit is implemented in a
physical FPGA chip by programming the configuration switches that configure the LEs and
established the required wiring connections.
PROCEDURE OF XILINX 14.3 SOFTWARE:
1. Start Xilinx ISE 13.1, click on CREATE A NEW PROJECT and then click on
Next.
2. Select youre working directory, give the name of the project, then click on NEXT.
3. Select the device family (Spartan 3E), Device (XC3S250E), package (PQ208), Speed
grade (4), Synthesis tool (XST [VHDL/VERILOG]), simulator (ISim) and preferred
language (Verilog) from the available device list, and then click NEXT and click
FINISH.
4. Write the HDL code and be careful to give the entity name the same as project name.
After writing the code save the file and click on Synthesis XST.
5. If the HDL code is error free a green check mark will be shown on the synthesis XST.
6. Select simulation then double click on Simulate Behavioral Model (here we can
change the level of abstraction. i.e. structural/behavioral/dataflow/switch level)
7. If there is zero error a new window will be shown. Apply the desired input as 1s and
0s and check whether the outputs are correct or not in the output waveform.
8. Expand the user constraints n the processes for source window and double click
Assign package pins (with ISE 13.1 web pack is called I/O floor plan presynthesis).
This is where you tell Xilinx which pins on Spartan 3E will be used.
9. In the Design object list I/O pins window type the pin numbers in the following pin
assignments under the heading LOC. This action will create a .UCF file for the
top_level_struct file and will contain the pin assignments for the Spartan-3E.
10. Make sure that the top_level_struct file is selected in the sources window.
11. Expand the Synthesis-XST in the Processes window and then double click it. This
action will check the syntax of the source code for top_level_struct and convert the
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source code into a netlist of gates. A synthesis report will also be produced. When the
synthesis is finished, green check marks should be displayed indicating that
top_level_struct has compiled successfully.
12. Expand the Implement design process and double click on it. This is where the
netlist is translated, mapped, placed and routed for the logic circuits of the Spartan-3E
FPGA. After this process has been run, green check mark should be displayed.
13. Expand the Generate Programming file process and double click it. This process
creates
A bit file that is used to program the Spartan-3E chip. Again, after this process is
finished, green check mark should be shown.
14. Expand the Implement design and double click on Generate programming file.
15. Right click on the depiction of the Spartan-3E chip and select program. If the
download was successful, the message Program succeeded will be displayed.
RESULT:
The verilog modelling methodology and Spartan 3E FPGA board were studied.
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Expt. No:
Date:
DESIGN ENTRY AND SIMULATION OF COMBINATIONAL CIRCUITS
AIM:
To design and implement the following combinational circuits using Verilog HDL and
testbench circuits.
1. 8 bit adders,
2. 4 bit multipliers,
3. Address decoders,
4. Multiplexers
APPARATUS REQUIRED:
PC with Windows XP.

XILINX 14.3.
THEORY:
8-Bit Addition (Ripple Carry Adder)
The n-bit adder built from n one bit full adders is known as ripple carry adder
because of the carry is computed. The addition is not complete until n-1th adder has
computed its Sn-1 output; that results depends upon ci input, n and so on down the line, so
the critical delay path goes from the 0-bit inputs up through cis to the n-1 bit.(We can find
the critical path through the n-bit adder without knowing the exact logic in the full adder
because the delay through the n-bit adder without knowing the exact logic in the full adder
because the delay through the n-bit carry chain is so much longer than the delay from a and b
to s). The ripple-carry adder is area efficient and easy to design but it is when n is large. It can
also be called as cascaded full adder.
4-Bit Multiplier
Binary multiplication can be accomplished by several approaches. The approach
presented here is realized entirely with combinational circuits. Such a circuit is called an
array multiplier. The term array is used to describe the multiplier because the multiplier is
organized as an array structure. Each row, called a partial product, is formed by a bit-by-bit
multiplication of each operand.
For example, a partial product is formed when each bit of operand a is multiplied by
b0, resulting in a3b0, a2b0,a1b0, a0b0. The binary multiplication table is identical to the
AND truth table.
Each product bit {o(x)}, is formed by adding partial product columns. The product
equations, including the carry-in {c(x)}, from column c(x-1), are (the plus sign indicates
addition not OR). Each product term, p(x), is formed by AND gates and collection of product
terms needed for the multiplier. By adding appropriate p term outputs, the multiplier output
equations are realized, as shown in figure.
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Address Decoder
A decoder is a combinational circuit that converts binary information from n input
lines to a maximum of 2n unique output lines. It performs the reverse operation of the
encoder. If the n-bit decoded information has unused or dont-care combinations, the decoder
output will have fewer than 2n outputs. The decoders are represented as n-to-m line decoders,
where m 2n. Their purpose is to generate the 2n (or fewer) minterms of n input variables.
The name decoder is also used in conjunction with some code converters such as BCD-toseven-segment decoders. Most, if not all, IC decoders include one or more enable inputs to
control the circuit operation. A decoder with an enable input can function as a de-multiplexer
4x1 Multiplexer
A digital multiplexer is a combinational circuit that selects binary information from
one of many input lines and directs it to a single output line. Multiplexing means transmitting
a large number of information units over a smaller number of channels or lines. The selection
of a particular input line is controlled by a set of selection lines. Normally, there are 2n input
lines and n selection lines whose bit combinations determine which input is selected. A
multiplexer is also called a data selector, since it selects one of many inputs and steers the
binary information to the output lines. Multiplexer ICs may have an enable input to control
the operation of the unit.
The size of the multiplexer is specified by the number 2n of its input lines and the
single output line. In general, a 2n to 1 line multiplexer is constructed from an n to 2n
decoder by adding to it 2n input lines, one to each AND gate. The outputs of the AND gates
are applied to a single OR gate to provide the 1 line output.
PROCEDURE:
Next.
2. Select your working directory, give the name of the project, then click on NEXT.
FINISH.
5. In the design window change into simulation and double click behavioral check
syntax.
6. If the HDL code is error free a green check mark will be shown on the behavioral
check syntax.
9. Create a new verilog test fixture and give the various input constraints and save the
file and check if any errors are present.
10. Simulate the testbench and analyze the output waveform.
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8-Bit Addition (Ripple Carry Adder)
Logic Diagram:
MULTIPLEXER
Truth Table
Select lines
Output
Logic Diagram
sel1
sel0
i0
i1
i2
i3
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4-Bit Multiplier
4 X 4 Array Multiplier:
a3b3
a3
a2
a1
b3
b2
b1
a3b0 a2b0 a1b0
a3b1 a2b1 a1b1 a0b1
a3b2 a2b2 a1b2 a0b2
a2b3 a1b3 a0b3
o7
o6
o5
a0b0 = p0
a1b0 = p1
a0b1 = p2
a2b0 = p3
a1b1 = p4
a0b2 = p5
a3b0 = p6
a2b1 = p7
o4
o3
o2
a0
b0
a0b0
o1
a1b2 = p8
a0b3 = p9
a3b1 = p10
a2b2 = p11
a1b3 = p12
a3b2 = p13
a2b3 = p14
a3b3 = p15
Logic Diagram:
P15
P14 P13
P11,P10
FA
FA
P4 P3
P2 P1
HA
HA
HA
FA
FA
P7 P6
P0
P8
P12
FA
P9
FA
O7
O6
FA
O5
FA
O4
HA
O3
O2
O1
O0
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Address Decoder
Truth Table:
INPUTS
DIN
X
Y
1
0
0
Logic Diagram
OUTPUTS
D0 D1 D2 D3
1
0
0
0
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Programs:
Addition using Dataflow modeling
module addition8bit(a,b,oup);
input [7:0] a;
input [7:0] b;
output [8:0] oup;
assign oup = a + b;
endmodule
Ripple Carry Adder using

Structural Modelling
module ripplecarry_adder(a,b,oup);
input [7:0] a,b;
output [8:0] oup;
wire [6:0]c;
parameter cin=1'b0;
Full Adder using Dataflow Modelling

module fulladder(cout,sum, in1,in2,cin);
output cout;
output sum;
input in1,in2,cin;
assign {cout,sum}= in1 + in2 + cin;
endmodule
// instantiating 1b-ti full adders

fulladder f1(c[0],oup[0], a[0],b[0],cin);
fulladder f2(c[1],oup[1], a[1],b[1],c[0]);
fulladder f8(oup[8],oup[7], a[7],b[7],c[6]);
endmodule
Multiplier using Dataflow Modelling

module mult4bit(a,b,op);
input [3:0] a;
input [3:0] b;
output [7:0]op;
assign op= a * b;
endmodule
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2 x 4 Decoder using Gate Level Modeling

module decoder_2to4_gates (din,x,y,d);
input din,x,y;
output [0:3];
wire [1:0]n;
not g1(n[1],x);
not g2(n[0],y);
and g3 (d[0],n[1],n[0]);
and g4 (d[1],n[1],y);
and g5 (d[2],x,n[0]);
and g6 (d[3],x,y);
endmodule
2 x 4 Decoder using Dataflow Modeling

module decoder_2to4_dataflow(din,x,y,d);
input din,x,y;
output [0:3]d;
assign d= {(din & (~x)&(~y)),(din & (~x)&(y)),(din & (x)&(~y)),(din & (x)&(y))};
endmodule
2 x 4 Behaviour (CASE) Modelling
module decoder_2to4_case(din,x,y,d);
input din,x,y;
output reg [0:3]d;
always @(din)
begin
case (din)
2'b00:d=4'b1000;
2'b01:d=4'b0100;
2'b10:d=4'b0010;
2'b11:d=4'b0001;
default:d=4'bxxxx;
endcase
end
endmodule
4x1 Multiplexer Gate Level Modelling

module mux_4X1_gate(d,sel,y);
input [3:0]d;
2 x 4 Behaviour (IF) Modelling

module decoder_2to4_if(din,x,y,d);
input din,x,y;
output reg [0:3]d;
always @(din)
begin
if (din)
begin
if (x==0 && y==0)
d=4'b1000;
else if (x==0 && y==1)
d=4'b0100;
else if (x==1 && y==0)
d=4'b0010;
else
d=4'b0001;
end
end
endmodule
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input [1:0]sel;
output y;
wire [3:0]w;
and g0(w[0],d[2],~sel[0],~sel[1]);
and g1(w[1],d[1],sel[0],~sel[1]);
and g2(w[2],d[2],~sel[0],sel[1]);
and g3(w[3],d[3],sel[0],sel[1]);
or g4(y,w[0],w[1],w[2],w[3]);
endmodule
4x1 Multiplexer Dataflow Modelling
module mux_4X1_dataflow(d,sel,y);
input [3:0]d;
input [1:0]sel;
output y;
assign y = (d[0] & ~sel[0]& ~sel[1])|(d[1] & sel[0] & ~sel[1])| (d[2] & ~sel[0] & sel[1])|
(d[3] & sel[0] & sel[1]);
endmodule
4x1 Behaviour (CASE) Modelling
module mux_4X1_behav_case(d,sel,y);
input [3:0]d;
input [1:0]sel;
output y;
reg y;
always @(d or sel)
begin
case (sel)
2'b00:y=d[0];
2'b01:y=d[1];
2'b10:y=d[2];
2'b11:y=d[3];
default:y=1'bx;
endcase
end
endmodule
4x1 Behaviour (IF) Modelling

module mux_4X1_behav_if(d,sel,y);
input [3:0]d;
input [1:0]sel;
output y;
reg y;
always @(d or sel)
begin
if (sel==00)
y=d[0];
else if (sel==01)
y=d[1];
else if (sel==10)
y=d[2];
else
y=d[3];
end
endmodule
RESULT:
The combinational circuits were designed and, HDL codes were written and verified using
Testbench circuits.
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Expt No:
Date:
DESIGN ENTRY AND SIMULATION OF SEQUENTIAL CIRCUITS

AIM:
To design and implement the following sequential circuits using Verilog HDL and
verify using the testbench
1. Counters,
2. PRBS generators,
3. Accumulators
APPARATUS REQUIRED:
PC with Windows XP.

Xilinx 14.3
THEORY:
Counters
Synchronous counters are distinguished from asynchronous counters in that clock
pulses are applied to the CP inputs of all flip-flops. The common pulse triggers all the flipflops simultaneously, rather than one at a time in succession as in asynchronous counter. The
decision whether a flip-flop is to be complemented or not is determined from the values of
the J and K inputs at the time of the pulse. If J = K = 0, the flip-flop remains unchanged. If J
= K = 1, the flip-flop complements. In a synchronous binary ripple counter, the flip-flop in
the lowest-order position is complemented with very pulse. This means that its J and K
inputs must be maintained at logic-1. A flip-flop in any other position is complemented with
a pulse provided all the bits in the lower-order positions are equal to 1, because the lowerorder bits (when all 1s) will change to 0s on the next count pulse. The binary count dictates
the next higher-order bit is complemented. Synchronous binary counters have a regular
pattern and can easily be constructed with complementing flip-flops ( J K or T Type) and
gates.
PRBS Generator
PRBS generator generates pseudo random binary sequence based on the concept
of linear feedback shift register.It is pseudo because it is deterministic and after n
elements it starts to repeat itself, unlike real random sequences.
Random numbers for polynomial equations are generated by using the shift register
circuit. The random number generator is nothing but the Linear Feedback Shift Register
(LFSR). The shift registers are very helpful and versatile modules that facilitate the design of
many sequential circuits whose design may otherwise appear very complex. In its simplest
form, a shift register consists of a series of flip-flops having identical interconnection
between two adjacent flip-flops. Two such registers are shift right registers and the shift left
registers. In the shift right register, the bits stored in the flip-flops shift to the right when shift
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pulse is active. Like that, for a shift left register, the bits stored in the flip-flops shift left when
shift pulse is active. In the shift registers, specific patterns are shifted through the register.
There are applications where instead of specific patterns, random patterns are more
important.
For a 4-bit PRBS generator, LFSR consist of 4-registers connected together as a shift
register. Here, we used D flipflop as a register. The input to the first register comes from the
XOR of third and fourth output bits of the register. The inputs fed to the XOR are called
the tap sequence and are often specified with characteristic polynomial. On reset the
register must be initialized to a non zero value(all 1s).The output sequences through
all 2^n-1 combinations when clock signal is given. Obviously, its possible to get a longer msequence using more stages to the shift register. The formula connecting these is: m=2^n1.Where m is the length of the m-sequence and n is the number of shift register
stages. The pseudo-random sequences are handy for built-in-test and bit-error-rate
testing
in communication links. They are also used in many spread spectrum
communications systems such as GPS and CDMA and encoding and decoding the error
control codes. LFSRs used as a generators of pseudorandom sequences have proved
externally useful in the area of testing of VLSI chips.
PROCEDURE:
Next.
FINISH.
syntax.
check syntax.
9. Create a new verilog test fixture and give the various input constraints and save the
file and check if any errors are present.
10. Simulate the testbench and analyze the output waveform.
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COUNTER
Logic Diagram:
PRBS GENERATOR
Logic Diagram:
Page 17
Up Counter Design using Behavioral

Modelling
module counter_up(out,clk,reset);
output [3:0]out;
input clk, reset;
reg [3:0] out;
always @(negedge clk or posedge reset)
if(reset)
out <=4'b0000;
else
out<=out+1;
endmodule
Down Counter Design using

Behavioral Modelling
module
counter_up_down(out,clk,reset);
output [3:0]out;
input clk, reset;
reg [3:0] out;
if(reset)
out <=4'b0000;
else
out<=out-1;
endmodule
Up/Down Counter Design using Behavioral

Modelling
module counter_up_down(out,clk,reset,control);
output [3:0]out;
input clk, reset,control;
reg [3:0] out;
if(reset)
out <=4'b0000;
else
if (control)
out<=out+1;
else
out<=out-1;
endmodule
Mod-10 Counter Design

module counter_ten(out,clk,reset);
output [3:0]out;
input clk, reset;
reg [3:0] out;
always @(posedge clk or posedge reset)
begin
if(clk)
if(reset)
out <=4'b0000;
else
if (out==4'b1001)
out<=0;
else
out<=out+1;
end
endmodule
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Counter Design using Structural

Modelling
module counter_strutural(q,qbar,clk,reset);
output [3 : 0] q;
output [3 : 0] qbar;
input clk,reset;
wire [0 : 1] temp;
reg high;
initial
high = 1'b1;
jkff ff1 (q[0],qbar[0],high,high,clk,reset);
jkff ff2 (q[1],qbar[1],high,high,q[0],reset);
endmodule
Counter Design using Behavioral
Modelling
module counter(clk, reset,result); //,ena
input clk, reset;
output [3:0]result;
reg [3:0] result;
always @(negedge clk or posedge
reset)
begin
if (reset)
result = 0;
else
result = result + 1;
end
endmodule
JK Flip-Flop Design using Behavioral

Modelling
module jkff (q,qbar,j,k,clk,reset);
output q,qbar;
input j,k,clk,reset;
reg q,qbar;
always @ (negedge clk or reset)
if (~reset)
begin
q = 1'b0;
qbar = 1'b1;
end
else if (reset)
begin
if (j==0 && k ==0)
begin
q = q;
qbar = qbar;
end
else if ( j== 0 && k ==1)
begin
q = 1'b0;
qbar = 1'b1;
end
else if (j==1 && k == 0)
begin
q = 1'b1;
qbar = 1'b0;
end
else if (j ==1 && k ==1)
begin
q = ~q;
qbar = ~qbar;
end
else
begin
q = 1'bz;
qbar = 1'bz;
end
end
endmodule
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PRBS using Behavioral Level
module prbs(q,qb,clk,clr);
output [3:0] q,qb;
input clk,clr;
reg [3:0] tmp, tmpb;
always @(negedge clk or posedge clr)
begin
if(clr)
begin
tmp = 4'b1111;
tmpb = 4'b0000;
end
else
tmp = { tmp[2],tmp[1],tmp[0], tmp[3]^tmp[2]};
end
assign q=tmp;
assign qb=tmpb;
endmodule
PRBS using Structural Level

module prbs(q, qb,clk, rst);
output [3:0]q,qb;
input clk;
input rst;
wire d;
xor (d,q[3],q[2]);
dff f1(q[0], qb[0],d,clk,rst);
dff f2(q[1],qb[1],clk,rst);
endmodule
D Flip-Flop using Behavioral Level

module dff(q,qb,data,clk,reset);
input data, clk, reset ;
output q,qb;
reg q,qb;
always @ ( posedge clk or posedge reset )
begin
if (reset)
begin
q <= 1'b0;
qb <= 1'b1;
end
else
begin
q <= data;
qb<= ~data;
end
end
endmodule
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ACCUMULATOR
Accumulator using Behavioral Level
module accum (c, clr, d, q);
input c,clr;
input [3:0] d;
output [3:0] q;
reg [3:0] tmp;
always @(posedge c or posedge clr)
begin
if (clr)
tmp = 4'b0000;
else
tmp = tmp + d;
end
assign q= tmp;
endmodule
RESULT:
The Sequential circuits were designed and, HDL codes were written and verified using
Testbench circuits
Page 21
Expt No:
Date:
SYNTHESIZE AND PLACE & ROUTE SIMULATIONS OF COMBINATIONAL

AND SEQUENTIAL CIRCUITS
AIM:
To synthesize and post place and route simulations the following combinational and
sequential circuits using Verilog HDL
1. 8 bit adders,
4. Multiplexers
5. Counters,
6. PRBS generators,
7. Accumulators
APPARATUS REQUIRED:
PC with Windows XP.

XILINX 14.3.
PROCEDURE:
Next.
FINISH.
syntax.
check syntax.
7. In the design window change into implementation and click on Synthesis XST. If
the HDL code is error free a green check mark will be shown on the Synthesize
XST.
8. Note down the Device Utilization Summary (Number of Slices , Number of LUTs and
Number of bonded IOBs)
9. Double Click the View RTL Schematic in the process window and RTL Schematic
view of your HDL code.
10. Double Click View Technology Schematic in the process window and View the
Technology Schematic view of your HDL code.
11. In User Constraints, double click I/O Pin Planning (PlanAhead) Post synthesize.
PlanAhead window is opened.
12. Give the input ports and output port 9n the PlanAhead tool and save the configuration
and close the PlanAhead window.
Page 22
13. Double Click the Implementation Design and green check mark will be shown on the
Implementation Icon.
14. In the Design window, change into Post Route Simulation and by double clicking
the Post-Place & Route Check Syntax and if code is error free a green check mark
will be shown on the Post-Place & Route Check Syntax.
15. Double Click Simulate Post-Place & Route Model and analyze the output waveform.
16. In the design window change into Implementation and process window under
implementation Place & Route, double click the View/Edit Routed Design (FPGA
Editor), now we can see the routed design of our circuit.
Page 23
Programs:
Combinational Circuits:
Ripple Carry Adder using Structural
Modelling
module ripplecarry_adder(a,b,oup);
input [7:0] a,b;
output [8:0] oup;
wire [6:0]c;
parameter cin=1'b0;
Full Adder using Dataflow Modelling

module fulladder(cout,sum, in1,in2,cin);
output cout;
output sum;
input in1,in2,cin;
assign {cout,sum}= in1 + in2 + cin;
endmodule
// instantiating 1b-ti full adders

fulladder f1(c[0],oup[0], a[0],b[0],cin);
fulladder f8(oup[8],oup[7], a[5],b[5],c[6]);
endmodule
2 x 4 Decoder Behaviour (CASE)

Modelling
module decoder_2to4_case(din,x,y,d);
input din,x,y;
output reg [0:3]d;
always @(din)
begin
case (din)
2'b00:d=4'b1000;
2'b01:d=4'b0100;
2'b10:d=4'b0010;
2'b11:d=4'b0001;
default:d=4'bxxxx;
endcase
end
endmodule
2 x 4 Decoder Behaviour (IF) Modelling

module decoder_2to4_if(din,x,y,d);
input din,x,y;
output reg [0:3]d;
always @(din)
begin
if (din)
begin
if (x==0 && y==0)
d=4'b1000;
else if (x==0 && y==1)
d=4'b0100;
else if (x==1 && y==0)
d=4'b0010;
else
d=4'b0001;
end
end
endmodule
Sequential Circuits;
Counter Design using Structural
JK Flip-Flop Design using Behavioral
Page 24
Modelling
module counter_strutural(q,qbar,clk,reset);
output [3 : 0] q;
output [3 : 0] qbar;
input clk,reset;
wire [0 : 1] temp;
reg high;
initial
high = 1'b1;
jkff ff1 (q[0],qbar[0],high,high,clk,reset);
endmodule
Counter Design using Behavioral
Modelling
module counter(clk, reset,result); //,ena
input clk, reset;
output [3:0]result;
reg [3:0] result;
always @(negedge clk or posedge
reset)
begin
if (reset)
result = 0;
else
result = result + 1;
end
endmodule
Modelling
module jkff (q,qbar,j,k,clk,reset);
output q,qbar;
input j,k,clk,reset;
reg q,qbar;
always @ (negedge clk or reset)
if (~reset)
begin
q = 1'b0;
qbar = 1'b1;
end
else if (reset)
begin
if (j==0 && k ==0)
begin
q = q;
qbar = qbar;
end
else if ( j== 0 && k ==1)
begin
q = 1'b0;
qbar = 1'b1;
end
else if (j==1 && k == 0)
begin
q = 1'b1;
qbar = 1'b0;
end
else if (j ==1 && k ==1)
begin
q = ~q;
qbar = ~qbar;
end
else
begin
q = 1'bz;
qbar = 1'bz;
end
end
endmodule
Page 25
PRBS using Behavioral Level
module prbs(q,qb,clk,clr);
output [3:0] q,qb;
input clk,clr;
reg [3:0] tmp, tmpb;
always @(negedge clk or posedge clr)
begin
if(clr)
begin
tmp = 4'b1111;
tmpb = 4'b0000;
end
else
tmp = { tmp[2],tmp[1],tmp[0], tmp[3]^tmp[2]};
end
assign q=tmp;
assign qb=tmpb;
endmodule
RESULT:
The Combinational and Sequential circuits were designed and Verilog HDL codes were
written and verified. The verilog codes are Synthesized and Post Place and Route was done.
Page 26
Expt No:
Date:
HARDWARE IMPLEMENTATION OF COMBINATIONAL AND
SEQUENTIAL CIRCUITS
AIM:
To synthesize and post place and route simulations the following combinational and
sequential circuits using Verilog HDL
1. 8 bit adders,
4. Multiplexers
5. Counters,
6. PRBS generators,
7. Accumulators
APPARATUS REQUIRED:
PC with Windows XP.

XILINX 14.3.
Spartan 3E FPGA Kit.
PROCEDURE:
Next.
FINISH.
syntax.
check syntax.
7. In the design window change into implementation and click on Synthesis XST. If
the HDL code is error free a green check mark will be shown on the Synthesize
XST.
8. Note down the Device Utilization Summary (Number of Slices , Number of LUTs and
Number of bonded IOBs)
9. Double Click the View RTL Schematic in the process window and RTL Schematic
view of your HDL code.
10. Double Click View Technology Schematic in the process window and View the
Technology Schematic view of your HDL code.
11. In User Constraints, double click I/O Pin Planning (PlanAhead) Post synthesize.
PlanAhead window is opened.
Page 27
12. Give the input ports and output port 9n the PlanAhead tool and save the configuration
and close the PlanAhead window.
13. Double Click the Implementation Design and green check mark will be shown on the
Implementation Icon.
14. In the Design window, change into Post Route Simulation and by double clicking
the Post-Place & Route Check Syntax and if code is error free a green check mark
will be shown on the Post-Place & Route Check Syntax.
15. Double Click Simulate Post-Place & Route Model and analyze the output waveform.
16. In the design window change into Implementation and process window under
implementation Place & Route, double click the View/Edit Routed Design (FPGA
Editor), now we can see the routed design of our circuit.
17. A BIT file will be generate by double clicking the Generate Programming File.
18. The BIT file is loaded in the FPGA processor through JTAG or USB cable and the
output can be verified using the hardware kit.
19. MCS file is created and loaded into the PROM for verification.
20. By using ChipScope tool outputs waveforms in the PC can be controlled by Hardware
kit for Clock based circuits.
Procedure for ChipScope:
1. Click the project menu and then select new source.
2. Select Chip Scope Definition and Connection File and enter the file name, click Next
and click finish.
3. Double click your .cdc File.
4. Now your chip scope pro application will open, and then click next.
5. Mention the Number of Input Trigger Port and Mention the Trigger Width then Click
Next.
6. Click Modify Connections and Select your clk_BUFGP then click Make connections.
7. Mention your Trigger input then click Make connections, click OK.
8. Click Return to Project Navigator and then click YES.
9. Right click the Analyze Design Using Chip scope and Click Run.
10. Connect your board using JTAG or USB.
11. Open the Chip scope Pro Analyzer.
12. Click JTAG Chain and select Xilinx Parallel cable, Click Auto Detect Cable Type
then click OK.
13. Your IC has been detected then clicks OK. Now Select My Device and click
configure.
14. Click Select New File and Select your .bit file and click open.
15. Click Select New File Select your .cdc file and click open and then click OK.
16. Open the UNIT: 0 then Right click the Trigger setup and open the trigger setup.
17. Now the Trigger setup will be appear.
18. Right Click the Waveform and Open Waveform.
19. Right Click the Trigger setup => click trigger run mode =>click Repetitive, click
RUN.
20. You can change the input in your board the corresponding output is show in your PC.
Page 28
2 x 4 Decoder using Gate Level Modeling

module decoder_2to4_gates (din,x,y,d);
input din,x,y;
output [0:3];
wire [1:0]n;
not g1(n[1],x);
not g2(n[0],y);
and g3 (d[0],n[1],n[0]);
and g4 (d[1],n[1],y);
and g5 (d[2],x,n[0]);
and g6 (d[3],x,y);
endmodule
Accumulator using Behavioral Level

module accum (c, clr, d, q);
input c,clr;
input [3:0] d;
output [3:0] q;
reg [3:0] tmp;
always @(posedge c or posedge clr)
begin
if (clr)
tmp = 4'b0000;
else
tmp = tmp + d;
end
assign q= tmp;
endmodule
RESULT:
The Combinational and Sequential circuits were designed and Verilog HDL codes were
written and verified. The verilog codes are Synthesized and Post Place and Route was done.
Also the outputs were verified using the Spartan3E FPGA hardware kit.
Page 29
Expt No:
Date:
SCHEMATIC ENTRY AND SPICE SIMULATION OF
MOS DIFFERENTIAL AMPLIFIER
AIM:
To design and simulate the MOS differential amplifier and determine the bandwidth,
output impedance and CMRR cadence tool.
APPARATUS REQUIRED:
1. Personal Computer with Linux Operating System
2. Cadence tool
PROCEDURES:
Schematic Entry:
Creating a new library:
1. In the library manager, execute File - New library. The new library form appears.
2. In the new library form, type my design lib in the name section.
3. In the field of directory section, verify that the path to the library is set to ~/Database /
Cadence- analog lab bl3 and click ok.
4. In the next technology file for new library form select option attach to an existing
tech file and click ok.
5. In the attach design library to technology file form, select gpdk180 form the cyclic
field and click ok.
6. After creating a new library you can verify it from the library manager.
7. If you right click on the my design lib and select properties, you wil find that
gpdk180 library is attached as techlib to my design lib.
Creating a schematic cell view:
1. In the CIW or library manager, execute file new cell view.
2. Setup the new file form as follows, Do not edit the library path file and the above
might be different from the path shown in your form.
3. Click ok when done the above setting. A black schematic window for the inverter
design appears.
Adding components to schematic:
1. In the inverter schematic window, click the instance fixed menu icon to display the
add instance form.
2. Click on the browse button. This opens up a library browser from which you can
select components and the symbol view.
3. After you complete the add instance form move your cursor to the schematic window
and click left to place a component.
4. This is a table of components for building the inverter schematic.
Page 30
5. After entering components, click cancel in the add instance form or press ESC with
your cursor in the schematic window.
LIBRARY NAME
CELL NAME
gpdk180
PMOS
gpdk180
NMOS
PROPERTIES/COMMENTS
For M0 : model name PMOS1,
W = wp, L =180n
For M1 : model name NMOS1,
W = 2u, L =180n
Adding pins to schematic:

1. Click the pin fixed menu icon in the schematic window. You can execute create pin or
press p.
2. Add pin form appears. Type the following in the ADD pin form in the next order
leaving space between the pin.
PIN NAMES
DIRECTION
Vin
Input
Vout
output
3. Select cancel and then the schematic window enter window file or press the f bind
key.
Adding wires to schematic:
1. Click the wire (narrow) icon in the schematic window.
2. In the schematic window click on a pin of one of your components as the first point
for your wiring. A diamond shape appears over the starting point of this wire.
3. Follow the prompts at the bottom of design window and click left on the destination
point for your wire. A wire is routed between the source and destination points.
4. Complete the wiring as shown in the figure and when done wiring press ECS key in
the schematic window to cancel wiring.
Saving the design:
Click the check and save icon in the schematic editor window observe CIW output for
any errors.
Building the inverter test design:
Creating the inverter test cell view:
2. Setup the newfile as shown below.
3. Click ok when done. A blank schematic window for the inverter test design appears.
Page 31
4. Using the components list and properties/ comments in this table build the inverter
test schematic.
5. Add the above components using create instance or by pressing I.
6. Click the wire (narrow) icon and wire your schematic.
7. Click create wirename or press c to name the i/p (vin) and output wires as in below
schematic.
8. Click on the check and save icon to save the design.
Analog simulation with spectra:

Starting the simulation environment:
1. In the inverter-test schematic window execute launch ADEL. The variable virtuoso
analog design environment (ADE) simulation window appears.
Choosing a simulator:
1. In the simulation window (ADE) execute setup simulator / directory / host.
2. In the choosing simulator form, set the simulator field to specra and click ok.
3. In the simulation window (ADE) execute the setup model libraries.
To complete, move the cursor and click ok.
Choosing Analysis:
1. Click the choose- Analysis icon in the simulation window (ADE).
2. The choosing analysis form appears.
3. To Setup the transient analysis.
a. In the analysis section select tron.
b. Set the stoptime as 200ns
c. Click at the moderate or enabled button and the bottom and then click apply.
4. To set for DC analysis
a. In the analysis section select DC.
b. Turn on save DC operating point.
c. Turn on the component parameters.
d. Double click the select Vpulse source.
e. Select the DC voltage in the select window parameter and click in the form start
and stop voltages are 0 to 1.8.
f. Select the enable button and click apply and then click ok.
Setting deign variables:
1. Click on the edit variable icon and its corresponding form appears.
2. Click copy from at the bottom of the form. The design is scanned. All variables
formed in the design are listed.In the few moments the wp variable name wp and
enter.
Value (ixpr) 2u
3. Click change and notice the update and then click ok or cancel (in the editing design
variable window)
Page 32
Selecting o/ps for plotting:
1. Execute the o/ps to be plotted -select on sschematic in the simulation window.
2. Follow the prompt at the bottom. Click on the o/p net vout input vin of the inverter.
Press esc with the cursor after selecting.
Running the simulation:
1. Execute the simulation Netlist and run in the simulation window to start the
simulation on the icon. This will create the netlist as well as run the simulation.
2. When the simulation finishes the transient DC plots automatically with the log file.
V3
+15v
R1
10k
R2
10k
R4
100k
Q1
BC548A
BC548A
Q2
V1
VOFF = 0v
VAMPL = 50mv
FREQ = 4k
0
R3
8k
V2
-15
RESULT:
The Differential Amplifier Schematic and symbol was created and DC and Transient analysis
were done.
Page 33
Expt No:
Date:
CMOS INVERTER LAYOUT DESIGN
AIM:
To design and simulate the CMOS inverter and observe the DC and transient
responses and to create the layout of CMOS inverter and extract the parasitic values using
cadence tool.
APPARATUS REQUIRED:
2. Cadence tool
PROCEDURES:
Schematic Entry:
Creating a new library:
1. In the library manager, execute File - New library. The new library form appears.
2. In the new library form, type my design lib in the name section.
3. In the field of directory section, verify that the path to the library is set to ~/Database /
Cadence- analog lab bl3 and click ok.
4. In the next technology file for new library form select option attach to an existing
tech file and click ok.
5. In the attach design library to technology file form, select gpdk180 form the cyclic
field and click ok.
6. After creating a new library you can verify it from the library manager.
7. If you right click on the my design lib and select properties, you wil find that
gpdk180 library is attached as techlib to my design lib.
Creating a schematic cell view:
9. Setup the new file form as follows, Do not edit the library path file and the above
might be different from the path shown in your form.
10. Click ok when done the above setting. A black schematic window for the inverter
design appears.
Adding components to schematic:
11. In the inverter schematic window, click the instance fixed menu icon to display the
add instance form.
12. Click on the browse button. This opens up a library browser from which you can
select components and the symbol view.
13. After you complete the add instance form move your cursor to the schematic window
and click left to place a component.
14. This is a table of components for building the inverter schematic.
Page 34
15. After entering components, click cancel in the add instance form or press ESC with
your cursor in the schematic window.
LIBRARY NAME
CELL NAME
gpdk180
PMOS
gpdk180
NMOS
PROPERTIES/COMMENTS
For M0 : model name PMOS1,
W = wp, L =180n
For M1 : model name NMOS1,
W = 2u, L =180n
Adding pins to schematic:

16. Click the pin fixed menu icon in the schematic window. You can execute create pin or
press p.
17. Add pin form appears. Type the following in the ADD pin form in the next order
leaving space between the pin.
PIN NAMES
DIRECTION
Vin
Input
Vout
output
18. Select cancel and then the schematic window enter window file or press the f bind
key.
Adding wires to schematic:
19. Click the wire (narrow) icon in the schematic window.
20. In the schematic window click on a pin of one of your components as the first point
for your wiring. A diamond shape appears over the starting point of this wire.
21. Follow the prompts at the bottom of design window and click left on the destination
point for your wire. A wire is routed between the source and destination points.
22. Complete the wiring as shown in the figure and when done wiring press ECS key in
the schematic window to cancel wiring.
Saving the design:
Click the check and save icon in the schematic editor window observe CIW output for
any errors.
Building the inverter test design:
Creating the inverter test cell view:
24. Setup the newfile as shown below.
25. Click ok when done. A blank schematic window for the inverter test design appears.
Page 35
26. Using the components list and properties/ comments in this table build the inverter
test schematic.
LIBRARY NAME
CELL VIEW NAME
PROPERTIES/COMMENTS
My design lib
Inverter
Symbol
Analog lib
Vpulse
V1 = 0, v2 = 1, td = 0,
tr=tf=1ns, ton = 10ns, T=
20ns
Analog lib
Vdc, gnd
Vdc = 1.8v
27. Add the above components using create instance or by pressing I.

28. Click the wire (narrow) icon and wire your schematic.
29. Click create wirename or press c to name the i/p (vin) and output wires as in below
schematic.
30. Click on the check and save icon to save the design.
Analog simulation with spectra:

Starting the simulation environment:
31. In the inverter-test schematic window execute launch ADEL. The variable virtuoso
analog design environment (ADE) simulation window appears.
Choosing a simulator:
32. In the simulation window (ADE) execute setup simulator / directory / host.
33. In the choosing simulator form, set the simulator field to specra and click ok.
34. In the simulation window (ADE) execute the setup model libraries.
To complete, move the cursor and click ok.
Choosing Analysis:
35. Click the choose- Analysis icon in the simulation window (ADE).
36. The choosing analysis form appears.
37. To Setup the transient analysis.
d. In the analysis section select tron.
e. Set the stoptime as 200ns
f. Click at the moderate or enabled button and the bottom and then click apply.
38. To set for DC analysis
g. In the analysis section select DC.
h. Turn on save DC operating point.
i. Turn on the component parameters.
j. Double click the select Vpulse source.
k. Select the DC voltage in the select window parameter and click in the form start
and stop voltages are 0 to 1.8.
l. Select the enable button and click apply and then click ok.
Page 36
Setting deign variables:
39. Click on the edit variable icon and its corresponding form appears.
40. Click copy from at the bottom of the form. The design is scanned. All variables
formed in the design are listed.In the few moments the wp variable name wp and
enter.
Value (ixpr) 2u
41. Click change and notice the update and then click ok or cancel (in the editing design
variable window)
Selecting o/ps for plotting:
42. Execute the o/ps to be plotted -select on sschematic in the simulation window.
43. Follow the prompt at the bottom. Click on the o/p net vout input vin of the inverter.
Press esc with the cursor after selecting.
Running the simulation:
44. Execute the simulation Netlist and run in the simulation window to start the
simulation on the icon. This will create the netlist as well as run the simulation.
45. When the simulation finishes the transient DC plots automatically with the log file.
Creating layout view of inverter:

46. From the inverter schematic window menu execute Launch lyout XL. A startup
option form appears.
47. Select create new option. This gives a new cell view form.
48. Check the cell name (inverter). Viewname (Layout).
49. Click ok from the newcell view form. LSW and a black layout window appears along
with schematic window.
Adding components to layout:
50. Execute connecting Generate All from source or click the icon in the layout editor
window. Generate the layout form appears. Click ok which imports the schematic
components into the layout window automatically.
51. Rearrange the components with in PR Boundary as shown.
52. To rotate a component select the component and execute Edit Properties. Now
select the degree of rotation from the property edit form.
53. Move a component, select the component and execute edit Move command.
Making connection:
54. Execute connectivity Nets show/hide selected incomplete Nets or click the icon in
the layout menu.
55. Move the mouse pointer over the device and click LMB to get the connectivity
information which shows the guide lines for the interconnections of the components.
Page 37
56. From the layout window, execute create shape path / create wire or create shape
rectangle and select the appropriate layers from the LSW window and vias for
making the interconnections.
Creating contacts/vias:
Execute create-via to place different contacts.
Connection
For metal 1 Polyconnection
For metal 1 psubstrate connection
For metal 1 nwell connection
Contact Type
Metal 1 Poly
Metal 1 psub
Metal 1 - nwell
Saving the design:

Save your design by selecting file save to save the layout and layout appears.
Running a DRC:
57. Open the inverter layout form the CIW or library manager if you have closed that.
Press shift f in the layout to display all the levels.
58. Select Assura Run DRC from layout window. The DRC form appears. The library
and cellname are taken from the current design window, but rule file maybe missing.
59. Seelect the technology as gpdk180. This automatically loads the rule file.
60. Click ok to start DRC.
61. A progress form will appear. You can click on the watch log file to see the log file.
62. When DRC finishes a dialog box asking you if you want to view your DRC results,
and click yes to view results of the run.
63. If there any DRC results in the design view layer window (VLW) and error layer
window (ELW) appears. Also the errors highlight in the design itself.
64. Click view summary in the ELW to find the details of error.
65. You can refer to the run file for info, correct all the DRC error and the Re-run the
DRC.
66. If there are no errors in the layout then a dialog bo appears with no DRC errors found
written in it, click on close to terminate the DRC run.
Running LVS:
67. Select Assura Run LVS from the layout window. The Assura Run LVS form
appears. It will automatically load both the schematic and layout view of the cell and
click ok.
68. The LVS begins and a progress form appears.
69. If the schematic and layout matches completely, you will get form displaying
schematic and layout match.
70. If the schematic and layout do not matches, a form informs that the LVS completed
successfully and asks if you want to see the results of this sum.
71. Click yes in the form.
72. In the LVS dialog box you can find the details of mismatches and you need to correct
all those mismatches and Re-Run the LVS.
Page 38
73. In the filtering tab of the form enter power nets as vdd! , vss! And enter ground nets
as gnd!
74. Click ok in the assura parasitic extraction form when done. The RCX progress form
appears, in the progress form click watch log file to see the output log file.
75. When RCX completes, a dialog box appears, informs you that Assura RCX run
completed successfully.
76. You can open the av-extracted view from the library manager and view the parasitic.
RESULT:
The CMOS inverter Schematic and symbol was created and DC and Transient analysis were
done. Manual layout was drawn and parasitic extraction was done.
Page 39
Expt No:
Date:
DESIGN AND AUTOMATIC LAYOUT GENEARTION FOR COUNTER

AIM:
To design, simulate and synthesize the counter circuit and generate the automatic
layout and simulate through post layout extraction using Cadence tool.
APPARATUS REQUIRED:
2. Cadence tool
PROCEDURES:
1. Write a verilog program (filename.v) for counter circuit and save it and close.
2. Simulate through the ncsim command and give the inputs and check the output
through the simvision window.
3. Synthesize and elaborate the verilog program.
4. Create a constraint file (filename.g) and read the file.
5. Synthesize the circuit and note down the power, timing parameters.
6. Create a net file (filename_net.v) and the hdl net file.
7. Open the encounter tool for automatic layout genearation.
8. Import the filename_net.v and select the *.lef file.
9. Create the power and ground nets.
10. Create the *.view file
11. Specify the floorplan structure and define the core utilization area.
12. Create power rings and nets (VDD and VSS) and select the ring configuration for
metal layers.
13. Create the power stripes and specify the number of sets to be used.
14. Route the design and Place the standard cells.
15. Do the Pre-CTS, clock synthesize, post-CTS and extract RC operations.
16. Create the *.gds file.
Page 40
PROGRAM:
Up Counter Design using Behavioral Modelling
module counter_up_down(out,clk,reset,control);
output [3:0]out;
input clk, reset,control;
reg [3:0] out;
if(reset)
out <=4'b0000;
else
out<=out+1;
endmodule
RESULT:
The counter circuit was designed, simulated and synthesized and generated the
automatic layout and simulate through post layout extraction using Cadence tool.
Page 41
Expt No:
Date:
DESIGN AND AUTOMATIC LAYOUT GENEARTION FOR 10 BIT NUMBER

CONTROLLED OSCILLATOR
AIM:
To design, simulate and synthesize the 10 bit Number Controlled Oscillator circuit
and generate the automatic layout and simulate through post layout extraction using Cadence
tool.
APPARATUS REQUIRED:
2. Cadence tool
PROCEDURES:
PROCEDURES:
1. Write a verilog program (filename.v) for counter circuit and save it and close.
2. Simulate through the ncsim command and give the inputs and check the output
through the simvision window.
3. Synthesize and elaborate the verilog program.
4. Create a constraint file (filename.g) and read the file.
5. Synthesize the circuit and note down the power, timing parameters.
6. Create a net file (filename_net.v) and the hdl net file.
7. Open the encounter tool for automatic layout genearation.
8. Import the filename_net.v and select the *.lef file.
9. Create the power and ground nets.
10. Create the *.view file
11. Specify the floorplan structure and define the core utilization area.
12. Create power rings and nets (VDD and VSS) and select the ring configuration for
metal layers.
13. Create the power stripes and specify the number of sets to be used.
14. Route the design and Place the standard cells.
15. Do the Pre-CTS, clock synthesize, post-CTS and extract RC operations.
16. Create the *.gds file.
Page 42
PROGRAMS:
Phase Incrementer:
ìfndef width
`define data_width 6
`define addr_width 6
`define width
èndif
module phase_inc(fclk,M,rst,addr_out);
parameter addr_width = 6;
input fclk,rst;
input [addr_width-1:0]M;
output reg [addr_width-1:0]addr_out;
reg [addr_width-1:0]count;
reg [addr_width-1:0]count_reg;
always@(M) count_reg = M;
always@(posedge fclk) begin
if(rst) addr_out = 0;
else begin
if (count!=0) count = count - 1'b1;
else begin
addr_out = addr_out + 1;
count = count_reg;
end
end
end
endmodule
Multiplexer:
module mux_2to1(addr_in,addr_load,load,addr_out);
input [addr_width-1:0]addr_in;
input [addr_width-1:0]addr_load;
input load;
output [addr_width-1:0]addr_out;
assign addr_out = load?addr_load:addr_in;
endmodule
Page 43
Memory:
ìfndef width
`define width
èndif
module mem(clk,rw,addr,data_in,data_out);
parameter data_width = 6;
input clk,rw;
input [addr_width-1:0]addr;
input [data_width-1:0]data_in;
output reg [data_width-1:0]data_out;
reg [data_width-1:0]memory[0:(2**addr_width-1)];
always@(posedge clk) begin
if (!rw) begin
memory[addr] = data_in;
data_out = `data_width'bZ;
end
else if (rw) begin
data_out = memory[addr];
end
end
endmodule
Top Module:
ìfndef width
`define width
èndif
module top(clk,M,rst,rw,data_in,load,addr_load,data_out);
parameter data_width = 6;
input clk,rst,rw,load;
input [addr_width-1:0]M;
input [data_width-1:0]data_in;
input [addr_width-1:0]addr_load;
output [data_width-1:0]data_out;
wire [addr_width-1:0]addr_ph;
wire [addr_width-1:0]addr_out;
phase_inc PHASE_INC(.fclk(clk),.M(M),.rst(rst),.addr_out(addr_ph));
mux_2to1 MUX(.addr_in(addr_ph),.addr_load(addr_load),.load(load),.addr_out(addr_out));
mem RAM(.clk(clk),.rw(rw),.addr(addr_out),.data_in(data_in),.data_out(data_out));
endmodule
Page 44
TESTBENCH:
ìfndef width
`define width
èndif
module testbench;
parameter data_width = 6; parameter addr_width = 6;
reg clk,rst,rw,load; reg [addr_width-1:0]M;
reg [addr_width-1:0]addr_load; reg signed [data_width-1:0]data_in;
wire signed [data_width-1:0]data_out;
integer fh,i,r;
initial begin
clk = 0;
rst = 1;
data_in = 0;
M = àddr_width'b0;
addr_load = àddr_width'h3f;
fh = $fopen("sine_values.txt","r");
#10 rst = 0;
#1000000 $stop;
end
always #1 clk = ~clk;
// Writing into memory
initial begin
load = 1;
for (i = 0; i <= (2**addr_width); i = i+1) begin
r = $fscanf(fh,"%d",data_in);
addr_load = addr_load + 1;
rw = 0;
@(posedge clk);
end
load = 0;
rw = 1;
end
initial begin
forever #100000 M = M+2;
end
top
TOP(.clk(clk),.M(M),.rst(rst),.rw(rw),.data_in(data_in),.load(load),.addr_load(addr_load),.data_out(da
ta_out));
endmodule
RESULT:
The 10 bit Number Controlled Oscillator circuit was designed, simulated and
synthesized and generated the automatic layout and simulated through post layout extraction
using Cadence tool.

Ec2357 - Vlsi Design Laboratory

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VLSI DESIGN LABORATORY

EC2357 VLSI Design Laboratory

The structure of a module is the following:

~(not), &(and), |(or) and ^(xor)

Fig. Flow chart of VLSI design flow

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Adding pins to schematic:

Analog simulation with spectra:

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CELL VIEW NAME

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Analog simulation with spectra:

Creating layout view of inverter:

Saving the design:

DESIGN AND AUTOMATIC LAYOUT GENEARTION FOR COUNTER

DESIGN AND AUTOMATIC LAYOUT GENEARTION FOR 10 BIT NUMBER

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