brick shaping

raw materials

Moores Law in Microprocessors

Transistors on lead microprocessors double every 2 years

Evolution in DRAM Chip Capacity

human memory
human DNA

4X growth every 3 years!

0.07 m

100000000

64,000,000

0.1 m

16,000,000

Kbit capacity/chip

10000000

0.13 m

4,000,000

book

1000000

0.18-0.25 m

1,000,000
256,000 0.35-0.4 m

100000

0.5-0.6 m
64,000

encyclopedia
2 hrs CD audio
30 sec HDTV

16,000
0.7-0.8 m

10000

4,000
1.0-1.2
m
1,000

1000

1.6-2.4 m

256
100
64
10
1980

1983

page

1986

1989

1992

1995

Year

1998

2001

2004

2007

2010

Die Size Growth

Die size grows by 14% to satisfy Moores Law

Die size (mm)

100

P6
486 Pentium proc

10

386
8080
8008
4004

8086
8085

286

~7% growth per year

~2X growth in 10 years

1
1970

1980

1990
Year
Courtesy, Intel

2000

2010

Clock Frequency
Lead microprocessors frequency doubles every 2 years
10000

2X every 2 years

Frequency (Mhz)

1000

P6
Pentium proc

100
486
10

8085

1
0.1
1970

8086 286

386

8080
8008
4004
1980

1990
Year
Courtesy, Intel

2000

2010

Power Dissipation
Lead Microprocessors power continues to increase

Power (Watts)

100
P6
Pentium proc
10
8086 286
1

8008
4004

486
386

8085
8080

0.1
1971

1974

1978

1985

1992

2000

Year

Power delivery and dissipation will be prohibitive

Courtesy, Intel

Power Density
Power Density (W/cm2)

10000

Rocket
Nozzle

1000

Nuclear
Reactor

100

8086
Hot Plate
10 4004
P6
8008 8085
Pentium proc
386
286
486
8080
1
1970

1980

1990
Year

2000

2010

Power density too high to keep junctions at low temp

Courtesy, Intel

Design Productivity Trends

100,000

Logic Tr./Chip

10,000

Tr./Staff Month.
1,000

100
58%/Yr. compounded
Complexity growth rate

10

100

10
x

0.1

xx
x x

0.01

21%/Yr. compound
Productivity growth rate

0.1
0.01

Complexity outpaces design productivity

Courtesy, ITRS Roadmap

2009

2007

2005

2003

2001

1999

1997

1995

1993

1991

1989

1987

1985

1983

0.001

Productivity
(K) Trans./Staff - Mo.

1,000

1981

Logic Transistor per Chip (M)

Complexity

10,000

How far can light travel in 1 clock

signal?

Major Design Challenges

Microscopic issues

Macroscopic issues

ultra-high speeds
power dissipation and
supply rail drop
growing importance of
interconnect
noise, crosstalk
reliability, manufacturability
clock distribution

Year

Tech.

Complexity

1997
1998
1999
2002

0.35
0.25
0.18
0.13

13 M Tr.
20 M Tr.
32 M Tr.
130 M Tr.

time-to-market
design complexity
(millions of gates)
high levels of abstractions
reuse and IP, portability
systems on a chip (SoC)
tool interoperability

Frequency 3 Yr. Design

Staff Size
400 MHz
210
500 MHz
270
600 MHz
360
800 MHz
800

Staff Costs
$90 M
$120 M
$160 M
$360 M