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B.Lojek
Fall 2014
Many todays business leaders are driven by Wall Street but do not
really understand the business they represent. They enjoy spending
others money. They claim that all is the question of Money
Resources People. They have never realized that they have the
priority wrong. All is a question of People Resources Money.
Strong and creative individuality is priceless.
MOS technology has undergone unprecedented evolution. For the past fifty years, MOS transistor scaling
has provided ever-increasing transistor performance and density. Interestingly enough, many people
predicted in each generation the end of scaling within one or two generation. However, each time the
technology reached the predicted barriers, scaling did not stop. There is no limit to engineering ingenuity;
however, there could be an economic limit when the cost of the scaled device would not be balanced by
benefits.
W. Shockley, A unipolar field-effect transistor. Proc. IRE, vol. 40 (1952), pp. 1365-1376
ECE3020SemiconductorDevices
B.Lojek
Fall 2014
Experimental measurements have confirmed the general predictions made for these structures and have,
in addition provided some specific information about surface states of the semiconductors. However, no
fully functional device was available until 1959 when M. M. Atalla reported that thermally grown silicon
dioxide has the property of passivating the surface and greatly decreases the density of deep surface traps.
ECE3020SemiconductorDevices
B.Lojek
Fall 2014
L ~ 20 m
tox ~1000
xj ~ 3 m
VDD = 12 -20 V
Main problem: oxide quality
L ~ 15 m
tox ~800-1000
xj ~ 3 m
VDD = 12 -15 V
(1974)
Constant Field Scaling
R. H. Dennard, F. H. Geansslen, H.-N. Yu, V.L. Rideout, E. Bassous, A.R. LeBlanc, Design of IonImplanted MOSFETs with Very Small Physical Dimension, IEEE J. Solid-State Circuits, SC-9 (5), p.
256 (1974)
ECE3020SemiconductorDevices
B.Lojek
Fall 2014
Circa 1975 : NMOS with self-aligned Polysilicon Gate (HMOS High Performance MOS)
L ~ 5 m
tox ~400-800
xj ~ 1.5 m
VDD = 5 - 10 V
The structure took full advantage of ion-implantation by use of (a) threshold adjust implant, (b) punchthrough
implant, (c) source/drain implant.
Introduction to VLSI Systems, published in late fall, 1979. Within a few years, this seminal text was adopted
for chip design courses at over 100 universities throughout the world.
ECE3020SemiconductorDevices
B.Lojek
Fall 2014
Citation from the induction of Mead and Conway into the Electronic Design Hall of Fame, in 2002.
By the mid-1970s, digital system designers eager to create higher-performance devices were frustrated by
having to use off-the-shelf large-scale-integration logic. It stymied their efforts to make chips sufficiently
compact or cost-effective to turn their very large-scale visions into timely realities. In 1979, a landmark
book titled Introduction to VLSI Systems changed all of that. Co-authored by Mead, the Gordon and Betty
E. Moore professor of computer science and electrical engineering at the California Institute of
Technology, and Conway, research fellow and manager of the VLSI system design area at the Xerox Palo
Alto Research Center, the book provided the structure for a new integrated system design culture that made
VLSI design both feasible and practical. Introduction to VLSI Systems resulted from work done by Mead
and Conway while they were part of the Silicon Structures Project, a cooperative effort between Xerox and
Caltech. Mead was known for his ideas on simplified custom-circuit design, which most semiconductor
manufacturers viewed with great skepticism but were finding increasing support from computer and
systems firms interested in affordable, high-performance devices tailored to their needs. Conway had
established herself at IBMs research headquarters as an innovator in the design of architectures for
ultrahigh-performance computers. She invented scalable VLSI design rules for silicon that triggered Mead
and Conways success in simplifying the interface between the design and fabrication of complex chips.
The structured VLSI design methodology that they presented, the Mead-Conway concept, helped bring
about a fundamental reassessment of how to put ICs together.
ECE3020SemiconductorDevices
B.Lojek
Fall 2014
Circa 1985 : CMOS with N+ Polysilicon Gate, LOCOS isolation, TiSi Silicide,
and LDD implant
L ~ 0.75 - 1.0m
tox ~200
xj ~ 0.2-0.4 m
VDD = 5 V
Circa 1990 : CMOS with N+/P+ Polysilicon Gate, LOCOS isolation, and selfaligned TiSi Silicide
L ~ 0.35 - 0.5 m
tox ~120
xj ~ 0.15 m
VDD = 3.3 - 5 V
ECE3020SemiconductorDevices
B.Lojek
Fall 2014
Circa 1995 : CMOS with STI isolation, and P+ pocket (halo) implants
L ~ 0.15 m
tox ~60
xj ~ 0.08 m
VDD = 5 V
Circa late 1990s : CMOS with STI isolation, and retrograde channel doping
L ~ 90 nm
tox < 30
xj ~ 0.06 m
VDD = 1.8 V
ECE3020SemiconductorDevices
B.Lojek
Fall 2014
FinFET device has been proposed to resolve the short channel effects (SCE). While FinFET provides a
significant resolution of drain-induced barrier lowering and SCE, it has its own challenges:
1) How to maintain high mobility enhancement from the stressor;
ECE3020SemiconductorDevices
B.Lojek
Fall 2014
(1.1)
(1.2)
Where is a constant, f is operating frequency, CL is the load capacitance, I 0 drain current for
VDD = VT , N surf is the surface carrier concentration in the channel, S is the S factor, I leak is the total
ECE3020SemiconductorDevices
B.Lojek
Fall 2014
leakage current including the gate and junctions leakages, CG is the gate capacitance, and is the
velocity.
In order to realize low power MOS device, lower VDD , higher VT , smaller S (higher immunity to shortchannel effects), and lower I leak are necessary. However, these requirements clearly conflict with those of
higher I on and are also inconsistent between themselves. According to (1.2), lower VDD and higher VT
lead to significant reduction of I on . In addition, thick gate oxide tox , which is needed for reduction the
direct tunneling current, decreases I on and increases S because of lower CG . An increase in substrate
concentration , N surf , is necessary to suppress short-channel effects and reduce S , but causes an increase
in I leak due to junction tunneling current and gate induced drain leakage current.
As a consequence, new device architecture is needed to overcome these difficulties. The introduction of
channels with high carrier mobility and velocity was suggested as a solution of the scaling problem of
conventional planar devices. This is because the higher carrier mobility channel can provide not only
higher I on due to higher but also can reduce VDD or increase tox (i.e. lower CG ) under a constant value
of I on and thereby reduce the active or the standby power.
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ECE3020SemiconductorDevices
B.Lojek
Fall 2014
Fig. 1.7. Concept of channel formation by selective growth of III-V materials on Si substrates.
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ECE3020SemiconductorDevices
B.Lojek
Fall 2014
n [cm2/Vsec]
me/m0
p [cm2/Vsec]
mh/m0
Eg [eV]
Si
Ge
GaAs
InP
InAs
InSb
1600
0.19 / 0.916
430
0.49 / 016
1.12
3900
0.82 / 1.467
1900
0.28 / 0.044
0.66
9200
0.067
400
0.45 / 0.082
1.42
5400
0.082
200
0.45 / 012
1.34
40000
0.023
500
0.57 / 0.35
0.36
77000
0.014
850
0.44 / 0.016
0.17
Table. 1.1. Mobility, effective mass and band-gap of electrons and holes in principal semiconductors.
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