Академический Документы
Профессиональный Документы
Культура Документы
Version 3.1 - PC
Copyright
ii
Limited Warranty
Lattice Semiconductor Corporation warrants the original purchaser that the Lattice
Semiconductor software shall be free from defects in material and workmanship for a
period of ninety days from the date of purchase. If a defect covered by this limited
warranty occurs during this 90-day warranty period, Lattice Semiconductor will
repair or replace the component part at its option free of charge.
This limited warranty does not apply if the defects have been caused by negligence,
accident, unreasonable or unintended use, modification, or any causes not related to
defective materials or workmanship.
To receive service during the 90-day warranty period, contact Lattice Semiconductor
Corporation at:
Phone: 1-800-LATTICE or (408) 826-6002
E-mail: techsupport@latticesemi.com
If the Lattice Semiconductor support personnel are unable to solve your problem over
the phone, we will provide you with instructions on returning your defective software
to us. The cost of returning the software to the Lattice Semiconductor Service Center
shall be paid by the purchaser.
Limitations on Warranty
iii
iv
Contents
vi
This section describes the ispLEVER software support for Lattice CPLD,
ispXPLD, ispXPGA, and ORCA FPGA devices. The following topics are discussed
in this section:
Floorplanner Enhancements
EPIC Enhancements
ispXPLD: LC51024MX
Preliminary Support
This release adds or updates preliminary support for the following devices:
ispXPLD: LC5768MX
ispMACH4000: LC4256ZC
The ispLEVER software does not generate a JEDEC file and the JEDEC File process
is not available for LC4256ZC devices. Silicon timing delay models for devices with
Preliminary Support are based on estimated data, and subject to change.
The licensing scheme has been changed from locking to the users hard disk ID to
locking to the users network interface card (NIC) address.
ispLSI 5000VE
ispMACH 5000VG
ispMACH 5000B
ispXPLD 5000MX
ispMACH 4000
ispGDX2
Copy Revision. You can copy a particular revision by right-clicking a revision and
choosing Copy Revision. A copy of the selected revision and all its sub-level revisions
will be created.
Rename Revision. The revision names can be customized in this release. You can
change a revision name by selecting the name, clicking it again, and then typing in a
new name.
Revision Comment. Comments can be added to any revision to better identify
different design versions. Right-click a revision and choose Property to add a
comment. The comment will then appear in a pop-up text box when you move your
mouse over the revision name (Figure 1).
Project Archiving
File > Archive Current Project and File > Open Archived Project are two new
commands in the Project Navigator. You can use them to save your project to a .zip
archive, and reload it as necessary.
Console for Running the ispLEVER software from the Command Line
Window > ispLEVER Console is a new command in the Project Navigator. You can
use this command to open a command line prompt window if you want to run the
ispLEVER software from the command line.
In the 3.0
Release
In the 3.1
Release
None (default)
Auto (default)
Bypass
Bypass
None
10
Wrap_all No clock enable is used. The software folds clock enable into
register data equation.
Keep_all If the number of clock enable product terms is greater than the
maximum clock enable PT limit of the target device, the software will insert
clock enable nodes, otherwise it just keeps the clock enable equation.
Auto If the number of clock enable product terms is greater than the
maximum clock enable PT limit of the target device, the software will wrap
the clock enable equation into register data equation to avoid a timing delay
issue, otherwise it just keeps the clock enable equation.
11
CAM
FIFO_DC
FIFO_DCX
RAM_DP
RAM_DP_TRUE
RAM_DQ
ROM
12
Added Totals field at the bottom of the GLB Resource Summary section
Added a column for Fan In per macrocell in the GLB Cluster sections
Added a single line indicating the number of signals per GLB in the GLB
Logic Array Fanin sections
Added a column to the GLB Logic Array Fanin sections that indicates the
fanout load inside the GLB for each signal
13
Floorplanner Enhancements
A separate Floorplanner interface has been added for ORCA FPGA devices. The
ORCA Floorplanner displays a completely separate window for the Package, PreMapped, Post-Mapped, and Floorplan views.
The appropriate view opens automatically from the Project Navigator when you run
one of the following processes:
Pre-Map Logical Design Floorplan. This process opens only the Pre-Mapped View,
allowing you to create logical groups (Ugroups) before mapping the design. The
changes that you save are applied to the logical design file (.ngd).
Post-Map Physical Design Floorplan. This process opens all four Floorplanner
windows. Any Ugroups that you created in the Pre-Mapped Floorplan are converted to
physical groups (Pgroups). You can create other Pgroups, make pin assignments, and
specify regions before placing and routing the design.
Post-PAR Design Floorplan. This process opens all four windows for the placed and
routed design. You can make further adjustments to the design and rerun the Place and
Route process.
14
EPIC Enhancements
Enhancements for EPIC (Editor for Programmable ICs) include:
Menu reorganization.
Locator area features new boundaries for active area and cross-hair zoom-in
feature.
New EPIC Start dialog box has been added. The EPIC Start dialog box appears
after you start the EPIC program independently or when you launch EPIC
initially from within Project Navigator.
15
New Slack column that displays difference between real and required delay
New Path Tracing Options and point selection dialog functionality for tP2P
timing delay type.
New Preferences > Save GUI Settings command that allows you to maintain
preferred dialog box sizes and fonts.
16
17
Comprehensive Glossary
The Online Help now features a comprehensive glossary of terms commonly used
with the ispLEVER software. You can view the Glossary by selecting it from the
Project Navigator Help menu or by clicking Glossary in the Toolbar.
18
Use the Project Navigator Help menu to access documents for other applications
through the ispLEVER Documentation Library.
ORCA Documentation
ORCA Libraries Manual (ORCA2, 3, 4, and above) and ORCA Attributes for
Design Entry Design Reference are available under User Guides in the
ispLEVER Documentation Library.
A new users guide has been supplied for EPIC Device Editor documentation.
19
-p exo
-t 256
orca.bit
-p exo
-t 256
-u 0 orca.bit
PUR
20
Workaround:
First, let the design run through the software flow without any pin locking.
This allows the fitter to choose compatible placement for the functions (you
should allow the fitter to run without any pin locking constraints until you
absolutely have to lock down the pinout). Second, backannotate the pin
assignments (the location assignments of the memory and arithmetic will be
automatically written into the constraints file) as you continue to make changes
to your design. This gives the fitter a known compatible placement of these
functions.
Devices Affected:
ispXPLD 5000 MX
Issue:
Workaround:
Devices Affected:
CPLD
Issue:
Workaround:
Device Affected:
21
Issue:
When you try to save changes to the projects constraint file (.lct) using the
Constraint Editor, a message instructs you to close the other application that
has the LCT file open. This message appears after youve attempted to import
the <project_name>.lct file.
Workaround:
Devices Affected:
All
Issue:
The following warning messages appear in the Constraint Editor output panel
after fitting a design, backannotating constraints, and then running the Post-Fit
Pinouts process in the Project Navigator.
C:\ispTOOLS31_starter\ispcpld\examples\ispXPLD\Veril
og\test_ramdq16kx2\test_ramdq16kx2.lco : <W0613> :
IO Types Setting Reset : bank setting 2 is
conflict with Pin locking.
C:\ispTOOLS31_starter\ispcpld\examples\ispXPLD\Veril
og\test_ramdq16kx2\test_ramdq16kx2.lco : <W0613> :
IO Types Setting Reset : bank setting 2 is
conflict with Pin locking.
Loading Lattice Constraint File
C:\ispTOOLS31_starter\ispcpld\examples\ispXPLD\Veri
log\test_ramdq16kx2\test_ramdq16kx2.lco done!
Workaround:
Device Affected:
All
Floorplanner
Issue:
The pins on the ASIC (non-FPGA core) side of an FPSC device are fixed, but
the Floorplanner allows them to be moved via drag and drop. The placer will
issue a warning and disregard the invalid assignment.
Workaround:
None needed.
Devices Affected:
FPSC
22
Issue:
If you right-click in the Package View in the Floorplanner, the pop-up menus
Package Property command displays the Package Property dialog box.
However, the Package Property dialog box does not give any information
about the properties of the selected device.
Workaround:
Devices Affected:
ispXPGA
Issue:
Some features on the right edges of Floorplan View in the Floorplanner may
not be visibible if you zoom in.
Workaround:
None.
Devices Affected:
ispXPGA
Installation
Issue:
EPIC can crash with a message saying the system is running low on virtual
memory.
Workaround:
Before running the EPIC software, increase the range of virtual memory on
your local computer to accommodate the EPIC software and any other
applications that you will be running simultaneously.
Devices Affected:
ORCA FPGA
Issue:
The Synplify software license agreement goes blank when the Synplify
software is started for the first time.
Workaround:
In the Synplicity software, choose Help > License Agreement to view the
license agreement.
Devices Affected:
All
23
Issue:
Workaround:
Dont click the Lattice Semiconductor Setup Program icon at the bottom of
the screen after you click the "Finished" button, and dont manually attempt to
stop the installation process. Allow the InstallShield program to completely
install the ispLEVER software. The icon at the bottom of the screen will
disappear by itself when the installation is complete.
Devices Affected:
All
Issue:
When installing ispLEVER software on a client server that has never had v3.x
(v3.0 or v3.1) ispLEVER software previously installed on it, the Product
Options dialog box will only have one checkbox choice named Starter.
Workaround.
Select the Starter checkbox option and click Next to continue with
installation.
Devices Affected:
All
ispLSI Macros
Issue:
OT14
OT18
OT21
OT24
OT28
OT31
OT34
OT38
OT41
OT44
OT48
Workaround:
Do not use the macro in such a design. Use the behavior description instead.
Devices Affected:
ispLSI 5000VE
24
ispVM Software
Issue:
You will receive an error message with Code 001 if you attempt to run the
ispVM software from the Project Navigator and the ispVM software is not
installed.
Workaround:
Ensure the ispVM software is installed before running ispVM software from
the Project Navigator.
Devices Affected:
All
ispXPGA
Issue:
When LVDS sysIO Type is configured for a clock signal, ispXPGA prevents
this setting from being placed on an I/O pin because of possible skew that will
degrade the LVDS signal. You can assign a normal clock to an I/O pin. Any
LVDS type clock signal needs to be assigned to a GCLK pin. This causes a
warning message from the ispXPGA placer. However, the warning incorrectly
specifies BLVDS type instead of LVDS type.
Incorrect Error Message:
<Error> F51104: Clock signal Clk0_nside$implicit_buf
with BLVDS sysIO type cannot be assigned to an I/O
pin.It must be assigned to a GCLKn pin.
<Error> F54031: Proper placement of sysCLOCK instance
failed.
Message should be:
<Error> F51104: Clock signal Clk0_nside$implicit_buf
with LVDS sysIO type cannot be assigned to an I/O
pin.It must be assigned to a GCLKn pin.
<Error> F54031: Proper placement of sysCLOCK instance
failed.
Workaround:
Devices Affected:
ispXPGA
25
Issue:
For Module FIFO_DC, the EDI/EDO feature will not work in functional RTL
Verilog simulation. VHDL simulation works.
Workaround:
None.
Device Affected:
ispXPGA
ispXPLD
Issue:
VHDL examples cause errors due to unknown LC5KMX library when RTL
synthesis is switched to Synplicity. The errors are caused by the LC5KMX
library which is primarily used for logic simulation.
Workaround:
Device Affected:
26
ispXPLD 5000MX
When using the Lattice Logic Simulator, you can get incorrect simulation
results for Functional Simulation of a D flip-flop and associated logic.
Discussion: The Lattice Logic Simulator will take the D signal value at the
time just prior to the clock edge and reflect that value after the transition of the
clock. In a functional simulation, the data and clock edges will most likely
occur at the same time. In order to catch possible race states in a functional
simulation, the D state just prior to a clock edge is considered in a stable state.
By sampling the data signal prior to the clock edge, the Lattice Logic
Simulator can emulate a setup time requirement similar to a timing simulation.
Workaround:
Adjust the test bench stimulus to transition the data prior to the clock edge or
run the timing simulation.
Device Affected:
CPLD
Issue:
When you simulate a sub-block of a design using the Lattice Logic Simulator,
the functional simulation process sometimes displays incorrect logic
information.
Workaround:
When the clock and data change at the same time for a register, you can
simulate using the previous value or future value of the D port. The Lattice
Logic Simulator uses the previous value known as the t- approach. You can
change the stimulus to prevent the conflict and show a correct value. Or you
can run timing simulation, and the timing simulation can show you the correct
value.
Devices Affected:
27
legacy2lci
Issue:
Workaround:
1. Change the PPN file names to reflect the case of the ABEL signal names;
or
Go back to ispDesignEXPERT and change case sensitive property to True
and regenerate your pin file.
2. Run the legacy2lci tool to convert the pin names correctly for ispLEVER.
Devices Affected:
28
Module/IP Manager
Issue:
When using Module IP/Manager for pipelined multiplier, the D-flops used for
pipeline can only have the reset as global reset. The routed reset is not
available.
Workaround:
None
Devices Affected:
ispXPGA
Issue:
Workaround:
Devices Affected:
ispXPLD
Issue:
Workaround:
None
Devices affected:
ispXPLD 5000 MX
Issue:
Numerous ORCA module and FPSC CORE dialog boxes have nonfunctioning links to datasheets.
Workaround:
Click on Help button for more information on modules and FPSC cores. More
information on all modules and cores, including data sheets, brochures, and
downloads, can be found on the Lattice Semiconductor Corporation web site at
the following URL:http://www.latticesemi.com/products.
Devices Affected:
29
Issue:
A synchronous FIFO with some parameters (or any other block using a
ROM16X1 element) generated for an ORCA4 device with Module/IP
Manager can cause an error message when run through the Project Navigator
ORCA design flow. The error states that there is a problem converting ROM
init.
Workaround:
This is a problem with Synplicity 7.3.3. The initval attributes in the Verilog
HDL or VHDL source code should be written in the form OxAEAE.
However, Synplicity writes the initval attribute in the form OxOxAEAE for
ROM16X1 elements for ORCA 4. Edit the HDL source code to remove the
extra Ox and re-run the design flow in Project Navigator. Later versions of
Synplify, such as 7.5.3, should fix this problem.
Devices Affected:
ORCA4
Online Help
Issue:
Clicking the Help button on the ispUPDATE dialog box produces a dialog box
that displays the following error message:
Cannot find the ..\..\ispcpld\bin\concepts.hlp file.
Do you want to try to find this file yourself?
Workaround:
Devices Affected:
All
Issue:
Adobe Acrobat documents (.pdf) may not display artwork correctly if using a
version of Adobe Acrobat Reader that is older than version 4.0.
Workaround:
Devices Affected:
All
30
ORCA
Issue:
Before you perform a JTAG Read and Save operation on an ORCA4 or FPSC
device, you must first instantiate the BNDSCAN library element into your
design, enable the appropriate bitgen settings, and program the device.
Workaround:
Devices Affected:
31
Issue:
There two versions of bitgen in the ispLEVER software: one for CPLD devices
located under <install_path>\ispcpld\bin, and one for ORCA
devices under <install_path>\ispfpga\bin\NT. The Project
Navigator will always use the correct version of bitgen, depending on your
project. However, when running ispLEVER programs via command line in
ispLEVER Console for ORCA devices, the CPLD bitgen will be selected
because the default path points to <install_path>\ispcpld\bin first.
Workaround:
To use the ORCA bitgen using command line, you must first manually set
<install_ path>\ispfpga\bin\NT in the PATH.
Devices Affected:
ORCA FPGA
Issue:
For better compatibility with simulators, all negative setup/hold delay numbers
in the Standard Delay Format (.sdf) file are set to 0 by default. This may
cause some discrepancies between back annotation and the TRACE (trce)
timing analysis result.
Workaround:
Use the new -neg option to get the negative numbers in the SDF file and back
annotation will match the TRACE report. But make sure that the simulator will
be able to handle negative numbers in the SDF file. For example, the following
command generates Verilog netlist and SDF file without setting the negative
setup/hold delays to 0:
ldbanno -neg -n verilog design.ncd
Devices Affected:
32
Performance Analyst
Issue:
When running Performance Analyst, when there are no timing paths for a
specific analysis type in a design (e.g. tCOE), and an option is enabled by
opening the Options dialog box and clicking OK, the Performance Analyst
may exit abruptly. If the enabled option does provide timing paths, then
Performance Analyst works as expected. If the enabled option does not provide
any timing paths, then Performance Analyst does not inform you that no timing
paths exist, and exits abruptly.
Workaround:
If the enabled options in the Options dialog box do not provide timing paths
and Performance Analyst exits abruptly, simply restart Performance Analyst
from Project Navigator.
Device Affected:
ispXPGA
Input registers should be assigned automatically for the M4A devices, but it is
possible that no input registers will be assigned. This is due to the fitter
requirement that all GLBs have a consistent macrocell to pin ratio, such as
16/8. In some M4A devices, the ratio in one GLB may be different than the
ratio in another GLB. Therefore, the input registers will not be assigned
properly for this device.
Workaround:
You can target the M4A3512/256 device and reserve pins so that the pinout of
the desired device is meet. You can then program the M4A3-512/160 device,
or the M4A3-512/192 device, using the M4A3-512/256 JEDEC file. Contact
Lattice Technical Support to obtain a constraint file with the correct pins
reserved for the device being used.
Devices Affected:
33
PLL
Issue:
Workaround:
None.
Devices Affected:
ispMACH 5000VG
Issue:
Workaround:
None
Devices affected:
ispXPLD 5000MX
Preference Editor
Issue:
Pin locate attributes defined in the HDL are not visible in the post-map
Preference Editor. These preferences are between SCHEMATIC
START/SCHEMATIC END statements in the post-mapped preference file
(.prf). Place and route will honor pin locates from HDL, and using Preference
Editor to set pin locates (including overriding those from HDL) will also be
honored. Similarly, frequency attributes defined in the HDL are not visible in
the Preference Editor.
Workaround:
To make HDL preferences visible in the Preference Editor post-map, use Edit
Constraints (ASCII) or any text editor to move these preferences to after the
SCHEMATIC END statement. They will then be visible in the Preference
Editor.
Devices Affected:
ORCA FPGA
34
Project Navigator
Issue:
Source files opened, and then saved, in Text Editor could fail to generate
database if blank spaces are left in the file name.
Workaround:
Dont leave blank spaces in file names of source files saved in the Text Editor.
Devices Affected:
All Devices
Issue:
When trying to view the JEDEC file by selecting the JEDEC File process in
the Processes for Current Source pane of the Project Navigator, and rightclicking on the view option, the JEDEC (.jed) file will not be displayed. This
option is not supported for the MACH4A, or MACH5 devices.
Workaround:
None. The view JEDEC option is not supported. View the JEDEC file with a
text editor.
Device Affected:
Issue:
When a new project is created in the same directory as an existing project, the
revision control for the old project appears in the Revision Control window.
Workaround:
None. Do not create multiple projects in the same directory when Revision
Control is enabled.
Devices Affected:
Issue:
CDR and FIFO are not supported in the Lattice Logic Simulator.
Workaround:
Devices Affected:
ispGDX2
35
Issue:
When a register signal drives a RAM/FIFO/CAM block and at the same time
outputs to a pin, it will cause a failure during timing analysis and Standard
Delay File (.sdf) file generation.
Workaround:
The failure can be prevented by preserving the register signal in the design
source code. The following examples show a workaround for a VHDL design:
Exemplar:
Attribute
Attribute
Attribute
Attribute
preserve_signal: boolean;
preserve_signal of reg_out: signal is true;
OPT : string;
OPT OF reg_out : SIGNAL IS "KEEP";
Synplicity:
Attribute
Attribute
Attribute
Attribute
syn_keep: boolean;
syn_keep of reg_out : signal is true;
OPT : string;
OPT OF reg_out: SIGNAL IS "KEEP";
Where signal reg_out is the Q output of the register that drives the memory
block.
Devices Affected:
ispXPLD 5000MX
Issue:
If you import a preference (.prf) file into Project Navigator, and the device
type is industrial, the PRF file must explicitly include the INDUSTRIAL
keyword. Otherwise, correct timing parameters will not be used.
Workaround:
After a PRF file is imported, open it using the Edit Constraints (ASCII)
process, and add keyword INDUSTRIAL;
Devices Affected:
ORCA FPGA
Issue:
The ispLEVER software aborts if you import a Verilog Test File (.tf) and then
attempt to display any Verilog Simulation Properties dialog box.
Workaround:
Before displaying any Verilog Simulation Properties dialog box, save the
project by choosing File > Save in the Project Navigator.
Device Affected:
All
36
Issue:
Workaround:
Ensure that you have the latest available version of the ispVM System software
installed on your computer before running the ISC-1532 File process in
Project Navigator.
If you are using ispLEVER Starter software, you must download the ispVM
software from the www.latticesemi.com website, and install the ispVM
software in your <install_path>\ispTOOLS directory
Devices Affected:
37
Revision History
This version of ispLEVER 3.1 Release Notes for PC contains updated information that is not contained
in the original printed version of the document that comes with the software.
Changes include:
Page 22 - A known issue was added describing warning messages that are generated in Constraint
Editor when backannotation is performed.
Page 23 - A known issue was added describing problems with Floorplanner Package View dialog box.
Page 23 - A known issue was added describing a problem with zoom feature of Floorplanner floorplan
view.
Page 23 - A known issue was added describing a problem with viewing the Synplicity License
Agreement during software installation.
Page 24 - A known issue was added describing a a possible problem with the Lattice Semiconductor
Setup Program icon during software installation.
Page 24 - A known issue was added describing a problem with the Product Options dialog box during
software installation on a client server.
Page 30 - A known issue was added describing a problem with synchronous FIFOs generated for
ORCA4 devices with Module/IP Manager when Synplicity v.7.3.3 is used as the synthesis tool.
Page 37- A known issue was added describing how an error message is generated in Project Navigator
if you run the ISC-1532 File process without having first installed the ispVM System software.
38