Академический Документы
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Author
Ralf Hffmann
9954597
Supervisor
Prof. Phil Burton, University of Limerick
Thanks to everybody who supported me here in Ireland, especially to Gerry Quilligan who gave me some useful hints how to get my circuit working and to Stephen
Bergin who set up my account on the UNIX system. I also would like to thank my
family. Without their support I could not afford my stay here in Ireland. Furthermore, thanks to my friends in Germany who still havent forgotten me and thanks
to all new friends I found here in Ireland for having a good time.
Abstract
Quite a lot of modern analogue circuits are using differential signal paths to reject
noise. Fully differential amplifiers are very useful to make such balanced circuits
possible. This report regards a design approach of a general-purpose fully differential opamp whereby some different design possibilities of a continuous-time
CMFB circuit are discussed.
Contents
1
Introduction
1.1
1.2
1.3
Basics
2.1
2.2
Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . .
2.3
Operation amplifiers . . . . . . . . . . . . . . . . . . . . . . . .
2.4
2.5
10
2.6
12
2.7
Target specification . . . . . . . . . . . . . . . . . . . . . . . . .
13
2.8
Simulation Strategy . . . . . . . . . . . . . . . . . . . . . . . . .
14
16
3.1
16
3.2
17
3.2.1
18
3.2.2
21
3.3
22
3.3.1
23
3.3.2
25
3.3.3
compensation difficulties . . . . . . . . . . . . . . . . . .
30
3.3.4
32
3.3.5
34
The CMFB
39
4.1
A continuous-time CMFB . . . . . . . . . . . . . . . . . . . . .
39
4.2
40
4.3
41
4.4
44
4.5
46
The Buffer
48
5.1
48
5.2
49
5.3
51
54
6.1
54
6.2
55
Conclusions
63
64
64
67
B Technical data
71
2
C Software
72
Chapter 1
Introduction
1.1
1.2
Fully differential opamps are very useful to build up a fully differential signal
path, which are used in many modern high-performance circuits. Because of its
symmetric manner such a balanced circuit has a very good noise rejection. Usually the positive and the negative signal are affected nearly identical by the noise
so that the noise on each signal erases each other when the negative signal is subtracted from the positive signal in a fully differential circuit. Most of the high
4
performance ADCs for example need a differential signal and there are only limited ways to build a balanced circuit without a fully differential amplifier because
there is always performance cost using a transformer or a special chip allowing
single-differential conversion . For this reasons fully differential opamp are becoming more and more important in new microcircuit designs.
1.3
Chapter 2
Basics
2.1
There are two different kinds of transistor technologies. In the early electronic
years most of the microcircuits were realized using bipolar junction transistors
(BJT) but today MOS transistors (that means Metal-Oxide Semiconductor although nowadays polysilicon is used instead of metal) dominate the industry.
MOS transistors have the big advantage that there is no current flow (except some
tiny leakage currents) between the gate and the source or drain. So nearly no energy is needed to control a MOS device. This results in a low power dissipation,
which gets more and more important in modern integrated circuits. The less energy a device needs the less heat it produces so that it can be built smaller which
also means cheaper and faster.
MOS transistors are divided into NMOS and PMOS devices to distinguish between n-channel and respectively p-channel types. Today most microcircuits are
containing both NMOS and PMOS devices. This technology is called complementary MOS (CMOS).
In n-channel devices there are negative charge carriers (i.e. the electrons) and in
6
p-channel devices there are positive charge carriers (electron-hole pairs). Before
the CMOS technology was widely available, NMOS devices gained a larger popularity because they are faster than PMOS devices because electrons have a higher
mobility than holes.
NMOS and PMOS transistors are each divided into depletion and enhancement
devices. N-channel enhancement transistors need a positive gate-to-source voltage to conduct current but depletion transistors require a gate-to-source voltage of
0V to conduct current. Depletion transistors are so called self-conducting.
In spite of MOS devices bipolar transistors always have a base current when they
are conducting. Fortunately this current is for low frequencies between 100 (for
an npn transistor) and 20 times (for a pnp transistor) smaller than the collector-toemitter current but it causes higher power dissipation. On the other hand modern
bipolar transistors can have a much higher unity-gain frequency (up to 45 GHz
and more) than MOS transistors (1 to 4 GHz).
This is the reason why nowadays the bipolar CMOS technology (BiCMOS) is
growing popularity. This technology uses both bipolar transistors and CMOS devices in the same microcircuit.
2.2
Integrated Circuits
Nowadays there are hardly any discrete electronic circuits. Most circuits are realized as integrated circuits (ICs) because this technology has some big advantages.
Of course the whole circuit becomes smaller when it is built on a single chip. So
the power dissipation must decrease, too, otherwise the IC would be heated up too
much. Usually integrated circuits are faster than discrete ones because the signal
paths on an IC are much shorter. This is beneficial for the signals because they
can hardly be affected by any external influences. Because of these reasons ICs
are usable in nearly every field of application, but the most important fact is that
ICs are cheaper than discrete circuits.
2.3
Operation amplifiers
Certainly modern amplifiers also make use of the integrated circuit technology.
There are many different one-chip amplifiers called operation amplifier or in short
form opamp. Originally developed for calculations in the analog computer technology they gained a large popularity. Many electronic circuits were even not
realizable without operation amplifiers.
An opamp is an amplification circuit with several gain stages. These gain stages
are nearly always the same for most of the different kind of opamp. The first stage
is the differential input stage, followed by the second gain stage (most often a
common-source gain stage). There is a third gain stage with an amplification of 1
called output buffer when resistive loads need to be driven. This buffer is seldom
included when the load is purely capacitive.
Another type of opamp is the folded-cascode opamp which is basically a single
gain stage opamp. I.e. it has only one dominant pole and so it is easier to compensate. Although a folded cascode opamp do not reach the gain of a two gain stage
opamp, its open loop gain is quite high due to the used cascode techniques.
Opamps are always built as an integrated circuit or as a hybrid circuit. Because of
the IC technology they use, opamps have usually superior characteristics although
they have not the ideal values they supposed to have in theory. So an ideal opamp
would have an infinite open-loop gain (
(CMMR) where a real opamp reaches values about 80 to 120dB. The bandwidth
amounts to maximum 500MHz for special opamps instead of being infinite as in
theory. The signal range certainly is not infinite but for real opamps it is a little bit
smaller than the supply voltage. Even if there is a temperature drift it is negligible
for the temperature range of -50 C to 125 C.
Of course a standard opamp will not reach top values, so that more expensive
special operation amplifiers must be used when excellent values are needed for
special applications. (E.g. video amplifiers are designed to have an excellent
bandwidth at the expense of other properties.)
2.4
A fully differential architecture has a very good noise rejection because of its
symmetric manner. Usually noise affects both signal paths (positive and negative)
nearly the same, so when the negative signal is subtracted from the positive one,
the noise on both signals cancels each other.
(2.1)
2.5
Although fully differential opamps are very beneficial for many modern circuits
there are not many available on the market because the differential output causes
some difficulties in the design. One disadvantage of fully differential opamps is
that the single-ended slew-rate often is reduced in one direction compared to the
slew-rate of an equivalent single-ended output design. The reason for this behavior is the limited maximum current for slewing given by the fixed bias currents of
the output-stages. On the other hand the unity-gain frequency usually is increased
because one of the current-mirrors is typically eliminated from the signal path.
The major problem in developing a fully differential opamp is the design of the
Common-Mode Feed-Back loop (CMFB) which is needed to realism the differential output. The CMFB circuit is used to establish the average (so called commonmode) output voltage. Ideally, this voltage should be immovable halfway between
the power-supply voltages even when there are large differential input signals.
Without this CMFB circuit the common-mode voltage is left to drift. Although
the opamp is placed in a feedback loop, the common-mode loop gain is usually
not large enough to control its value without using the CMFB circuit.
The requirements to the CMFB circuit are high: Its speed performance must be
comparable to the unity-gain frequency of the opamp to avoid that noise on the
power supplies might be significantly amplified and by this the output signals becomes distorted. Even when the CMFB itself is fast enough for the opamp it might
reduce the opamps speed due to the CMFBs resistance and capacitance which
increase the opamps load. Furthermore the CMFB should not reduce the possible
signal swing of the opamp too much.
2.6
11
also more affected by thermal noise than folded-cascode opamps. When the fully
differential opamp needs no very high bandwidth (e.g.
0/13254!687 9;:<>=@?
like
12
2.7
Target specification
My aim was to develop a general purpose fully differential opamp, which could be
used for video applications. I.e. the opamp must be able to produce a differential
ACB#D,B;D&E 4GF3F which is equivalent to a nondifferential peak to peak voltage of 9;AHB#D,B . This meets the PAL video standard
which specifies a signal voltage as maximal 9/ACB;D,B . The maximal video bandwidth
of a PAL signal is I <>=@? , so that the opamp should have a bandwidth of about
0/13254J687LK 9;:<>=@? and a corresponding linear settling time of M>N 9;:O:O P . The
peak to peak output signal of at least
opamp uses a single voltage power supply of V = 5V and the power dissipation is
specified as
9;:OW
Q E 4GRSRTNVU :OWYX
Z5[\48]^R_N
a`b c
&d U A . An open loop gain and a common mode rejection ratio of
of A
Kfe :gHh respectively i <jkjl e :gHh are required. The phase and the gain
margin should achieve values of PM m 60 respectively n <
m O:gHh to make
sure that the opamp works stable. Finally the opamp should be able to drive a
capacitive load of
i U3oap
2.8
q s tvu ;2 s r wyx-z|{
process.
Simulation Strategy
To test if the electronic circuit works like expected it has to be simulated. SPICE
is one of the most popular electronic circuit simulation software available in many
different versions (PSpice, HSpice, Spice) for many operating systems. (It is also
available one some PCs respectively UNIX-workstations in the University of Limerick.) There are also models for nearly every electronic device available and it is
possible to modify existing models or create your own (simple) models for some
13
devices. The Level1 models are simple models used to do rough hand calculations while higher level models describe the behavior of a device more precise.
Level49 models include more than 120 parameters which are extracted from the
manufacturing process.
To make it easier to simulate complex electronic circuits it is useful to work with
the behavioral mode. That means that the complex circuit is divided into smaller,
less complex circuits, so that only the part you are working on is built in detail.
The other parts of the circuit are presented by electronic models. A fully differential opamp for example can be replaced by a model of a voltage controlled voltage
source (VCVS) when the CMFB is to be developed.
The other way round the CMFB can be built with ideal devices like VCVSs,
too. This way the fully differential opamp can be developed using a rather ideal
CMFB before the real CMFB is created. It might be useful to simulate the electronic circuit with simple models first to see if it behaves like expected when it
is not affected by any parasitics effects. Certainly these simple models must have
the same values for the main parameters like or A}} . An other method to debug
14
Chapter 3
The Single-ended Opamp
3.1
When only capacitive loads need to be driven, as specified for the fully differential
opamp, either a folded-cascode or current-mirror opamp can be used. The latter
type has a larger bandwidth and a better slew-rate but it is more affected by thermal noise because its input transistors are biased at a smaller percentage of the
total current and therefore they have a smaller transconductance compared to the
input pair of the folded-cascode opamp. Due to its better noise rejection I chose
a folded-cascode design because a fully differential design usually is used to improve the noise rejection of a circuit. The required bandwidth of 0/13254!687
9;:C<=@?
can be achieved by a folded-cascode opamp, too, and the slew-rate might be improved using additional clamp transistors. Finally a folded-cascode opamp should
be able to meet the specifications.
15
3.2
16
16 :
In equation 3.1
$,
a $ 31 6
(3.1)
3.2.1
The transistors Mp3 and Mp4 supply both the input pair (Mn1,Mn2) and the cascode transistors (Mp5,Mp6) with the bias current whereby, the current source
Z5[\48]^R w
determines how much current the input transistors get. The rest of the bias
current provided by Mp3 and Mp4 flows through the cascode transistors and the
cascode current mirror.
(3.2)
(3.3)
Z5 z Z5 w #Z
When a small (e.g. positive) voltage (i.e. A 4J22m A 4!2 B ) is applied to the input of
the opamp, the current in the transistor Mn1 increases by Z while the current
in Mn2 decreases by the same amount Z . Due to 3.2, 3.3 and because the bias
currents Z5 and Z5 z are fixed, the current through Mp5 also increases and the
current in Mp6 decreases by the same value Z . The Z of Mp6 passes directly
to the load capacitance i while the additional current of Mp5 is mirrored by the
cascode current mirror (Mn7..Mn10). Finally the output current is decreased by
Z
. When the voltages applied to both of the input transistors are the same, they
both take the same current and thus the currents through the cascode transistors
are also the same and therefore, the net current to the load capacitance i
is zero.
The signal paths form the differential input transistors to the output node are
slightly different because of the current mirror. Thus, both paths have slightly
different transfer functions due to a pole-zero doublet caused by the n-channel
current mirror. Usually this can be ignored because the output is the only node
at very high impedance, so that this node causes the dominant pole and all other
poles are moved to frequencies well above the unity gain frequency
0;13254J687 . Thus,
16
(3.4)
only. The opamps
mid-band and high frequencies and thus, the gain can be approximated as
r S/ $
i
136i
(3.5)
124J687 $
i
18
(3.6)
respectively
For a large load capacitance
0;124J687
$,
0/13254!687 , i
(3.7)
$
which is given by
$ P X Z5v
(3.8)
Therefore, the ratio of width and length (W/L) and the current
13254!687
Z5v
of the input
while there is no
need for a high current in the cascode transistors. I.e. for a given power dissipation
the input transistors can be biased with a substantially higher current than the
transistors Mp5..Mn10. This maximizes the input transistors transconductance
and therefore the bandwidth is maximized and besides the thermal noise due to
136
is maximized
because all transistors which are connected to the output node, are biased at lower
currents. Finally, the dc gain is maximized, too.
Unfortunately this design approach does not work when high-frequency operation is important because of the effect of the second poles. These are primarily
due to the time constant caused by the impedance and parasitic capacitances at
the sources of the cascode transistors Mp5 and Mp6. For high frequencies these
impedances at the PMOS cascode devices are about
j y
which is usually
larger than the source impedances of the NMOS transistors in the signal path.
Thus reducing these impedances by increasing the current through the cascode
transistors should improve the opamp for high frequencies. To minimize the parasitic capacitances at the sources of the cascode transistors (Mp5,Mp6), minimizing
the peripheries and the junction areas at these nodes is important.
19
3.2.2
In figure 3.1 Mn11 and Mn12 are the clamp transistors which are added to minimize the transient voltage changes during slew-rate limiting. These transistors
prevent the drain voltages of Mn1 and Mn2 (the differential pair) from having
large transients where they get very close to the negative power supply voltage.
E.g. when a large differential input voltage causes Mn1 to be turned on completely, Mn2 will be turned off. Without the diode-connected clamp transistors all
of the current of Mp4 is directed through the cascode transistor Mp5 and through
the current mirror to the output. The output voltage over the load capacitance i
given by
z
j #Z i
(3.9)
On the other hand (in this example) during slew-rate limiting all of the bias current
Z5[\48]^R w flows through Mn1 which causes the transistor Mn1 and the current source
Z5[\48]^R w to go into the triode region. As a result, Z[\48]^R w decreases until it equals
Z# and the drain voltage of Mp3 approaches the negative power supply voltage.
After slew-rate limiting Mp3s drain voltage must turn back close to the positive
power supply voltage which takes some additional time. The diode connected
transistors Mn12 and Mn13 serve the purpose to clamp the drain voltages of Mn1
respectively Mn2. Thus these transistors allow the opamp to recover more quickly
from slew-rate conditions. Besides the insertion of the clamp transistors increase
the slew-rate of the opamp because they increase the bias currents of Mp3 and
Mp4 during slew-rate limiting. When a large differential input signal is applied
to the opamp, and one of the input transistors (e.g. Mn1) is completely turned on
while the other (Mn2) is turned off, one clamp transistor (Mn12) conducts with
the current of Mp11. This increases the current in Mp11 and also in Mp3 and
Mp4 until the sum of the currents through Mn12 and Mp3 equals
20
Z[\48]^R w .
As a
Z# z .
i
is increased due
3.3
To get familiar with the HSpice simulator I decided to start with the simulation of
the folded-cascode opamp presented in [1] on p. 295. Unfortunately, in [1] it is
not mentioned which models are used for the simulation and also the values for
the feedback resistors R1 and R2 in the unity gain configuration are not given, so
that the simulation results can not be compared exactly. For my first simulation I
used Level 1 models with the following parameters:
NMOS:
PMOS:
e ar
C ra
A 6G x >:}d I A A G6 x :}d e A
Y:}d U A % w
:}d I A % w
>
>:}d::
:}d:: r
r
whereby
(3.10)
threshold voltage,
A 6G x
is the
constant. These values were taken from [1] p 78 except for the
values which
were given with the calculation of the simulation example. ([1] p 272)
According to the specification of the fully-differential opamp, a single-voltage
After these changings the simulation result did not differ much of the simulation
results of the dual-voltage supplied opamp. I.e. the AC-plot looked still different
from the plot presented in [1] probably because other models and other values for
21
3.3.1
The cadence design tool uses by default BSIM3v3 Level 49 models of a 0.8~
n-well process. These models describe the real behavior of the electronic devices
quite good but for hand calculations they are far too complicated. (see appendix
A) Thus, I estimated the main parameters of the level 49 models to get some
values to use for rough hand calculations. Therefore the plot of the drain current
for different values of the gate-source voltage
Aa
drain current of a MOS transistor are used. The drain current of a MOS transistor
in the linear region is given by
X
Z5 Q %
SAa_
A 6G x A A &
(3.11)
X
w
Z5 Q %
%A
A 6G x
9 A &
Two equations of 3.11 are resolved to deliver KP
(3.12)
w 5Z v
Z
5
(3.13)
Q A a
%A w A X
When the transistor is in the linear region (i.e. A m : ) two values for the
drain current can be measured for a fixed value of A to get two values for each
Z# and Aa .
To estimate the threshold voltage, 3.11 can be manipulated to
A 6G x >AT A 5Z X A
Q
(3.14)
is estimated with the transistor in saturation. For a fixed gate-source voltage two
22
Id
over
Vds
Symbol
1.25m
1.2m
1.15m
1.1m
1.05m
1m
950u
900u
850u
800u
750u
700u
Result (lin)
Wave
D0:A0:Ids
650u
600u
550u
500u
450u
400u
350u
300u
250u
200u
150u
100u
50u
0
-50u
0
4
5
6
Voltage X (lin) (VOLTS)
Figure 3.2:
23
10
values of the drain current and of the drain-source voltage have to be measured.
Inserting these values in 3.12 gives the ratio
Z#v 9 A
Z# w 9 A w
(3.15)
9
(3.16)
A % A w
Using all these equations I got following parameters for the level 49 models:
NMOS:
PMOS:
O: r
>O 5r
A 6G x :}d I A A G6 x :}dJ U A
>:}d:: q >
:d!::9 r
r
(3.17)
Although the BSIM3v3 level 49 model defines more than 120 parameters it does
not give the values for e.g.
ulation to take in account the changing conditions they depend on. Nevertheless
the rough values estimated above are quite handy for first hand calculations.
3.3.2
With the new values for the most important model parameters I calculated the
single-ended folded-cascode opamp again for the same conditions as specified in
Q E G4 R%R N WYX
and the supply voltage of AE|E U A result in total current of Z6 6G]^ q : : ~
[1] but with a single-voltage supply. The given power dissipation
for the whole opamp. Thus the bias transistors Mn3 and Mn4 have to provide
200~
each because they supply the whole circuit. With 3.3 and the requirement
of having the input currents four times greater than the current through the PMOS
cascode devices the currents are given as
Z#v Z# w 9 : ~
24
(3.18)
Z# #Z z >:: ~
#Z 5Z Z#P Z# { Z5 5Z v x q : ~
The current in the bias transistors Mp3,Mp4 is set by the current source Z5[\4J]Ry and
the bias transistor Mp11. To save a little bit of power, Mp11 is scaled down to
9/O: G6
9/O: G6
of the width of Mp3 or Mp4. Thus, the drain current through Mp11 is also
of the bias transistors currents. Using a modified version of equation 3.12,
the transistors dimensions can be calculated. Here, the effective gate-drive voltage
Aa FF 1 A A 6G x
is assumed to be 0.25V.
4 4 w
X 4 S
Aa Z5(
4 4 A 6G x
(3.19)
where 4 is the number of the corresponding transistor. The formula is a little bit
simplified by ignoring the channel-length modulation term (i.e.
be zero).
Using 3.19 and a fixed length of
V9d ~ W
is assumed to
Mp6 = 90
Mn7 = 30
Mn9 = 30
Mn10 = 30 Mp11 = 15
Mn8 = 30
Mn12 = 15 Mn13 = 15
The clamp transistors were sized somewhat arbitrarily to the same dimensions
as the bias transistor Mp11 and the widths of the input transistors were not calculated but chosen to a large value of
q : : ~ W
O or -
25
:~W
I limited
their width to q
:O: ~ W
$
X y Z#v dCW
OA
(3.20)
or better
(3.21)
To place a zero at a frequency 1.2 times higher than the unity-gain frequency, a
so called lead resistor
j `
i
. Its
value is given by
9d!,9 $, U O
j ` 9 d! 9
i 31 254!687
(3.22)
j #Z z O:CA ~
i
(3.23)
without clamp transistors. When clamp transistors are used the current through
Mp3,Mp4 will be increased to
C: ~
z
j #Z i >CA ~
All these values were calculated for a load capacitance of i
(3.24)
9;: oap
Plots 3.3 and 3.4 show the results of the corresponding simulation.
These results are much closer to the example given in [1]. More important
the values for e.g. the unity-gain frequency
j> I d A ~
0/1324J687 C<>=@?
26
or the slew-rate
single-ended folded-cascode
Wave
D0:A1:vdb(dbout)
C=10pF
Symbol
80
Volts dB (lin)
60
40
20
0
-20
-40
10
100
1k
10k
100k
Frequency (log) (HERTZ)
1x
10x
100x
1x
10x
100x
1g
phase
Wave
D0:A1:p(vout)
Symbol
180
160
140
120
100
80
60
10
100
step response
Wave
D0:A0:v(vout)
D0:A0:v(vin-)
Symbol
1k
10k
100k
Frequency (log) (HERTZ)
1g
Voltages (lin)
2.8
2.6
2.4
2.2
2
0
200n
400n
600n
Time (lin) (TIME)
800n
1u
Figure 3.3: Frequency plot and step-response of the folded-cascode opamp without clamp transistors
27
single-ended folded-cascode
Wave
D0:A1:vdb(dbout)
C=10pF
Symbol
80
Volts dB (lin)
60
40
20
0
-20
-40
10
100
1k
10k
100k
Frequency (log) (HERTZ)
1x
10x
100x
1x
10x
100x
1g
phase
Wave
D0:A1:p(vout)
Symbol
180
160
140
120
100
80
60
10
100
1k
10k
100k
Frequency (log) (HERTZ)
1g
step response
Wave
D0:A0:v(vout)
D0:A0:v(vin-)
Symbol
Voltages (lin)
2.8
2.6
2.4
2.2
2
0
200n
400n
600n
Time (lin) (TIME)
800n
1u
Figure 3.4: Frequency plot and step-response of the folded-cascode opamp with
clamp transistors
28
3.3.3
compensation difficulties
i Uoap
thus the next step was to simulate the single-ended folded-cascode opamp with
this load value. In theory using a smaller
i
quency and a better slew-rate because of 3.7 and 3.9. Thus, the unity-gain frequency should rise to
of
j> q A ~
0/1324J687 U dC<>=@?
(with clamp transistors). But on the other hand the opamp might
get less stable because it is compensated only by its load capacitance. This is seen
in plot 3.5.
The step response shows a legible overshoot which points to a an undercompensation of the opamp although the frequency plot looks ok. Certainly, the
slew-rate did not double as it is supposed to be in theory but it raised a little bit
0/1324J687 qC dJ<=@?
but on the other hand the phase margin has dropped to PM=56 . Obviously, this
to
j I d A ~ .
opamp is not compensated enough with a load capacitance of 5pF so that the second poles affect the opamps behaviour.
The compensation can not be done just using a larger load capacitance because the capacitive load is specified to
i U3o0
single-ended folded-cascode
Wave
D0:A1:vdb(dbout)
C=5pF
Symbol
80
Volts dB (lin)
60
40
20
0
-20
-40
10
100
1k
10k
100k
Frequency (log) (HERTZ)
1x
10x
100x
1x
10x
100x
1g
phase
Wave
D0:A1:p(vout)
Symbol
180
160
140
120
100
80
60
40
10
100
1k
10k
100k
Frequency (log) (HERTZ)
1g
step response
Wave
D0:A0:v(vout)
D0:A0:v(vin-)
Symbol
3
Voltages (lin)
2.8
2.6
2.4
2.2
2
0
200n
400n
600n
Time (lin) (TIME)
800n
1u
Figure 3.5: Frequency plot and step-response of the folded-cascode opamp with a
i Uoap
30
current and their transconductance will decrease, too. Unfortunately, this results
in a smaller open-loop gain and less noise-rejection.
3.3.4
Obviously, the closed-loop feedback causes trouble for the opamp compensation
(see step response) because in the open-loop configuration the opamp seems to be
stable (3.5). The phase margin is a little bit too low (PM=56 ) but this can not be
the only reason for the overshooting. Furthermore, the step response plot shows
that the opamp does not achieve a gain of one although the feedback resistors
R1 and R2 are both the same (j9LjT9;:C} ). For larger values of these
resistors (e.g. j9jT@9;::} ), the gain gets closer to its ideal value of one
but the overshoot increases, too. The other way round, the gain drops to very low
values but the overshoot is gone for low resistor values (j9jT9;} ). The
opamp behaves like this because the feedback resistor is connected between the
opamps output and its negative input node which is tied to virtual ground (or in
this case to virtual analog ground i.e. 2.5V). Thus, the feedback resistor acts as
a load. For a small feedback resistor the opamp can not provide enough output
current to drive the low impedance at the output, so that the gain breaks down. In
spite, large feedback resistors do not have such high current requirements to the
output but large resistors have quite large parasitic capacitances which cause the
overshooting.
One method to avoid parasitic capacitances introduced by large resistors without loosing gain is to place a buffer between the output node of the opamp and the
feedback resistor R2. The idea is to use small feedback resistors which have only
low parasitic capacitances. The buffer ensures that the gain does not break down,
i.e. the opamp needs to provide only a little current to drive the buffer instead
of driving the feedback resistor directly. For test purposes a voltage-controlled
31
voltage source (VCVS) can be used as an ideal buffer. Figure 3.6 shows the block
diagram of the opamp with the VCVS in the feedback loop.
Figure 3.6: Block diagram of the opamp with a VCVS in the feedback loop
Figure 3.7 shows the simulation result of the opamp with the ideal buffer between output node and feedback resistor R2. The step-response was simulated
#9 :C} (i.e. unity gain) and the ac-plots were done with a
O:gHh ). Unfortunately, the overshoot
gain of ten (j99/}jTY9#:C}
with resistor values of
got even worse so that the step-response now shows a ringing. Nevertheless, the
gain now achieves its ideal value and the ideal buffer can not harm the operation of
the opamp. Thus, I keep the ideal buffer in the circuit to debug the opamp further.
32
Symbol
20
Volts dB (lin)
-20
-40
10
100
1k
10k
100k
Frequency (log) (HERTZ)
1x
10x
100x
1x
10x
100x
1g
phase
Wave
D0:A1:p(vout)
Symbol
150
100
50
10
100
1k
step response
Wave
D0:A0:v(vout)
D0:A0:v(vin-)
10k
100k
Frequency (log) (HERTZ)
1g
3.2
Symbol
Voltages (lin)
2.8
2.6
2.4
2.2
2
0
200n
400n
600n
Time (lin) (TIME)
800n
1u
Figure 3.7: Frequency plots (gain and phase) and step-response of the foldedcascode opamp with VCVS in feedback loop
33
3.3.5
As already mentioned in 3.2.1 there are second poles due to the RC-time-constant
of the impedance and parasitic capacitances at the sources of the cascode transistors. After some simulations in which I used simple level 1 models for different transistors I was convinced that, these second poles affect my opamp. When
the input, the bias and the cascode transistors (i.e. Mn1..Mp6) were replaced by
level 1 model transistors (i.e. transistors with no parasitic capacitances), the stepresponse did not show any overshooting. Thus the parasitic capacitances at the
sources of the PMOS cascode devices must be decreased. The parasitic capacitances at this node are mainly the drain-to-bulk and the drain-to-gate capacitances
of the input and bias tansistors and the gate-source capacitances of the cascode
transistors. To decrease these capacitances substantially the only way is to reduce
the sizes of the corresponding transistors. Besides, smaller input transistors take
less current, so that the current in the cascode transistors is increased and as a result their impedance is decreased. This is also beneficial to move the second poles
to higher frequencies. Thus, I tried values of U
:~W
and
9;:: ~ W
mirror, the mirror can be replaced by current sinks as in the fully-differential design. Certainly, then the cascode current sinks Mn9 and Mn10 have to be biased
by an additional bias transistor (Mn14). Usually, a current mirror is preferred to
single current sinks, because the break of the mirror which does the differentialto-single-ended conversion results in a by 6dB reduced gain. Nevertheless, the
design with the biased current sinks is closer to the fully-differential opamp. Table 3.3.5 shows the values of the widths of each transistor in the circuit. Mn14 is
the bias transistor for the current sinks Mn9 and Mn10. Its widths is chosen to bias
Mn9 and Mn10 so, that they take about the same current as in the current-mirror
design. To maximize the performance of the circuit, the widths of the current
sinks were increased to
9;:: ~ W
R 686 N 9;:: P
which is required be able to run the opamp with up to 10MHz. Finally, the clamp
transistors (Mn12,Mn13) do not affect the circuit anymore, because of the high
bias currents the circuit is supplied with. The bias transistors (Mp3,Mp4) now get
Z5[\48]^R| :: ~
Z[\48]R w CO: ~
the bias transistor for the cascode current sinks gets Z5[\4J]R q : ~ .
, the differential input pair is supplied with
Mn1 = 50
Mn2 = 50
Mp3 = 100
Mp4 = 100
Mp5 = 90
Mp6 = 90
Mn7 = 30
Mn8 = 30
Mn9 = 30
Mn10 = 30
Mp11 = 100
and
Mn14 = 30
Figure 3.8 shows the schematic of the single-ended opamp described above.
To buffer the feedback resistor a VCVS is used. Later (in the fully-differential
design) this ideal device will be replaced by a real buffer.
The plot 3.9 presents the simulation results of this opamp. As the step-response
35
(the pulse rate) shows this circuit should be able to cope with the specified speed
requirements. Thus, the folded cascode opamp can be based on this circuit.
36
single-ended opamp
Wave
D0:A1:vdb(dbout)
Symbol
20
Volts dB (lin)
-20
-40
10
100
1k
10k
100k
Frequency (log) (HERTZ)
1x
10x
100x
1x
10x
100x
1g
phase
Wave
D0:A1:p(vout)
Symbol
150
100
50
10
100
1k
10k
100k
Frequency (log) (HERTZ)
1g
step response
Wave
D0:A0:v(vout)
D0:A0:v(vin-)
Symbol
3.5
Voltages (lin)
2.5
1.5
0
200n
400n
600n
800n
1u
Time (lin) (TIME)
1.2u
1.4u
1.6u
37
Chapter 4
The CMFB
4.1
A continuous-time CMFB
should be placed exactly halfway between both power supply voltages. To build
a general-purpose fully-differential opamp a general-purpose CMFB is needed.
Thus, a switched-capacitor (SC) CMFB can not be used, because this circuit requires a clock signal. Therefore, a continuous-time (CT) CMFB is to prefer, because it can be used in any environment and does not need a clock signal. Unfortunately, continuous-time CMFBs have some disadvantages compared to SC
CMFBs, as already mentioned in 2.5. These different drawbacks will be discussed
in this chapter.
38
4.2
To get started with a fully-differential opamp an ideal CMFB circuit can be taken.
This circuit can not be build in reality because it consists of ideal devices. Nevertheless, this circuit might be useful to simulate a fully-differential opamp under
ideal conditions. Therefore, it can be tested how the opamp behaves when it is not
limited by the CMFB circuit because usually, the (real) CMFB circuit is the major limitation for a fully-differential opamp. Figure 4.1 shows a fully differential
Figure 4.1: a fully differential folded-cascode opamp with ideal CMFB circuit
folded-cascode opamp with an ideal CMFB circuit. The ideal CMFB loop consists
of four voltage-controlled voltage-sources (VCVS). The two VCVS connected to
the outputs of the opamp just work as ideal buffers to reduce the load effect of
the following resistors which act as a simple voltage divider. The common-mode
voltage of the outputs which is generated by the voltage divider (at node Vcm)
is connected to the third VCVS which compares the common-mode voltage to a
reference voltage of 2.5V. The difference between the common-mode and the reference voltage (the error-voltage) is given to the last VCVS. Here the error-voltage
39
is added to a fixed voltage Vgs. This voltage must have a value according to
the bias voltage which is needed to drive the transistors Mn9 and Mn10 in their
saturated region. As a result the control voltage A_3
| lA_. , AT$
will drive
the current sinks so that the common-mode output voltage always equals the reference voltage of 2.5V. The accuracy how close the output common-mode voltage
will get to its ideal value depends on the gain of the CMFB. Thus, using a high
gain of the last VCVS will increase the accuracy of the circuit.
4.3
40
CMFB loop works quite similar to a differential input pair: Actually, it consists
of two interlaced differential input pairs. Each of the opamps output voltages
is connected to the gate of an identical PMOS transistor (Mp14,Mp15, the first
differential input pair). When a differential output signal is applied to the CMFBinput transistors (Mp14,Mp15), usually, one output voltage rises by certain value
while the other output voltage is decreased by this value. E.g. when the positive output voltage
A 136
rises by
Aa 136 D
is decreased by
and
thus the current through Mp15 will increase. Therefore, the total current through
the transistor pair stays the same, even when large transient voltages are present.
When both output voltages rise at the same time, i.e. the output common-mode
voltage rises, the total current through Mp14 and Mp15 decreases (e.g. by
As a result, the current through the transistor pair Mp17,Mp17b does not change
either and thus the control voltage does not change. On the other hand the current
through the transistors Mp17 and Mp17b increases by Z because both transistor
pairs are supplied by the same current source. Thus, the current at node Vcntr is
decreased by
41
136 A
16 A
is given to Mp15, the differences of the currents through Mp14 and Mp15 are
not equal (Z,
z Z Z Z/ Z w Z
with:
Y w ).
Therefore, the
voltage at the drains of the differential input pair (node Vcm) does not stay
constant, although the average output voltage stays constant. Even very small
voltage changes (a few ~
4.4
There are a few tricks to reduce the effect of the non-linearity of a Differential
Difference Amplifier. Firstly, the CMFB-input transistors should have a large
gate-source voltage. This allows them to work linear for larger differential signals.
Another method is to place so called degeneration resistors between the sources
of the input transistor and the bias transistor Mp16. To keep the circuit matched,
such resistors also have to be placed in series to the transistors Mp17 and Mp17b.
The degeneration resistors also should serve the purpose to allow larger differential input signals by avoiding that all the current is directed to one side of the
CMFB input pair.
Breaking the connection of the current-mirror, i.e. using single current sinks
instead of the current-mirror, cuts the gain of the CMFB loop by 6dB. Therefore
the changing of the control voltage is reduced because the tiny changes at node
Vcm are not amplified by the current-mirror anymore.
Another approach to get a DDA CMFB working is the use of a replica of the
fully-differential opamp to provide the output voltages to the CMFB. The replica
can be run with smaller differential signals according to the CMFB which works
42
more linear for small signal swings. Therefore, the CMFB can control both, the
opamp and its replica. The replica has to be matched exactly to the opamp to ensure that both work under the same conditions. Unfortunately, you can not always
ensure that the opamp sees the same load as the replica. Furthermore, the output
voltages of the opamp might affect the replica because they are connected via the
feedback resistors to the opamps inputs, and therefore, they are also connected
(via the input resistors) to the inputs of the replica. Besides, using a replica the
space needed on a chip is doubled.
Figure 4.3 shows the DDA CMFB with degeneration resistors and single current sinks instead of the current-mirror.
Although I tried all the tricks mentioned above, I did not achieve a satisfying
result using the DDA CMFB. The non-linearities were still too strong. The gatesource voltage of the CMFB-input transistors have a value of 2.495V which is
43
the current-mirror was replaced by single current sinks the maximum possible
signal swing was not satisfying using the source generated DDA CMFB. Thus, I
designed a different CMFB circuit.
4.5
To get rid of the non-linearity problems caused by the input transistors, I replaced
the input pair by a single transistor. The common-mode output voltage is now
generated by a voltage divider consisting of two resistors. This CMFB should be
able to cope with large input signal swings because resistors are linear devices.
It should be mentioned that buffers between the opamps output and the averaging resistors of the CMFB are essential to relieve the opamp. These buffers are
not shown in figure 4.4. Certainly, the resistor averaged CMFB has less gain than
the DDA CMFB, because the generation of the common-mode voltage is done by
passive devices instead of active devices as in the DDA CMFB. A reduced gain
results in less accuracy of the resulting output common-mode voltage but on the
other hand the phase margin of the CMFB loop is increased. This is quite useful
to get the whole system stable as it will be seen in 6.2.
44
45
Chapter 5
The Buffer
5.1
Unfortunately the opamp has only a very low gain when small resistor values in
the feedback loop are used. The gain does not follow the usual formula
w
anymore. To achieve a high gain either high resistor values have to be used or
a buffer must be placed between the output node and the feedback resistor R2.
The former version is easier to implement but it has the disadvantage, that large
resistors have quite large parasitic capacitances which may affect the input of the
opamp. Besides the feedback resistor acts also as a load to the opamp because it
is connected between the output and the negative input. This input has ideally the
same potential as the positive input which is usually connected to analog ground
for a single ended opamp.
Furthermore, a buffer is needed between the outputs of the opamp and the
CMFB circuit. Otherwise the CMFB would act as a (quite large) additional load.
One method would be to use a simple opamp as an unity-gain buffer. I.e. the
output is connected directly to the negative input of the opamp. Such a buffer
works fine, but it has the drawbacks that it has usually a high power consumption.
46
5.2
Figure 5.1 shows a so called diode-prebiased source follower with resistive frequency compensation. This buffer, first presented in [11] by Marius Neag and
thermore, it should achieve a better accuracy and linearity than pure open-loop
design can do.
In figure 5.1 Mxi1 and Mxi2 are the diode-connected transistors which bias the
source-followers Mxo1 and Mxo2. When they were not biased by the diodes, the
source-followers would have an offset of their gate-source voltage. Transistors
Mxo3,4 present the common-source output stage. Together with Mxo1,2 these
transistors form an opamp with unity feedback loop. This results in a lower output
impedance while the output stage allows to provide more power to the load. To
minimize the offset of the buffer (i.e. the voltage difference between the input and
the output of the buffer) the currents through Mxi1,2 and Mxo1,2 should be equal.
The current levels through the different signal paths can be adjusted by the sizes
of the bias transistors Mxb1..Mxb6.
Table 5.2 shows the calculated sizes for the transistors, using a current source
of
Z5[\48]^R| 9 e : ~
j S B 9d!}
Mxb2 = 49.9/1.6
Mxb5 = 330/o.8
Mxb6 = 98.8/o.8
Mxb3 = 165/1.6
. Figure 5.2
Mxb4 = 49.9/1.6
Mxo4 = 499/o.8
Mxd = 100/1.6
shows the gain and phase plots and the step response of the diode-prebiased source
follower with resistive frequency compensation. Obviously, the buffer causes a
little offset and a gain error as it is seen in the step response. The offset equals
Aa F3F WYA
M 9 P .
-
48
Symbol
-5
Volts dB (lin)
-10
-15
-20
-25
-30
10
100
1k
10k
100k
Frequency (log) (HERTZ)
1x
10x
100x
1x
10x
100x
1g
phase
Wave
D0:A1:p(out)
Symbol
150
100
50
0
-50
-100
-150
10
100
1k
10k
100k
Frequency (log) (HERTZ)
1g
step response
Wave
D0:A0:v(out)
D0:A0:v(in)
Symbol
3.5
Voltages (lin)
2.5
1.5
0
50n
100n
150n
200n
400n
450n
500n
550n
600n
Figure 5.2: gain, phase and step response of the complementary source-follower
49
5.3
The gain error and offset of the buffer can cause trouble, when the buffer is placed
into the feedback loop of the folded-cascode opamp. Thus, the gain of the whole
opamp circuit does not follow the equation
where
and
w
R 7R 9
R7R is the gain of the whole circuit,
is the gain of the buffer in the feedback loop. The gain error of the buffer
results directly in a gain error of the system. For a gain error of the buffer of
+5% the system gets a gain error of +11% but for a buffer gain error of -5% the
systems gain error is -9% (assuming a gain of 1 for the opamp and the buffer).
Furthermore, it should be mentioned, that a positive offset at the buffer results in
a negative offset of the whole system (due to the inverting opamp).
Figure 5.3 shows the block diagram of an opamp with a buffer in the feedback
loop.
50
51
Chapter 6
The fully-differential Opamp
6.1
52
6.2
My first attempt to simulate the fully-differential opamp with the resistor averaged
CMFB circuit showed large overshoots in the step-response plot. Obviously, the
system was not compensated enough although the corresponding single-ended
opamp was and still ideal buffers were used. Thus, the CMFB loop itself was not
compensated well. Its phase margin was too low. To stabilize the system the gain
in the CMFB loop should be decreased to achieve a better phase margin. It has
to be mentioned that the increased phase margin will be achieved on the expense
of accuracy. I.e. the output common-mode voltage will not meet its ideal value
of 2.5V as exactly as it could be achieved with a high gain CMFB circuit. This
problem is one of the major difficulties in designing a continuous time CMFB.
The simplest method to cut the gain of the CMFB circuit is to break the connection of the current mirror. The (ex-current-mirror) transistor (M4) which is
driving the control voltage could be biased by another transistor with a fixed bias
current instead. The transistor (M3) at the other side of the current mirror might
be connected as a diode or it might be replaced by a resistor with a corresponding
value to the transistor. Another possibility is to bias the ex-current-mirror transistor pair with a fixed bias current. This circuit is shown in 6.1. The corresponding
simulation results are presented in 6.2. The simulation results show, that the circuit still is not well compensated. There are still overshoots and the circuit needs
far too long to settle although still ideal buffers are used. On the other hand the
plot shows that the calculated output common-mode voltage A
54
Symbol
D0:A0:v(vout+)
D0:A0:v(vout-)
2.8
Voltages (lin)
D0:A0:v(vin+)
D0:A0:v(vin-)
2.6
2.4
2.2
200n
400n
600n
Time (lin) (TIME)
800n
1u
800n
1u
800n
1u
Vocm
Wave
D0:A0:Vocm
Symbol
2.54
2.52
Result (lin)
2.5
2.48
2.46
2.44
2.42
2.4
200n
400n
600n
Time (lin) (TIME)
Vdiff
Wave
D0:A0:Vdiff
Symbol
Result (lin)
500m
-500m
-1
0
200n
400n
600n
Time (lin) (TIME)
Figure 6.2: step response, output common-mode voltage and differential step response
55
used to achieve a small gain, the generated control voltage might be to small to
drive the current sinks in the opamp. Therefore, it is useful to add the small
dynamic control voltage to a fixed bias voltage which is near to the voltage needed
to drive the current sink transistors. Thus the sum of the fixed bias voltage and
the dynamic control voltage generated by the CMFB loop, is large enough to
control the opamp, but the gain in the CMFB loop might be quite small. The
fixed bias voltage should be generated by a replica of the opamp to be able to
adapt on the outer conditions like temperature drift or supply voltage variation. To
add the fixed and the dynamic voltage, two current sinks (Mn9b,Mn10b) can be
placed in parallel to Mn9 and Mn10. The current which is taken by these devices
can be adjusted by sizing them to the right width. Thus, when the fixed voltage
should provide 9/10 of the total control voltage, the corresponding transistors (e.g.
Mn9,10) must have a width of about 9/10 of the total width while the transistors
Mn9b,10b must have a width of 1/10. The dynamic voltage will be applied to
these transistors.
When I experimented with different possibilities to add two voltages I found
an unconventional method to realize a resistor generated CMFB circuit. (Figure
6.3 On my way to cut the gain of the CMFB loop I simplified that circuit step
by step. At first I replaced transistor M3 by a resistor while M4 was biased by a
fixed current, then I replaced transistor M4 as well. Thus, the gain in the CMFB
circuit was minimized, but now the control voltage was too small. Therefore, the
control voltage had to be added to a fixed bias voltage. Using a bias transistor as
for biasing the single-ended opamp, can not work. If the gate and the drain are
connected both to the control voltage, the transistor would only work as a diode to
ground. When the transistors drain is only connected to the gates of the transistors
which are to be controlled while the gate is connected to the output of the CMFB
circuit, the transistor might tie down the gate-source voltage of Mn9,10 to ground
56
only. Connecting a positive voltage to the source of the control transistor, the
transistor works in a highly resistive region. Thus, this transistor acts as a voltage
controlled resistor. Therefore, the CMFB circuit needs only a small gain to drive
the control transistor, which controls the opamp.
Figure 6.4 shows the step response, the output common-mode voltage and
the differential output voltage. The circuit is able to operate up to frequencies
Figure 6.5 shows the frequency plots (gain and phase) of the fully-differential
57
Symbol
D0:A0:v(vin+)
D0:A0:v(vin-)
2.8
Voltages (lin)
D0:A0:v(vout+)
D0:A0:v(vout-)
2.6
2.4
2.2
500n
1u
1.5u
2u
2.5u
Time (lin) (TIME)
3u
3.5u
4u
3u
3.5u
4u
3u
3.5u
4u
Vocm
Wave
D0:A0:Vocm
Symbol
2.56
Result (lin)
2.54
2.52
2.5
2.48
2.46
0
500n
1u
1.5u
2u
2.5u
Time (lin) (TIME)
Vdiff
Wave
D0:A0:Vdiff
Symbol
Result (lin)
500m
-500m
-1
500n
1u
1.5u
2u
2.5u
Time (lin) (TIME)
Figure 6.4: step response, output common-mode voltage and differential step response
58
Symbol
20
10
Volts dB (lin)
-10
-20
-30
-40
-50
10
100
1k
10k
100k
Frequency (log) (HERTZ)
1x
10x
100x
1x
10x
100x
1g
phase
Symbol
150
100
50
Volts Phase (lin)
Wave
D0:A1:p(vout+)
D0:A1:p(vout-)
-50
-100
-150
10
100
1k
10k
100k
Frequency (log) (HERTZ)
59
1g
opamp able to operate fast enough. Furthermore, the four buffers in the circuit
and the resistors (especially in the CMFB loop) are quite power-hungry.
60
Chapter 7
Conclusions
Although I did not achieve what I wanted, I learned quite a lot working on this
project. The fully-differential folded-cascode opamp I developed is theoretically
able to operate at frequencies of up to 10MHz for input signals of 9;AHB#D,B . Thus, the
opamp meets the PAL-TV norm and could be used for video applications (as it was
specified). For lower frequencies the opamp can even process larger signals up to
K OAHB#D,B
which equals q
61
Appendix A
BSIM3v3 Level 49 models
A.0.1
.include /usr/local/ee4408/hspice/cux/modn.mod
.model modn nmos level=49
* ----------------------------------------------------------********************* simulation parameters ******************
* ----------------------------------------------------------* format
: hspice
* model
: mos bsim3v3
* process
: cu[beqwavp]
: 9933011 rev_b
* created
: 1998-11-17
* -----------------------------------------------------------
62
* ----------------------------------------------------------*
*
+k1
=1.057e+00
+k2
=-1.23e-01 k3
=6.535e+00 k3b
+nch
=9.114e+16 vth0
=8.481e-01
+voff
=-1.16e-01 dvt0
=3.561e+00 dvt1
+dvt2
=-2.50e-01 keta
=-4.48e-02
=-2.02e+00
=8.652e-01
=-2.98e+00 dvt1w
=1.000e-12 ub
+u0
=4.269e+02
+dsub
=-9.24e-03
+ua
=1.306e+06 dvt2w
=1.709e-18 uc
=-3.60e-11
=1.008e-02 etab
=-1.72e-02
+nfactor=6.529e-01
*
+em
=9.549e-01
=3.510e-01
+a0
=9.550e-01 a1
=0.000e+00 a2
=1.000e+00
+pvag
=0.000e+00 vsat
=8.665e+04 ags
=1.785e-01
+b0
=2.652e-07 b1
=0.000e+00 delta
=1.000e-02
+pdiblcb=2.306e-01
63
+w0
=3.151e-08 dlc
=1.449e-07
+dwc
=-8.94e-09 dwb
=0.000e+00 dwg
=0.000e+00
+ll
=0.000e+00 lw
=0.000e+00 lwl
=0.000e+00
+lln
=1.000e+00 lwn
=1.000e+00 wl
=0.000e+00
+ww
=0.000e+00 wwl
=0.000e+00 wln
=1.000e+00
+wwn
=1.000e+00
+at
=3.300e+04 ute
=-1.90e+00
+kt1
=-4.20e-01 kt2
=2.200e-02 kt1l
=0.000e+00
+ua1
=0.000e+00 ub1
=0.000e+00 uc1
=0.000e+00
+prt
=0.000e+00
***
+cgdo
=3.400e-10 cgso
=3.400e-10 cgbo
+cgdl
=0.000e+00 cgsl
+cf
=0.000e+00 elm
=5.000e+00
+xpart
=1.000e+00 clc
=1.000e-15 cle
=1.300e-10
=6.000e-01
+rdsw
=1.687e+03
+cdsc
=0.000e+00 cdscb
=0.000e+00 cdscd
=0.000e+00
+prwb
=0.000e+00 prwg
=0.000e+00 cit
=2.234e-04
+tox
=1.270e-08 ngate
+nlx
=1.000e-10
=0.000e+00
64
+xl
=0.000e+00 xw
=0.000e+00
=3.000e+01
+af
=1.343e+00 kf
=6.896e-27 ef
=1.000e+00
+noia
=1.000e+20 noib
=5.000e+04 noic
=-1.40e-12
+nlev
=0
+acm
=2
+rd
=0.000e+00 rs
=0.000e+00 rsh
+rdc
=0.000e+00 rsc
=0.000e+00
+lint
=1.449e-07
+ldif
=0.000e+00 hdif
=8.000e-07 wmlt
+lmlt
=1.000e+00 xj
=3.000e-07
+js
=2.000e-05 jsw
=0.000e+00 is
+n
=1.000e+00 nds
=1000. vnds
+cbd
=0.000e+00 cbs
=0.000e+00 cj
+cjsw
=4.300e-10 fc
=0.000e+00
+mj
=4.400e-01 mjsw
=2.500e-01 tt
+pb
=8.400e-01 php
=9.400e-01
A.0.2
wint
=3.000e+01
=-8.94e-09
=1.000e+00
=0.000e+00
=-1.000e+00
=3.800e-04
=0.000e+00
* ----------------------------------------------------------.include /usr/local/ee4408/hspice/cux/modp.mod
.model modp pmos level=49
* ----------------------------------------------------65
: hspice
* model
: mos bsim3v3
* process
: cu[beqwavp]
: 9933011 rev_b
* created
: 1998-11-17
* ----------------------------------------------------------*
* ----------------------------------------------------------*
*
+k1
=5.626e-01
+k2
=-1.66e-02 k3
=1.485e+01 k3b
+nch
=5.948e+16 vth0
=-7.85e-01
+voff
=-1.12e-01 dvt0
=2.066e+00 dvt1
+dvt2
=-3.99e-02 keta
=-7.67e-03
=-1.40e+00
=5.015e-01
=0.000e+00 dvt1w
=0.000e+00 dvt2w
=0.000e+00
66
+ua
=6.770e-11 ub
+u0
=1.115e+02
=1.040e-18 uc
=-1.16e-10
+dsub
=4.379e-01 eta0
=4.843e-02 etab
=-3.50e-05
+nfactor=2.220e-01
*
+em
=4.100e+07 pclm
=1.459e+00
=7.861e-02
+a0
=7.522e-01 a1
=0.000e+00 a2
=1.000e+00
+pvag
=0.000e+00 vsat
=9.496e+04 ags
=1.746e-01
+b0
=3.421e-07 b1
=0.000e+00 delta
=1.000e-02
+pdiblcb=-3.18e-01
*
+w0
=7.289e-07 dlc
=9.927e-08
+dwc
=3.878e-08 dwb
=0.000e+00 dwg
=0.000e+00
+ll
=0.000e+00 lw
=0.000e+00 lwl
=0.000e+00
+lln
=1.000e+00 lwn
=1.000e+00 wl
=0.000e+00
+ww
=0.000e+00 wwl
=0.000e+00 wln
=1.000e+00
+wwn
=1.000e+00
+at
=3.300e+04 ute
=-1.40e+00
+kt1
=-5.70e-01 kt2
=2.200e-02 kt1l
=0.000e+00
+ua1
=0.000e+00 ub1
=0.000e+00 uc1
=0.000e+00
+prt
=0.000e+00
+cgdo
***
=3.400e-10 cgso
=3.400e-10 cgbo
67
=1.300e-10
+cgdl
=0.000e+00 cgsl
+cf
=0.000e+00 elm
=5.000e+00
+xpart
=1.000e+00 clc
=1.000e-15 cle
=6.000e-01
+rdsw
=3.796e+03
+cdsc
=0.000e+00 cdscb
=0.000e+00 cdscd
=2.171e-04
+prwb
=0.000e+00 prwg
=0.000e+00 cit
=3.231e-04
+tox
=1.270e-08 ngate
+nlx
=2.784e-07
+xl
=0.000e+00 xw
=0.000e+00
=0.000e+00
=3.000e+01
+af
=1.772e+00 kf
=1.126e-26 ef
=1.000e+00
+noia
=1.000e+20 noib
=5.000e+04 noic
=-1.40e-12
+nlev
=0
+acm
=2
+rd
=0.000e+00 rs
=0.000e+00 rsh
+rdc
=0.000e+00 rsc
=0.000e+00
+lint
=9.927e-08
+ldif
=0.000e+00 hdif
=8.000e-07 wmlt
+lmlt
=1.000e+00 xj
=3.000e-07
+js
=2.000e-05 jsw
=0.000e+00 is
wint
=6.000e+01
=3.878e-08
68
=1.000e+00
=0.000e+00
+n
=1.000e+00 nds
=1000. vnds
+cbd
=0.000e+00 cbs
=0.000e+00 cj
+cjsw
=3.300e-10 fc
=0.000e+00
+mj
=4.400e-01 mjsw
=2.400e-01 tt
+pb
=8.400e-01 php
=9.400e-01
69
=-1.000e+00
=6.000e-04
=0.000e+00
Appendix B
Technical data
0 9;:C<=@?
peak-to-peak input voltage:
A 9/ACB;D,B
power consumption:
AACB;D,B#D&E 4GF3F .
M CI U P .
slew-rate downwards: j>9 I d r R
slew-rate upwards: jd e r R
unity-gain frequency 0/13254J687 d U <>=@?
phase margin: PM = 77.3
Q E 4GR%R q :WYX
For lower frequencies the opamp works even for larger differential signals.
70
Appendix C
Software
Below is a short list of the software I used for the project.
Most time I typed in the hspice netlists instead of using the schematic entry. This
method has the advantage that changes in the circuit can be realised much easier and faster. All changes can be made in the netlist at once and devices can be
copied or out-commented which is quite handy to insert or delete whole devices.
Using the schematic entry, each device has to be selected to change its values and
it is more complicated to insert respectively delete devices. On the other hand the
schematic entry has the benefit that you always can see how the circuit looks like.
It is more difficult to see how all the devices are connected by reading the netlist
of a circuit.
xv 3.10 (screengrabber)
xEmacs
LATEX
xdvi
Adobe AcrobatReader
Suse-Linux 6.3:
xEmacs
LATEX
xdvi
Adobe AcrobatReader
Windows NT/98:
Orcad 9 PSpice Demo
72
Bibliography
[1] David. A. Johns, Ken Martin; Analog integrated circuit design
[2] Adel S. Sedra, Kenneth C. Smith; Microelectronic Circuits
[3] Kenneth R. Laker, Willy M.C. Sansen; Design of analog integrated circuits
and systems
[4] Ulrich Ludemann; script of the lecture "Halbleiterschaltungstechnik" (corresponding to Active Circuit Design)
[5] Winfried Soppa; working sheets of the lecture "Schaltkreissimulation mit
SPICE"
[6] Norbert Emeis; script of the lecture "Bauelemente der Elektronik"
[7] Oliver McCarthy; notes of the lecture "Analog Integrated Circuit Design"
[8] Ian Grout; notes of the lecture "ASICs II"
[9] online manual of the Star HSpice 99.2 simulator
[10] META-SOFTWARE; HSpice, Quick Reference Guide
[11] C. Beccari, M. Biey, P.P. Civvalleri, M. Gilli; European Conference on Circuit Theory and Design 99
73