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A fully differential opamp

Author
Ralf Hffmann
9954597

Supervisor
Prof. Phil Burton, University of Limerick

BEng Electronic Engineering


Department of Electronic and Computer Engineering
University of Limerick, Ireland
Europisches Elektrotechnik Studium, Nachrichtentechnik
FH Osnabrck, Germany

Submitted in part requirement for final year project University of Limerick,


Limerick, Ireland
24.04.2000

Thanks to everybody who supported me here in Ireland, especially to Gerry Quilligan who gave me some useful hints how to get my circuit working and to Stephen
Bergin who set up my account on the UNIX system. I also would like to thank my
family. Without their support I could not afford my stay here in Ireland. Furthermore, thanks to my friends in Germany who still havent forgotten me and thanks
to all new friends I found here in Ireland for having a good time.

Abstract
Quite a lot of modern analogue circuits are using differential signal paths to reject
noise. Fully differential amplifiers are very useful to make such balanced circuits
possible. This report regards a design approach of a general-purpose fully differential opamp whereby some different design possibilities of a continuous-time
CMFB circuit are discussed.

Contents
1

Introduction

1.1

What is a fully differential opamp? . . . . . . . . . . . . . . . . .

1.2

Is there a need for fully differential opamps? . . . . . . . . . . . .

1.3

Why I chose this project . . . . . . . . . . . . . . . . . . . . . .

Basics

2.1

Introduction of different transistor technologies . . . . . . . . . .

2.2

Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . .

2.3

Operation amplifiers . . . . . . . . . . . . . . . . . . . . . . . .

2.4

The benefits of a fully differential architecture . . . . . . . . . . .

2.5

Known difficulties of fully differential amplifiers . . . . . . . . .

10

2.6

Investigation and possible solutions . . . . . . . . . . . . . . . .

12

2.7

Target specification . . . . . . . . . . . . . . . . . . . . . . . . .

13

2.8

Simulation Strategy . . . . . . . . . . . . . . . . . . . . . . . . .

14

The Single-ended Opamp

16

3.1

What kind of opamp is to be used? . . . . . . . . . . . . . . . . .

16

3.2

The folded-cascode opamp . . . . . . . . . . . . . . . . . . . . .

17

3.2.1

operating method of the folded-cascode opamp . . . . . .

18

3.2.2

Slew-rate and clamp transistors . . . . . . . . . . . . . .

21

3.3

Simulation of the folded-cascode opamp . . . . . . . . . . . . . .

22

3.3.1

Estimation of the main parameters of the level 49 models .

23

3.3.2

Simulation of the folded-cascode opamp (level 49 models)

25

3.3.3

compensation difficulties . . . . . . . . . . . . . . . . . .

30

3.3.4

The feedback resistors . . . . . . . . . . . . . . . . . . .

32

3.3.5

down-sizing the transistors . . . . . . . . . . . . . . . . .

34

The CMFB

39

4.1

A continuous-time CMFB . . . . . . . . . . . . . . . . . . . . .

39

4.2

The ideal common-mode feedback circuit . . . . . . . . . . . . .

40

4.3

A Differential Difference Amplifier (DDA) CMFB . . . . . . . .

41

4.4

Tricks to improve the DDA CMFB . . . . . . . . . . . . . . . . .

44

4.5

The Resistor Averaged CMFB . . . . . . . . . . . . . . . . . . .

46

The Buffer

48

5.1

Why a buffer is needed . . . . . . . . . . . . . . . . . . . . . . .

48

5.2

The diode-prebiased source follower . . . . . . . . . . . . . . . .

49

5.3

Gain error and offset . . . . . . . . . . . . . . . . . . . . . . . .

51

The fully-differential Opamp

54

6.1

The fully-differential folded-cascode opamp . . . . . . . . . . . .

54

6.2

The CMFB loop . . . . . . . . . . . . . . . . . . . . . . . . . . .

55

Conclusions

63

A BSIM3v3 Level 49 models

64

A.0.1 The NMOS transistor model . . . . . . . . . . . . . . . .

64

A.0.2 The PMOS transistor model . . . . . . . . . . . . . . . .

67

B Technical data

71
2

C Software

72

Chapter 1
Introduction
1.1

What is a fully differential opamp?

A fully differential opamp is an operation amplifier with a differential input stage


(which is typically for every opamp) and also a differential output stage. This
means that this amplifier has both two inputs (a positive one and an inverted so
called negative input) and two outputs (a positive and a negative one). So this
opamp is a kind of balanced circuit, which should behave like a solid-state transformer.

1.2

Is there a need for fully differential opamps?

Fully differential opamps are very useful to build up a fully differential signal
path, which are used in many modern high-performance circuits. Because of its
symmetric manner such a balanced circuit has a very good noise rejection. Usually the positive and the negative signal are affected nearly identical by the noise
so that the noise on each signal erases each other when the negative signal is subtracted from the positive signal in a fully differential circuit. Most of the high
4

performance ADCs for example need a differential signal and there are only limited ways to build a balanced circuit without a fully differential amplifier because
there is always performance cost using a transformer or a special chip allowing
single-differential conversion . For this reasons fully differential opamp are becoming more and more important in new microcircuit designs.

1.3

Why I chose this project

When I decided to study electronics I wanted to learn how to design electronic


circuits. Unfortunately there are no possibilities to study circuit design in more
detail at my home University, the Fachhochschule Osnabrck. So I did not have
any experience in circuit design when I chose my final year project. To do do
an analog IC design of a fully differential opamp really sounded like a challenge.
Besides such a device would be very useful for audio and video applications which
is the field of electronics I am interested in most.

Chapter 2
Basics
2.1

Introduction of different transistor technologies

There are two different kinds of transistor technologies. In the early electronic
years most of the microcircuits were realized using bipolar junction transistors
(BJT) but today MOS transistors (that means Metal-Oxide Semiconductor although nowadays polysilicon is used instead of metal) dominate the industry.
MOS transistors have the big advantage that there is no current flow (except some
tiny leakage currents) between the gate and the source or drain. So nearly no energy is needed to control a MOS device. This results in a low power dissipation,
which gets more and more important in modern integrated circuits. The less energy a device needs the less heat it produces so that it can be built smaller which
also means cheaper and faster.
MOS transistors are divided into NMOS and PMOS devices to distinguish between n-channel and respectively p-channel types. Today most microcircuits are
containing both NMOS and PMOS devices. This technology is called complementary MOS (CMOS).
In n-channel devices there are negative charge carriers (i.e. the electrons) and in
6

p-channel devices there are positive charge carriers (electron-hole pairs). Before
the CMOS technology was widely available, NMOS devices gained a larger popularity because they are faster than PMOS devices because electrons have a higher
mobility than holes.
NMOS and PMOS transistors are each divided into depletion and enhancement
devices. N-channel enhancement transistors need a positive gate-to-source voltage to conduct current but depletion transistors require a gate-to-source voltage of
0V to conduct current. Depletion transistors are so called self-conducting.
In spite of MOS devices bipolar transistors always have a base current when they
are conducting. Fortunately this current is for low frequencies between 100 (for
an npn transistor) and 20 times (for a pnp transistor) smaller than the collector-toemitter current but it causes higher power dissipation. On the other hand modern
bipolar transistors can have a much higher unity-gain frequency (up to 45 GHz
and more) than MOS transistors (1 to 4 GHz).
This is the reason why nowadays the bipolar CMOS technology (BiCMOS) is
growing popularity. This technology uses both bipolar transistors and CMOS devices in the same microcircuit.

2.2

Integrated Circuits

Nowadays there are hardly any discrete electronic circuits. Most circuits are realized as integrated circuits (ICs) because this technology has some big advantages.
Of course the whole circuit becomes smaller when it is built on a single chip. So
the power dissipation must decrease, too, otherwise the IC would be heated up too
much. Usually integrated circuits are faster than discrete ones because the signal
paths on an IC are much shorter. This is beneficial for the signals because they

can hardly be affected by any external influences. Because of these reasons ICs
are usable in nearly every field of application, but the most important fact is that
ICs are cheaper than discrete circuits.

2.3

Operation amplifiers

Certainly modern amplifiers also make use of the integrated circuit technology.
There are many different one-chip amplifiers called operation amplifier or in short
form opamp. Originally developed for calculations in the analog computer technology they gained a large popularity. Many electronic circuits were even not
realizable without operation amplifiers.
An opamp is an amplification circuit with several gain stages. These gain stages
are nearly always the same for most of the different kind of opamp. The first stage
is the differential input stage, followed by the second gain stage (most often a
common-source gain stage). There is a third gain stage with an amplification of 1
called output buffer when resistive loads need to be driven. This buffer is seldom
included when the load is purely capacitive.
Another type of opamp is the folded-cascode opamp which is basically a single
gain stage opamp. I.e. it has only one dominant pole and so it is easier to compensate. Although a folded cascode opamp do not reach the gain of a two gain stage
opamp, its open loop gain is quite high due to the used cascode techniques.
Opamps are always built as an integrated circuit or as a hybrid circuit. Because of
the IC technology they use, opamps have usually superior characteristics although
they have not the ideal values they supposed to have in theory. So an ideal opamp
would have an infinite open-loop gain (



) and common mode rejection ratio

(CMMR) where a real opamp reaches values about 80 to 120dB. The bandwidth
amounts to maximum 500MHz for special opamps instead of being infinite as in

theory. The signal range certainly is not infinite but for real opamps it is a little bit
smaller than the supply voltage. Even if there is a temperature drift it is negligible
for the temperature range of -50  C to 125  C.
Of course a standard opamp will not reach top values, so that more expensive
special operation amplifiers must be used when excellent values are needed for
special applications. (E.g. video amplifiers are designed to have an excellent
bandwidth at the expense of other properties.)

2.4

The benefits of a fully differential architecture

A fully differential architecture has a very good noise rejection because of its
symmetric manner. Usually noise affects both signal paths (positive and negative)
nearly the same, so when the negative signal is subtracted from the positive one,
the noise on both signals cancels each other.


   
  

(2.1)

 !#"%$& ('&) *! (+,"-/.


The differential architecture helps to reject noise from the substrate as well as
from pass-transistor switches turning off in switched capacitor applications.
Unfortunately the noise does not affect the positive and the negative signal exactly
the same and there are also other noise sources. But in spite of this the noise
rejection is still much better than using an unbalanced architecture.
That is why many modern high-performance circuits make use of fully differential
signal paths.

2.5

Known difficulties of fully differential amplifiers

Although fully differential opamps are very beneficial for many modern circuits
there are not many available on the market because the differential output causes
some difficulties in the design. One disadvantage of fully differential opamps is
that the single-ended slew-rate often is reduced in one direction compared to the
slew-rate of an equivalent single-ended output design. The reason for this behavior is the limited maximum current for slewing given by the fixed bias currents of
the output-stages. On the other hand the unity-gain frequency usually is increased
because one of the current-mirrors is typically eliminated from the signal path.
The major problem in developing a fully differential opamp is the design of the
Common-Mode Feed-Back loop (CMFB) which is needed to realism the differential output. The CMFB circuit is used to establish the average (so called commonmode) output voltage. Ideally, this voltage should be immovable halfway between
the power-supply voltages even when there are large differential input signals.
Without this CMFB circuit the common-mode voltage is left to drift. Although
the opamp is placed in a feedback loop, the common-mode loop gain is usually
not large enough to control its value without using the CMFB circuit.
The requirements to the CMFB circuit are high: Its speed performance must be
comparable to the unity-gain frequency of the opamp to avoid that noise on the
power supplies might be significantly amplified and by this the output signals becomes distorted. Even when the CMFB itself is fast enough for the opamp it might
reduce the opamps speed due to the CMFBs resistance and capacitance which
increase the opamps load. Furthermore the CMFB should not reduce the possible
signal swing of the opamp too much.

Typically there are two different CMFB designs - a continuous-time (CT)


respectively a switched-capacitor (SC) design. The continuous-time CMFB is
10

hardly explored yet because the switched-capacitor CMFB is somewhat easier to


realism. The major benefits of a switched-capacitor CMFB are that it usually does
not limit the signal swings or the frequency range. Switched-capacitors CMFBs
can cause clock-feedthrough glitches in continuous-time systems but this is no
major problem. The output signals of the opamp can be sampled at the right time
to get an output signal without any glitches. The major drawback of an SC CMFB
is the need of a clock signal which forbids the use in many applications where no
clock signal is available. Another disadvantage of SC CMFBs is that they usually
increase the capacitive load of the opamp and so they slow down the circuit.

In opposite to switched-capacitor CMFBs, continuous-time CMFB loops often


do not work properly when large differential signals are present. Continuous-time
circuits are often the major limitation on the maximum signal range because they
are limiting the signals more than the differential signal-path does. The problem
is to build a continuous-time CMFB which works linear over a wide signal range.
I will go a little bit more in detail about these difficulties later when I describe the
different CMFB approaches I tried. (4) Although the continuous-time design has
some drawbacks there is one major advantage compared to switched-capacitor
circuits. The CT CMFB can be used in every environment because it does not
need a clock signal. That is why a continuous-time CMFB is preferable when a
general purpose fully differential opamp is to be designed.

2.6

Investigation and possible solutions

There are some different possibilities in designing a fully differential opamp. It


can be realized as a folded-cascode opamp or as a fully differential current-mirror
opamp. The latter type has a larger bandwidth and a better slew-rate but it is

11

also more affected by thermal noise than folded-cascode opamps. When the fully
differential opamp needs no very high bandwidth (e.g.

0/13254!687  9;:<>=@?

like

specified for this opamp) a folded-cascode opamp is preferable to a current-mirror


amp because of its better noise rejection. The slew-rate of a folded-cascode opamp
can be increased anyway using so called clamp transistors.

Figure 2.1: a fully differential folded-cascode opamp

Figure 2.1([1] p267/282) shows a fully differential folded-cascode opamp.


Mn11 and Mn12 are the clamp transistors added to minimize the transient voltage
changes during slew-rate limiting. These transistors prevent the drain voltages of
Mn1 and Mn2 (the differential pair) from having large transients where they get
very close to the negative power supply voltage. So these transistors allows the
opamp to recover more quickly and thus the slew-rate of this opamp increases.

12

2.7

Target specification

My aim was to develop a general purpose fully differential opamp, which could be
used for video applications. I.e. the opamp must be able to produce a differential

 ACB#D,B;D&E 4GF3F which is equivalent to a nondifferential peak to peak voltage of 9;AHB#D,B . This meets the PAL video standard
which specifies a signal voltage as maximal 9/ACB;D,B . The maximal video bandwidth
of a PAL signal is I <>=@? , so that the opamp should have a bandwidth of about
0/13254J687LK 9;:<>=@? and a corresponding linear settling time of M>N 9;:O:O P . The
peak to peak output signal of at least

opamp uses a single voltage power supply of V = 5V and the power dissipation is
specified as

9;:OW

Q E 4GRSRTNVU :OWYX

, i.e. the bias current must not be larger than

Z5[\48]^R_N

. The single voltage source of 5V requires a common-mode output voltage

a`b c
 &d U A . An open loop gain and a common mode rejection ratio of
of A
 Kfe :gHh respectively i <jkjl e :gHh are required. The phase and the gain
margin should achieve values of PM m 60  respectively n <
m O:gHh to make
sure that the opamp works stable. Finally the opamp should be able to drive a
capacitive load of

i   U3oap

and the noise must not be larger than

which equals a resolution of 11 bit.

The opamp could be realized in an n-well :}d U~

2.8

q s tvu ;2 s r wyx-z|{

process.

Simulation Strategy

To test if the electronic circuit works like expected it has to be simulated. SPICE
is one of the most popular electronic circuit simulation software available in many
different versions (PSpice, HSpice, Spice) for many operating systems. (It is also
available one some PCs respectively UNIX-workstations in the University of Limerick.) There are also models for nearly every electronic device available and it is
possible to modify existing models or create your own (simple) models for some
13

devices. The Level1 models are simple models used to do rough hand calculations while higher level models describe the behavior of a device more precise.
Level49 models include more than 120 parameters which are extracted from the
manufacturing process.
To make it easier to simulate complex electronic circuits it is useful to work with
the behavioral mode. That means that the complex circuit is divided into smaller,
less complex circuits, so that only the part you are working on is built in detail.
The other parts of the circuit are presented by electronic models. A fully differential opamp for example can be replaced by a model of a voltage controlled voltage
source (VCVS) when the CMFB is to be developed.
The other way round the CMFB can be built with ideal devices like VCVSs,
too. This way the fully differential opamp can be developed using a rather ideal
CMFB before the real CMFB is created. It might be useful to simulate the electronic circuit with simple models first to see if it behaves like expected when it
is not affected by any parasitics effects. Certainly these simple models must have
the same values for the main parameters like or A}} . An other method to debug

a circuit is to place voltage controlled voltage sources in the circuit. Connected


as ideal buffers these devices can reduce some non-ideal effects like e.g. the parasitic capacitance of a resistor. Later the ideal buffers can be replaced by real
buffers which can be created as sub-circuit. Of course these sub-circuits should
be simulated and optimized as a stand alone circuit before they are used in the
main design.

14

Chapter 3
The Single-ended Opamp
3.1

What kind of opamp is to be used?

When only capacitive loads need to be driven, as specified for the fully differential
opamp, either a folded-cascode or current-mirror opamp can be used. The latter
type has a larger bandwidth and a better slew-rate but it is more affected by thermal noise because its input transistors are biased at a smaller percentage of the
total current and therefore they have a smaller transconductance compared to the
input pair of the folded-cascode opamp. Due to its better noise rejection I chose
a folded-cascode design because a fully differential design usually is used to improve the noise rejection of a circuit. The required bandwidth of 0/13254!687

9;:C<=@?

can be achieved by a folded-cascode opamp, too, and the slew-rate might be improved using additional clamp transistors. Finally a folded-cascode opamp should
be able to meet the specifications.

15

3.2

The folded-cascode opamp

The fully differential opamp is based on a single-ended folded-cascode opamp


(Figure 3.1). Although the folded cascode-opamp is basically a single gain stage
opamp, it can achieve a quite high gain due to the cascode technique. The input
transistor pair (Mn1, Mn2) and the bias transistors (Mp3, Mp4) are connected to
the sources of the cascode transistors (Mp5, Mp6) while a wide-swing cascode
current mirror (Mn7..Mn10) is connected to the drains of the cascode transistors.
As a result, the output node which is placed between the cascode PMOS devices
and the current mirror, is the only high-impedance node in the circuit. All other
nodes are connected to a source of a transistor so that they have relatively low
impedance which is on the order of a transistors transconductance. Due to their
low impedance, all internal nodes have only small voltages, but they can carry
quite large currents. That is why this kind of opamp is sometimes called a currentmode opamp. Another effect of the low impedance at the internal nodes is that the
speed of the opamp is maximized. The folded-cascode opamp is compensated by
its load capacitance, whereby the opamp becomes more stable but also slower,
when a large load capacitance is used. One very important property of such an
opamp is its transconductance, i.e. the ratio of the output current to the input voltage. Due to this parameter, this type of opamp is also referred to as Operational
Transconductance Amplifiers (OTA).
The differential-to-single-ended conversion is done by the NMOS current mirror. The use of a wide-swing cascode current mirror ensures a larger impedance
looking downward from the output node as it could be achieved using a simple
current mirror.Looking upwards from the output node, the cascode of Mp6 and
Mp4 ensures a high impedance at the output node. As a result, the open-loop gain



of the folded-cascode opamp is maximized because it depends on the output

16

Figure 3.1: a folded-cascode opamp


impedance

16 :

In equation 3.1

$,

a $ 31 6

(3.1)

is the transconductance of the input stage which equals the

transconductance of one of the input transistors.

3.2.1

operating method of the folded-cascode opamp

The transistors Mp3 and Mp4 supply both the input pair (Mn1,Mn2) and the cascode transistors (Mp5,Mp6) with the bias current whereby, the current source

Z5[\48]^R w

determines how much current the input transistors get. The rest of the bias

current provided by Mp3 and Mp4 flows through the cascode transistors and the
cascode current mirror.

Z5  Z5v  Z#


17

(3.2)

(3.3)
Z5 z  Z5 w  #Z 
When a small (e.g. positive) voltage (i.e. A 4J22m A 4!2 B ) is applied to the input of
the opamp, the current in the transistor Mn1 increases by Z while the current
in Mn2 decreases by the same amount Z . Due to 3.2, 3.3 and because the bias
currents Z5 and Z5 z are fixed, the current through Mp5 also increases and the
current in Mp6 decreases by the same value Z . The Z of Mp6 passes directly

to the load capacitance i while the additional current of Mp5 is mirrored by the
cascode current mirror (Mn7..Mn10). Finally the output current is decreased by

 Z

. When the voltages applied to both of the input transistors are the same, they

both take the same current and thus the currents through the cascode transistors
are also the same and therefore, the net current to the load capacitance i

is zero.

The signal paths form the differential input transistors to the output node are
slightly different because of the current mirror. Thus, both paths have slightly
different transfer functions due to a pole-zero doublet caused by the n-channel
current mirror. Usually this can be ignored because the output is the only node
at very high impedance, so that this node causes the dominant pole and all other
poles are moved to frequencies well above the unity gain frequency

0;13254J687 . Thus,

the approximate small-signal transfer function is given by

r %, aA A 31 6 S %//   9$,  136 


4J2
136i

when the compensation is realized by the load capacitance i


output impedance

16

(3.4)
only. The opamps

is quite large, so that the load capacitance dominates for

mid-band and high frequencies and thus, the gain can be approximated as


r S/  $    
i
136i

(3.5)

From equation 3.5 the unity gain frequency is obtained as

124J687  $ 
i

18

(3.6)

respectively
For a large load capacitance

0;124J687

$,
0/13254!687  , i 

(3.7)

is much less than the limit imposed by the

second poles. Thus, the bandwidth is determined by the transconductance

$

which is given by

$  P X  Z5v

(3.8)

Therefore, the ratio of width and length (W/L) and the current

transistors must have certain values to meet the specified

13254!687

Z5v

of the input

while there is no

need for a high current in the cascode transistors. I.e. for a given power dissipation
the input transistors can be biased with a substantially higher current than the
transistors Mp5..Mn10. This maximizes the input transistors transconductance
and therefore the bandwidth is maximized and besides the thermal noise due to

136

the input pair is reduced. Furthermore the output impedance

is maximized

because all transistors which are connected to the output node, are biased at lower
currents. Finally, the dc gain is maximized, too.
Unfortunately this design approach does not work when high-frequency operation is important because of the effect of the second poles. These are primarily
due to the time constant caused by the impedance and parasitic capacitances at
the sources of the cascode transistors Mp5 and Mp6. For high frequencies these
impedances at the PMOS cascode devices are about

j  y 

which is usually

larger than the source impedances of the NMOS transistors in the signal path.
Thus reducing these impedances by increasing the current through the cascode
transistors should improve the opamp for high frequencies. To minimize the parasitic capacitances at the sources of the cascode transistors (Mp5,Mp6), minimizing
the peripheries and the junction areas at these nodes is important.

19

3.2.2

Slew-rate and clamp transistors

In figure 3.1 Mn11 and Mn12 are the clamp transistors which are added to minimize the transient voltage changes during slew-rate limiting. These transistors
prevent the drain voltages of Mn1 and Mn2 (the differential pair) from having
large transients where they get very close to the negative power supply voltage.
E.g. when a large differential input voltage causes Mn1 to be turned on completely, Mn2 will be turned off. Without the diode-connected clamp transistors all
of the current of Mp4 is directed through the cascode transistor Mp5 and through
the current mirror to the output. The output voltage over the load capacitance i

will decrease with a slew-rate

given by

z
j #Z i 

(3.9)

On the other hand (in this example) during slew-rate limiting all of the bias current

Z5[\48]^R w flows through Mn1 which causes the transistor Mn1 and the current source
Z5[\48]^R w to go into the triode region. As a result, Z[\48]^R w decreases until it equals
Z# and the drain voltage of Mp3 approaches the negative power supply voltage.

After slew-rate limiting Mp3s drain voltage must turn back close to the positive
power supply voltage which takes some additional time. The diode connected
transistors Mn12 and Mn13 serve the purpose to clamp the drain voltages of Mn1
respectively Mn2. Thus these transistors allow the opamp to recover more quickly
from slew-rate conditions. Besides the insertion of the clamp transistors increase
the slew-rate of the opamp because they increase the bias currents of Mp3 and
Mp4 during slew-rate limiting. When a large differential input signal is applied
to the opamp, and one of the input transistors (e.g. Mn1) is completely turned on
while the other (Mn2) is turned off, one clamp transistor (Mn12) conducts with
the current of Mp11. This increases the current in Mp11 and also in Mp3 and
Mp4 until the sum of the currents through Mn12 and Mp3 equals
20

Z[\48]^R w .

As a

result the output current which charges the load capacitance


to the increase of

Z# z .

i 

is increased due

I.e. the slew-rate, which determines how fast the opamp

can follow an input signal, is improved.

3.3

Simulation of the folded-cascode opamp

To get familiar with the HSpice simulator I decided to start with the simulation of
the folded-cascode opamp presented in [1] on p. 295. Unfortunately, in [1] it is
not mentioned which models are used for the simulation and also the values for
the feedback resistors R1 and R2 in the unity gain configuration are not given, so
that the simulation results can not be compared exactly. For my first simulation I
used Level 1 models with the following parameters:
NMOS:

PMOS:

 e ar
C ra
A 6G x >:}d I A A G6 x  :}d e A
Y:}d U A % w 
 :}d I A % w
>
>:}d::
 :}d:: r
r
whereby

(3.10)

is the intrinsic transistor conduction (also called KP),

threshold voltage,

is the body-effect parameter and

A 6G x

is the

is the output impedance

constant. These values were taken from [1] p 78 except for the

values which

were given with the calculation of the simulation example. ([1] p 272)
According to the specification of the fully-differential opamp, a single-voltage

AEE U A was used in the second simulation attempt. So, the


bias voltages A [S and A [ w had to be increased by 2.5V to fit to the new conditions.
power supply of

After these changings the simulation result did not differ much of the simulation
results of the dual-voltage supplied opamp. I.e. the AC-plot looked still different
from the plot presented in [1] probably because other models and other values for
21

the resistors R1 and R2 were used.

3.3.1

Estimation of the main parameters of the level 49 models

The cadence design tool uses by default BSIM3v3 Level 49 models of a 0.8~

n-well process. These models describe the real behavior of the electronic devices
quite good but for hand calculations they are far too complicated. (see appendix
A) Thus, I estimated the main parameters of the level 49 models to get some
values to use for rough hand calculations. Therefore the plot of the drain current
for different values of the gate-source voltage

Aa

and the basic equation for the

drain current of a MOS transistor are used. The drain current of a MOS transistor
in the linear region is given by

X
Z5   Q %  SAa_
A 6G x A A &

(3.11)

In the saturation region the drain current is calculated as follows

X
w
Z5   Q %  %A
A 6G x  9 A &
Two equations of 3.11 are resolved to deliver KP

(3.12)

w 5Z v
Z
5


(3.13)
Q A a %A  w A   X
When the transistor is in the linear region (i.e. A m : ) two values for the
drain current can be measured for a fixed value of A to get two values for each
Z# and Aa .
To estimate the threshold voltage, 3.11 can be manipulated to

A 6G x >AT A 5Z X A 
Q

(3.14)

Again all needed values can be measured in 3.2.

is estimated with the transistor in saturation. For a fixed gate-source voltage two
22

Id

over

Vds

Symbol
1.25m
1.2m
1.15m
1.1m
1.05m
1m
950u
900u
850u
800u
750u
700u

Result (lin)

Wave
D0:A0:Ids

650u
600u
550u
500u
450u
400u
350u
300u
250u
200u
150u
100u
50u
0
-50u
0

4
5
6
Voltage X (lin) (VOLTS)

Figure 3.2:

23

10

values of the drain current and of the drain-source voltage have to be measured.
Inserting these values in 3.12 gives the ratio

Z#v  9 A
Z# w 9  A w

(3.15)

In a few steps this equation can be modified to give

9


(3.16)
A % A w


Using all these equations I got following parameters for the level 49 models:
NMOS:

PMOS:

 O: r

>O 5r
A 6G x :}d I A A G6 x  :}dJ U A
>:}d:: q >
 :d!::9 r
r

(3.17)

Although the BSIM3v3 level 49 model defines more than 120 parameters it does
not give the values for e.g.

or KP. These values are calculated during the sim-

ulation to take in account the changing conditions they depend on. Nevertheless
the rough values estimated above are quite handy for first hand calculations.

3.3.2

Simulation of the folded-cascode opamp (level 49 models)

With the new values for the most important model parameters I calculated the
single-ended folded-cascode opamp again for the same conditions as specified in

Q E G4 R%R N WYX
and the supply voltage of AE|E U A result in total current of Z6 6G]^  q : : ~
[1] but with a single-voltage supply. The given power dissipation

for the whole opamp. Thus the bias transistors Mn3 and Mn4 have to provide
200~

each because they supply the whole circuit. With 3.3 and the requirement

of having the input currents four times greater than the current through the PMOS
cascode devices the currents are given as

Z#v  Z# w 9 : ~
24

(3.18)

Z#  #Z z >:: ~
#Z   5Z   Z#P  Z# {  Z5  5Z v x  q : ~
The current in the bias transistors Mp3,Mp4 is set by the current source Z5[\4J]Ry and
the bias transistor Mp11. To save a little bit of power, Mp11 is scaled down to

9/O: G6
9/O: G6

of the width of Mp3 or Mp4. Thus, the drain current through Mp11 is also
of the bias transistors currents. Using a modified version of equation 3.12,

the transistors dimensions can be calculated. Here, the effective gate-drive voltage

Aa FF 1 A A 6G x

is assumed to be 0.25V.

4 4 w
X 4  S Aa Z5( 
4 4 A 6G x 

(3.19)

where 4 is the number of the corresponding transistor. The formula is a little bit
simplified by ignoring the channel-length modulation term (i.e.

be zero).
Using 3.19 and a fixed length of

V9d ~ W

is assumed to

the following width were calculated

for the transistors (Table 3.3.2)


Table 3.1: widths of the transistors in ~

Mn1 = 400 Mn2 = 400 Mp3 = 440 Mp4 = 440


Mp5 = 90

Mp6 = 90

Mn7 = 30

Mn9 = 30

Mn10 = 30 Mp11 = 15

Mn8 = 30

Mn12 = 15 Mn13 = 15

The clamp transistors were sized somewhat arbitrarily to the same dimensions
as the bias transistor Mp11 and the widths of the input transistors were not calculated but chosen to a large value of

q : : ~ W

to maximize their transconductance.

Although the bias transistors were calculated to have a width of qq


1

Sometimes this voltage is also referred as

O or  -
25

:~W

I limited

their width to q

:O: ~ W

$
  X  y Z#v dCW

OA

(3.20)

Thus, the opamps unity-gain frequency came to

or better

1324J687  $,  >O d 9;: { 'Hg&


i ,$

0;13254J687 , i  >dJO<>=@?

(3.21)

To place a zero at a frequency 1.2 times higher than the unity-gain frequency, a
so called lead resistor

j `

can be used in series with the load capacitance

i 

. Its

value is given by

 9d!,9 $,  U O
j `  9 d!  9
i 31 254!687

(3.22)

Finally, the slew-rate is given by

j  #Z  z O:CA ~ 
i

(3.23)

without clamp transistors. When clamp transistors are used the current through
Mp3,Mp4 will be increased to

C: ~

during slew-rate limiting and therefore the

slew-rate will be increased to

z
j #Z i  >CA ~ 
All these values were calculated for a load capacitance of i

(3.24)

 9;: oap

Plots 3.3 and 3.4 show the results of the corresponding simulation.
These results are much closer to the example given in [1]. More important
the values for e.g. the unity-gain frequency

j> I d A ~ 

0/1324J687 C<>=@?

of the simulation meet the calculated values.

26

or the slew-rate

single-ended folded-cascode
Wave
D0:A1:vdb(dbout)

C=10pF

Symbol
80

Volts dB (lin)

60
40
20
0
-20
-40
10

100

1k

10k
100k
Frequency (log) (HERTZ)

1x

10x

100x

1x

10x

100x

1g

phase
Wave
D0:A1:p(vout)

Symbol

180

Volts Phase (lin)

160
140
120
100
80
60

10

100

step response
Wave
D0:A0:v(vout)
D0:A0:v(vin-)

Symbol

1k

10k
100k
Frequency (log) (HERTZ)

1g

(without clamp transistors)

Voltages (lin)

2.8

2.6

2.4

2.2

2
0

200n

400n
600n
Time (lin) (TIME)

800n

1u

Figure 3.3: Frequency plot and step-response of the folded-cascode opamp without clamp transistors
27

single-ended folded-cascode
Wave
D0:A1:vdb(dbout)

C=10pF

Symbol
80

Volts dB (lin)

60
40
20
0
-20
-40
10

100

1k

10k
100k
Frequency (log) (HERTZ)

1x

10x

100x

1x

10x

100x

1g

phase
Wave
D0:A1:p(vout)

Symbol

180

Volts Phase (lin)

160
140
120
100
80
60

10

100

1k

10k
100k
Frequency (log) (HERTZ)

1g

step response
Wave
D0:A0:v(vout)
D0:A0:v(vin-)

Symbol

Voltages (lin)

2.8

2.6

2.4

2.2

2
0

200n

400n
600n
Time (lin) (TIME)

800n

1u

Figure 3.4: Frequency plot and step-response of the folded-cascode opamp with
clamp transistors
28

3.3.3

compensation difficulties

The fully-differential opamp is specified to drive a capacitive load of

i   Uoap

thus the next step was to simulate the single-ended folded-cascode opamp with
this load value. In theory using a smaller

i 

results in a higher unity-gain fre-

quency and a better slew-rate because of 3.7 and 3.9. Thus, the unity-gain frequency should rise to
of

j> q A ~ 

0/1324J687  U dC<>=@?

and the slew-rate should reach a value

(with clamp transistors). But on the other hand the opamp might

get less stable because it is compensated only by its load capacitance. This is seen
in plot 3.5.
The step response shows a legible overshoot which points to a an undercompensation of the opamp although the frequency plot looks ok. Certainly, the
slew-rate did not double as it is supposed to be in theory but it raised a little bit

0/1324J687  qC dJ<=@?
but on the other hand the phase margin has dropped to PM=56  . Obviously, this
to

j I d A ~  .

The unity-gain frequency now reaches

opamp is not compensated enough with a load capacitance of 5pF so that the second poles affect the opamps behaviour.
The compensation can not be done just using a larger load capacitance because the capacitive load is specified to

i   U3o0

. Unfortunately this would

be the usual and easiest method to compensate a folded-cascode opamp which is


supposed to be stable and solid as a rock, anyway. As mentioned in 3.2.1, the
folded-cascode opamp has some second poles due to the impedance and parasitic
capacitances at the sources of the PMOS cascode transistors. Therefore a smaller
impedance at these nodes decreases the RC-time constant and moves these second poles to higher frequencies. As a result the opamp becomes more stable. To
decrease the impedance at the cascode transistors sources, the current through the
cascode devices can be increased to a level equal to the current in the input transistors. Thus, for a given power dissipation, the input transistor will get a smaller
29

single-ended folded-cascode
Wave
D0:A1:vdb(dbout)

C=5pF

Symbol
80

Volts dB (lin)

60
40
20
0
-20
-40
10

100

1k

10k
100k
Frequency (log) (HERTZ)

1x

10x

100x

1x

10x

100x

1g

phase
Wave
D0:A1:p(vout)

Symbol

180

Volts Phase (lin)

160
140
120
100
80
60
40
10

100

1k

10k
100k
Frequency (log) (HERTZ)

1g

step response
Wave
D0:A0:v(vout)
D0:A0:v(vin-)

Symbol
3

Voltages (lin)

2.8

2.6

2.4

2.2

2
0

200n

400n
600n
Time (lin) (TIME)

800n

1u

Figure 3.5: Frequency plot and step-response of the folded-cascode opamp with a

i   Uoap

30

current and their transconductance will decrease, too. Unfortunately, this results
in a smaller open-loop gain and less noise-rejection.

3.3.4

The feedback resistors

Obviously, the closed-loop feedback causes trouble for the opamp compensation
(see step response) because in the open-loop configuration the opamp seems to be
stable (3.5). The phase margin is a little bit too low (PM=56  ) but this can not be
the only reason for the overshooting. Furthermore, the step response plot shows
that the opamp does not achieve a gain of one although the feedback resistors
R1 and R2 are both the same (j9LjT9;:C} ). For larger values of these

resistors (e.g. j9jT@9;::} ), the gain gets closer to its ideal value of one
but the overshoot increases, too. The other way round, the gain drops to very low

values but the overshoot is gone for low resistor values (j9jT9;} ). The
opamp behaves like this because the feedback resistor is connected between the

opamps output and its negative input node which is tied to virtual ground (or in
this case to virtual analog ground i.e. 2.5V). Thus, the feedback resistor acts as
a load. For a small feedback resistor the opamp can not provide enough output
current to drive the low impedance at the output, so that the gain breaks down. In
spite, large feedback resistors do not have such high current requirements to the
output but large resistors have quite large parasitic capacitances which cause the
overshooting.
One method to avoid parasitic capacitances introduced by large resistors without loosing gain is to place a buffer between the output node of the opamp and the
feedback resistor R2. The idea is to use small feedback resistors which have only
low parasitic capacitances. The buffer ensures that the gain does not break down,
i.e. the opamp needs to provide only a little current to drive the buffer instead
of driving the feedback resistor directly. For test purposes a voltage-controlled
31

voltage source (VCVS) can be used as an ideal buffer. Figure 3.6 shows the block
diagram of the opamp with the VCVS in the feedback loop.

Figure 3.6: Block diagram of the opamp with a VCVS in the feedback loop

Figure 3.7 shows the simulation result of the opamp with the ideal buffer between output node and feedback resistor R2. The step-response was simulated

#9 :C} (i.e. unity gain) and the ac-plots were done with a
O:gHh ). Unfortunately, the overshoot
gain of ten (j99/}jTY9#:C}
with resistor values of

got even worse so that the step-response now shows a ringing. Nevertheless, the
gain now achieves its ideal value and the ideal buffer can not harm the operation of
the opamp. Thus, I keep the ideal buffer in the circuit to debug the opamp further.

32

single-ended folded-cascode opamp with VCVS in feedback loop


Wave
D0:A1:vdb(dbout)

Symbol

20

Volts dB (lin)

-20

-40

10

100

1k

10k
100k
Frequency (log) (HERTZ)

1x

10x

100x

1x

10x

100x

1g

phase
Wave
D0:A1:p(vout)

Symbol

Volts Phase (lin)

150

100

50

10

100

1k

step response
Wave
D0:A0:v(vout)
D0:A0:v(vin-)

10k
100k
Frequency (log) (HERTZ)

1g

VCVS in feedback loop

3.2

Symbol

Voltages (lin)

2.8
2.6
2.4
2.2
2
0

200n

400n
600n
Time (lin) (TIME)

800n

1u

Figure 3.7: Frequency plots (gain and phase) and step-response of the foldedcascode opamp with VCVS in feedback loop
33

3.3.5

down-sizing the transistors

As already mentioned in 3.2.1 there are second poles due to the RC-time-constant
of the impedance and parasitic capacitances at the sources of the cascode transistors. After some simulations in which I used simple level 1 models for different transistors I was convinced that, these second poles affect my opamp. When
the input, the bias and the cascode transistors (i.e. Mn1..Mp6) were replaced by
level 1 model transistors (i.e. transistors with no parasitic capacitances), the stepresponse did not show any overshooting. Thus the parasitic capacitances at the
sources of the PMOS cascode devices must be decreased. The parasitic capacitances at this node are mainly the drain-to-bulk and the drain-to-gate capacitances
of the input and bias tansistors and the gate-source capacitances of the cascode
transistors. To decrease these capacitances substantially the only way is to reduce
the sizes of the corresponding transistors. Besides, smaller input transistors take
less current, so that the current in the cascode transistors is increased and as a result their impedance is decreased. This is also beneficial to move the second poles
to higher frequencies. Thus, I tried values of U

:~W

and

9;:: ~ W

for the widths of

the input transistors (Mn1,Mn2) respectively the bias transistors (Mp3,Mp4). (I


was a little bit surprised that the drain currents of Mn1..Mp4 were not reduced very
much, although these transistors are far smaller than the sizes I calculated.) Using
this values, I got rid of the ringing of the output voltage but the step-response still
showed a negative overshoot.
This negative overshoot is caused by the transistors Mn7, Mn9 and Mn10 of
the cascode current mirror because they cause a pole due to their parasitic capacitances. In the fully-differential opamp this current-mirror is replaced by cascode
current sinks to break the differential to single-ended conversion. I.e. the Mn9
and Mn10 are not biased by the node between Mp5 and Mn7 anymore but by
the output of the CMFB-circuit. To get rid of the poles caused by the current
34

mirror, the mirror can be replaced by current sinks as in the fully-differential design. Certainly, then the cascode current sinks Mn9 and Mn10 have to be biased
by an additional bias transistor (Mn14). Usually, a current mirror is preferred to
single current sinks, because the break of the mirror which does the differentialto-single-ended conversion results in a by 6dB reduced gain. Nevertheless, the
design with the biased current sinks is closer to the fully-differential opamp. Table 3.3.5 shows the values of the widths of each transistor in the circuit. Mn14 is
the bias transistor for the current sinks Mn9 and Mn10. Its widths is chosen to bias
Mn9 and Mn10 so, that they take about the same current as in the current-mirror
design. To maximize the performance of the circuit, the widths of the current
sinks were increased to

9;:: ~ W

. This results in a greater power consumption but

it was necessary to decrease the linear settling time to a value of

R 686 N 9;:: P

which is required be able to run the opamp with up to 10MHz. Finally, the clamp
transistors (Mn12,Mn13) do not affect the circuit anymore, because of the high
bias currents the circuit is supplied with. The bias transistors (Mp3,Mp4) now get

Z5[\48]^R| :: ~

Z[\48]R w CO: ~
the bias transistor for the cascode current sinks gets Z5[\4J]R  q : ~ .
, the differential input pair is supplied with

Table 3.2: widths of the transistors in ~

Mn1 = 50

Mn2 = 50

Mp3 = 100

Mp4 = 100

Mp5 = 90

Mp6 = 90

Mn7 = 30

Mn8 = 30

Mn9 = 30

Mn10 = 30

Mp11 = 100

(Mn12 = 15) (Mn13 = 15)

and

Mn14 = 30

Figure 3.8 shows the schematic of the single-ended opamp described above.
To buffer the feedback resistor a VCVS is used. Later (in the fully-differential
design) this ideal device will be replaced by a real buffer.
The plot 3.9 presents the simulation results of this opamp. As the step-response
35

Figure 3.8: schematic of the single-ended opamp

(the pulse rate) shows this circuit should be able to cope with the specified speed
requirements. Thus, the folded cascode opamp can be based on this circuit.

36

single-ended opamp
Wave
D0:A1:vdb(dbout)

Symbol

20

Volts dB (lin)

-20

-40

10

100

1k

10k
100k
Frequency (log) (HERTZ)

1x

10x

100x

1x

10x

100x

1g

phase
Wave
D0:A1:p(vout)

Symbol

Volts Phase (lin)

150

100

50

10

100

1k

10k
100k
Frequency (log) (HERTZ)

1g

step response
Wave
D0:A0:v(vout)
D0:A0:v(vin-)

Symbol

3.5

Voltages (lin)

2.5

1.5
0

200n

400n

600n

800n
1u
Time (lin) (TIME)

1.2u

1.4u

1.6u

Figure 3.9: simulation results of the final version folded-cascode opamp

37

Chapter 4
The CMFB
4.1

A continuous-time CMFB

The common-mode feedback circuit (CMFB) is essential to build a fully-differential


opamp because without the CMFB loop the differential output could not be realized. The CMFB circuit regards the output voltages of the fully-differential opamp
to generate a control voltage which biases the output stage of the opamp. (I.e.
the control voltage is connected to the gates of the cascode current-sinks of the
opamp.) Ideally, the CMFB should establish a common-mode output voltage (i.e.
the average of the positive and negative output voltage:

A a`b  r3O8w r3O

should be placed exactly halfway between both power supply voltages. To build
a general-purpose fully-differential opamp a general-purpose CMFB is needed.
Thus, a switched-capacitor (SC) CMFB can not be used, because this circuit requires a clock signal. Therefore, a continuous-time (CT) CMFB is to prefer, because it can be used in any environment and does not need a clock signal. Unfortunately, continuous-time CMFBs have some disadvantages compared to SC
CMFBs, as already mentioned in 2.5. These different drawbacks will be discussed
in this chapter.
38

4.2

The ideal common-mode feedback circuit

To get started with a fully-differential opamp an ideal CMFB circuit can be taken.
This circuit can not be build in reality because it consists of ideal devices. Nevertheless, this circuit might be useful to simulate a fully-differential opamp under
ideal conditions. Therefore, it can be tested how the opamp behaves when it is not
limited by the CMFB circuit because usually, the (real) CMFB circuit is the major limitation for a fully-differential opamp. Figure 4.1 shows a fully differential

Figure 4.1: a fully differential folded-cascode opamp with ideal CMFB circuit

folded-cascode opamp with an ideal CMFB circuit. The ideal CMFB loop consists
of four voltage-controlled voltage-sources (VCVS). The two VCVS connected to
the outputs of the opamp just work as ideal buffers to reduce the load effect of
the following resistors which act as a simple voltage divider. The common-mode
voltage of the outputs which is generated by the voltage divider (at node Vcm)
is connected to the third VCVS which compares the common-mode voltage to a
reference voltage of 2.5V. The difference between the common-mode and the reference voltage (the error-voltage) is given to the last VCVS. Here the error-voltage
39

is added to a fixed voltage Vgs. This voltage must have a value according to
the bias voltage which is needed to drive the transistors Mn9 and Mn10 in their
saturated region. As a result the control voltage A_3

| lA_. , AT$

will drive

the current sinks so that the common-mode output voltage always equals the reference voltage of 2.5V. The accuracy how close the output common-mode voltage
will get to its ideal value depends on the gain of the CMFB. Thus, using a high
gain of the last VCVS will increase the accuracy of the circuit.

4.3

A Differential Difference Amplifier (DDA) CMFB

My first attempt to build a continuous-time CMFB circuit is shown in figure 4.2.


Figure 4.2 shows only the CMFB and its bias circuit without the opamp. This

Figure 4.2: a DDA CMFB circuit

40

CMFB loop works quite similar to a differential input pair: Actually, it consists
of two interlaced differential input pairs. Each of the opamps output voltages
is connected to the gate of an identical PMOS transistor (Mp14,Mp15, the first
differential input pair). When a differential output signal is applied to the CMFBinput transistors (Mp14,Mp15), usually, one output voltage rises by certain value
while the other output voltage is decreased by this value. E.g. when the positive output voltage

A 136

rises by

the current through Mp14 will decrease

but at the same time the negative output voltage

Aa 136 D

is decreased by

and

thus the current through Mp15 will increase. Therefore, the total current through
the transistor pair stays the same, even when large transient voltages are present.
When both output voltages rise at the same time, i.e. the output common-mode
voltage rises, the total current through Mp14 and Mp15 decreases (e.g. by

As a result, the current through the transistor pair Mp17,Mp17b does not change
either and thus the control voltage does not change. On the other hand the current
through the transistors Mp17 and Mp17b increases by Z because both transistor
pairs are supplied by the same current source. Thus, the current at node Vcntr is
decreased by 

because Z is mirrored in the current mirror (Mn18,Mn19) and

therefore, the voltage at node Vcntr is increased. It should be mentioned that


the transistors Mp17,Mp17b are identical to the CMFB-input transistors. Mp17
and Mp17b are connected in parallel to achieve a better matching than a single
transistor with twice the width of Mp17 could do. The parallel connection of the
CMFB-input pair and the transistor(s) Mp17(b) build the second differential input pair. Therefore, the average voltage applied to the CMFB-input transistors
is compared to the reference voltage applied to Mp17(b). As a result the control
voltage 268 will keep the output common-mode voltage at the same level as the
reference voltage (i.e. 2.5V) on condition that the transistors in the CMFB are
sized correctly.

41

In reality the circuit suffers of the non-linearity of the CMFB-input transistors.

E.g. when a voltage of Aa

136  A

is applied to Mp14 and a voltage of Aa

16 A

is given to Mp15, the differences of the currents through Mp14 and Mp15 are
not equal (Z,

z  Z Z Z/  Z  w Z

with:

Y w ).

Therefore, the

voltage at the drains of the differential input pair (node Vcm) does not stay
constant, although the average output voltage stays constant. Even very small
voltage changes (a few ~

) have a big effect (several mV) on the control voltage

because of the amplification in the current mirror.

4.4

Tricks to improve the DDA CMFB

There are a few tricks to reduce the effect of the non-linearity of a Differential
Difference Amplifier. Firstly, the CMFB-input transistors should have a large
gate-source voltage. This allows them to work linear for larger differential signals.
Another method is to place so called degeneration resistors between the sources
of the input transistor and the bias transistor Mp16. To keep the circuit matched,
such resistors also have to be placed in series to the transistors Mp17 and Mp17b.
The degeneration resistors also should serve the purpose to allow larger differential input signals by avoiding that all the current is directed to one side of the
CMFB input pair.
Breaking the connection of the current-mirror, i.e. using single current sinks
instead of the current-mirror, cuts the gain of the CMFB loop by 6dB. Therefore
the changing of the control voltage is reduced because the tiny changes at node
Vcm are not amplified by the current-mirror anymore.
Another approach to get a DDA CMFB working is the use of a replica of the
fully-differential opamp to provide the output voltages to the CMFB. The replica
can be run with smaller differential signals according to the CMFB which works

42

more linear for small signal swings. Therefore, the CMFB can control both, the
opamp and its replica. The replica has to be matched exactly to the opamp to ensure that both work under the same conditions. Unfortunately, you can not always
ensure that the opamp sees the same load as the replica. Furthermore, the output
voltages of the opamp might affect the replica because they are connected via the
feedback resistors to the opamps inputs, and therefore, they are also connected
(via the input resistors) to the inputs of the replica. Besides, using a replica the
space needed on a chip is doubled.

Figure 4.3: DDA CMFB circuit with source degeneration

Figure 4.3 shows the DDA CMFB with degeneration resistors and single current sinks instead of the current-mirror.
Although I tried all the tricks mentioned above, I did not achieve a satisfying
result using the DDA CMFB. The non-linearities were still too strong. The gatesource voltage of the CMFB-input transistors have a value of 2.495V which is
43

quite close to the theoretical maximum of 2.5V. Using source-degeneration with

j  ::C} the input transistor still were not able to cope


with signal swings of 9/AHB#D,B . The maximum signal swing got better using resistor
values of j  9/<> but such large resistors are not acceptable. Even when
resistor values of

the current-mirror was replaced by single current sinks the maximum possible
signal swing was not satisfying using the source generated DDA CMFB. Thus, I
designed a different CMFB circuit.

4.5

The Resistor Averaged CMFB

To get rid of the non-linearity problems caused by the input transistors, I replaced
the input pair by a single transistor. The common-mode output voltage is now
generated by a voltage divider consisting of two resistors. This CMFB should be
able to cope with large input signal swings because resistors are linear devices.
It should be mentioned that buffers between the opamps output and the averaging resistors of the CMFB are essential to relieve the opamp. These buffers are
not shown in figure 4.4. Certainly, the resistor averaged CMFB has less gain than
the DDA CMFB, because the generation of the common-mode voltage is done by
passive devices instead of active devices as in the DDA CMFB. A reduced gain
results in less accuracy of the resulting output common-mode voltage but on the
other hand the phase margin of the CMFB loop is increased. This is quite useful
to get the whole system stable as it will be seen in 6.2.

44

Figure 4.4: Resistor averaged CMFB circuit

45

Chapter 5
The Buffer
5.1

Why a buffer is needed

Unfortunately the opamp has only a very low gain when small resistor values in
the feedback loop are used. The gain does not follow the usual formula

 w

anymore. To achieve a high gain either high resistor values have to be used or
a buffer must be placed between the output node and the feedback resistor R2.
The former version is easier to implement but it has the disadvantage, that large
resistors have quite large parasitic capacitances which may affect the input of the
opamp. Besides the feedback resistor acts also as a load to the opamp because it
is connected between the output and the negative input. This input has ideally the
same potential as the positive input which is usually connected to analog ground
for a single ended opamp.
Furthermore, a buffer is needed between the outputs of the opamp and the
CMFB circuit. Otherwise the CMFB would act as a (quite large) additional load.
One method would be to use a simple opamp as an unity-gain buffer. I.e. the
output is connected directly to the negative input of the opamp. Such a buffer
works fine, but it has the drawbacks that it has usually a high power consumption.
46

Furthermore, using an opamp in the feedback loop of the folded-cascode opamp


would cause difficulties in the compensation of the whole system. Thus another
kind of buffer is to prefer.

5.2

The diode-prebiased source follower

Figure 5.1 shows a so called diode-prebiased source follower with resistive frequency compensation. This buffer, first presented in [11] by Marius Neag and

Figure 5.1: A diode-prebiased source follower with resistive frequency compensation

Oliver McCarthy, combines the benefits of an open-loop design and a closed-loop


structure. Thus, the buffer is based on a complementary source follower (openloop structure) but it uses an additional feedback circuitry. Therefore, this buffer
should be able to run at high frequencies, without causing stability problems. Fur47

thermore, it should achieve a better accuracy and linearity than pure open-loop
design can do.
In figure 5.1 Mxi1 and Mxi2 are the diode-connected transistors which bias the
source-followers Mxo1 and Mxo2. When they were not biased by the diodes, the
source-followers would have an offset of their gate-source voltage. Transistors
Mxo3,4 present the common-source output stage. Together with Mxo1,2 these
transistors form an opamp with unity feedback loop. This results in a lower output
impedance while the output stage allows to provide more power to the load. To
minimize the offset of the buffer (i.e. the voltage difference between the input and
the output of the buffer) the currents through Mxi1,2 and Mxo1,2 should be equal.
The current levels through the different signal paths can be adjusted by the sizes
of the bias transistors Mxb1..Mxb6.
Table 5.2 shows the calculated sizes for the transistors, using a current source

of

Z5[\48]^R|  9 e : ~

and compensation resistors of

j S B 9d!}

Table 5.1: widths and lengths of the transistors in ~


Mxb1 = 165/1.6

Mxb2 = 49.9/1.6

Mxb5 = 330/o.8

Mxb6 = 98.8/o.8

Mxo1 = 499/o.8 Mxo2 = 1650/o.8

Mxb3 = 165/1.6

. Figure 5.2

Mxb4 = 49.9/1.6

Mn=xi1 = 499/o.8 Mxi2 = 1650/o.8


Mxo3 = 1650/o.8

Mxo4 = 499/o.8

Mxd = 100/1.6

shows the gain and phase plots and the step response of the diode-prebiased source
follower with resistive frequency compensation. Obviously, the buffer causes a
little offset and a gain error as it is seen in the step response. The offset equals

Aa F3F  WYA
M 9 P .

and the gain error is

-  

48

. The settling time equals

buffer with resistive frequency compensation


Wave
D0:A1:vdb(dbout)

Symbol

-5

Volts dB (lin)

-10

-15

-20

-25

-30
10

100

1k

10k
100k
Frequency (log) (HERTZ)

1x

10x

100x

1x

10x

100x

1g

phase
Wave
D0:A1:p(out)

Symbol
150

Volts Phase (lin)

100
50
0
-50
-100
-150

10

100

1k

10k
100k
Frequency (log) (HERTZ)

1g

step response
Wave
D0:A0:v(out)
D0:A0:v(in)

Symbol

3.5

Voltages (lin)

2.5

1.5
0

50n

100n

150n

200n

250n 300n 350n


Time (lin) (TIME)

400n

450n

500n

550n

600n

Figure 5.2: gain, phase and step response of the complementary source-follower

49

5.3

Gain error and offset

The gain error and offset of the buffer can cause trouble, when the buffer is placed
into the feedback loop of the folded-cascode opamp. Thus, the gain of the whole
opamp circuit does not follow the equation

where
and

 w



R 7R 9  
R7R is the gain of the whole circuit, 

anymore, but is given by


(5.1)
is the gain of the opamp itself

is the gain of the buffer in the feedback loop. The gain error of the buffer

results directly in a gain error of the system. For a gain error of the buffer of
+5% the system gets a gain error of +11% but for a buffer gain error of -5% the
systems gain error is -9% (assuming a gain of 1 for the opamp and the buffer).
Furthermore, it should be mentioned, that a positive offset at the buffer results in
a negative offset of the whole system (due to the inverting opamp).
Figure 5.3 shows the block diagram of an opamp with a buffer in the feedback
loop.

50

Figure 5.3: Block diagram of an opamp with buffered feedback loop

51

Chapter 6
The fully-differential Opamp
6.1

The fully-differential folded-cascode opamp

The fully-differential opamp is based on the single-ended folded-cascode opamp


presented in 3.3.5. To use that opamp as a fully-differential opamp some changes
have to be made. The cascode current sinks must not be biased by a fixed bias
current provided by transistor Mn14. Instead they have to be biased dynamically
by a CMFB circuit (e.g. the CMFB loop described in 4.5). The use of a resistor
averaged CMFB circuit requires buffers between the output of the opamp and the
CMFB loop. Buffers are also needed in the feedback loops of the opamp. For
both purposes the diode-prebiased source-follower presented in 5.2 can be used.
Unfortunately, it is a little bit more difficult to make a single-ended opamp
running as a fully-differential one. It is not just connecting a single-ended opamp
with a CMFB circuit. The CMFB loop has to meet the opamps speed requirements
and must not destabilize the system.

52

6.2

The CMFB loop

My first attempt to simulate the fully-differential opamp with the resistor averaged
CMFB circuit showed large overshoots in the step-response plot. Obviously, the
system was not compensated enough although the corresponding single-ended
opamp was and still ideal buffers were used. Thus, the CMFB loop itself was not
compensated well. Its phase margin was too low. To stabilize the system the gain
in the CMFB loop should be decreased to achieve a better phase margin. It has
to be mentioned that the increased phase margin will be achieved on the expense
of accuracy. I.e. the output common-mode voltage will not meet its ideal value
of 2.5V as exactly as it could be achieved with a high gain CMFB circuit. This
problem is one of the major difficulties in designing a continuous time CMFB.
The simplest method to cut the gain of the CMFB circuit is to break the connection of the current mirror. The (ex-current-mirror) transistor (M4) which is
driving the control voltage could be biased by another transistor with a fixed bias
current instead. The transistor (M3) at the other side of the current mirror might
be connected as a diode or it might be replaced by a resistor with a corresponding
value to the transistor. Another possibility is to bias the ex-current-mirror transistor pair with a fixed bias current. This circuit is shown in 6.1. The corresponding
simulation results are presented in 6.2. The simulation results show, that the circuit still is not well compensated. There are still overshoots and the circuit needs
far too long to settle although still ideal buffers are used. On the other hand the
plot shows that the calculated output common-mode voltage A

a`b  r3O8Cw r3O

is still quite accurate.


Another method to cut the gain of the CMFB loop is to apply a smaller voltage
to the CMFB circuit. This can be done using a voltage-divider at the input of the
CMFB circuit. Certainly, the reference voltage has to be adapted to the same
voltage as applied to the input transistor. When very small input voltages are
53

Figure 6.1: fully-differential opamp with resistor averaged CMFB circuit

54

fully-differential opamp with ideal buffers


Wave

Symbol

D0:A0:v(vout+)
D0:A0:v(vout-)

2.8
Voltages (lin)

D0:A0:v(vin+)
D0:A0:v(vin-)

2.6

2.4

2.2

200n

400n
600n
Time (lin) (TIME)

800n

1u

800n

1u

800n

1u

Vocm
Wave
D0:A0:Vocm

Symbol

2.54
2.52

Result (lin)

2.5
2.48
2.46
2.44
2.42
2.4

200n

400n
600n
Time (lin) (TIME)

Vdiff
Wave
D0:A0:Vdiff

Symbol

Result (lin)

500m

-500m

-1
0

200n

400n
600n
Time (lin) (TIME)

Figure 6.2: step response, output common-mode voltage and differential step response
55

used to achieve a small gain, the generated control voltage might be to small to
drive the current sinks in the opamp. Therefore, it is useful to add the small
dynamic control voltage to a fixed bias voltage which is near to the voltage needed
to drive the current sink transistors. Thus the sum of the fixed bias voltage and
the dynamic control voltage generated by the CMFB loop, is large enough to
control the opamp, but the gain in the CMFB loop might be quite small. The
fixed bias voltage should be generated by a replica of the opamp to be able to
adapt on the outer conditions like temperature drift or supply voltage variation. To
add the fixed and the dynamic voltage, two current sinks (Mn9b,Mn10b) can be
placed in parallel to Mn9 and Mn10. The current which is taken by these devices
can be adjusted by sizing them to the right width. Thus, when the fixed voltage
should provide 9/10 of the total control voltage, the corresponding transistors (e.g.
Mn9,10) must have a width of about 9/10 of the total width while the transistors
Mn9b,10b must have a width of 1/10. The dynamic voltage will be applied to
these transistors.
When I experimented with different possibilities to add two voltages I found
an unconventional method to realize a resistor generated CMFB circuit. (Figure
6.3 On my way to cut the gain of the CMFB loop I simplified that circuit step
by step. At first I replaced transistor M3 by a resistor while M4 was biased by a
fixed current, then I replaced transistor M4 as well. Thus, the gain in the CMFB
circuit was minimized, but now the control voltage was too small. Therefore, the
control voltage had to be added to a fixed bias voltage. Using a bias transistor as
for biasing the single-ended opamp, can not work. If the gate and the drain are
connected both to the control voltage, the transistor would only work as a diode to
ground. When the transistors drain is only connected to the gates of the transistors
which are to be controlled while the gate is connected to the output of the CMFB
circuit, the transistor might tie down the gate-source voltage of Mn9,10 to ground

56

only. Connecting a positive voltage to the source of the control transistor, the
transistor works in a highly resistive region. Thus, this transistor acts as a voltage
controlled resistor. Therefore, the CMFB circuit needs only a small gain to drive
the control transistor, which controls the opamp.

Figure 6.3: fully-differential opamp with unconventional resistor averaged CMFB


circuit

Figure 6.4 shows the step response, the output common-mode voltage and
the differential output voltage. The circuit is able to operate up to frequencies

A  9/AHB#D,B i.e. the opamp can


provide a differential peak-to-peak voltage of AACB;D,B#D&E 4GF3F . The linear settling
time has a value of M  ICU P . For lower frequencies the opamp works even for
r
larger differential signals. The slew-rate downwards equals j9 I d R and

r
the slew-rate upwards is given as j>>d e R

of 10MHz for a peak-to-peak input voltage of

Figure 6.5 shows the frequency plots (gain and phase) of the fully-differential

;0 13254J687 &d U <=@?


and PM = 80.5  for a gain configuration of -10 and 0/13254!687  I d!<>=@? and PM
w wyxy
= 77.3  for a gain of -20 (i.e.  ). Unfortunately, the power consumption
is far too large Q E 4GR%R  q :WYX due to the large bias currents taken to make the
opamp. The unity-gain frequency and the phase margin are

57

fully-differential folded-cascode opamp


Wave

Symbol

D0:A0:v(vin+)
D0:A0:v(vin-)
2.8
Voltages (lin)

D0:A0:v(vout+)
D0:A0:v(vout-)

2.6

2.4

2.2

500n

1u

1.5u

2u
2.5u
Time (lin) (TIME)

3u

3.5u

4u

3u

3.5u

4u

3u

3.5u

4u

Vocm
Wave
D0:A0:Vocm

Symbol
2.56

Result (lin)

2.54

2.52

2.5

2.48

2.46
0

500n

1u

1.5u

2u
2.5u
Time (lin) (TIME)

Vdiff
Wave
D0:A0:Vdiff

Symbol

Result (lin)

500m

-500m

-1

500n

1u

1.5u

2u
2.5u
Time (lin) (TIME)

Figure 6.4: step response, output common-mode voltage and differential step response
58

fully-differential folded-cascode opamp


Wave
D0:A1:vdb(dboutp)
D0:A1:vdb(dboutn)

Symbol
20

10

Volts dB (lin)

-10

-20

-30

-40

-50

10

100

1k

10k
100k
Frequency (log) (HERTZ)

1x

10x

100x

1x

10x

100x

1g

phase
Symbol

150

100

50
Volts Phase (lin)

Wave
D0:A1:p(vout+)
D0:A1:p(vout-)

-50

-100

-150

10

100

1k

10k
100k
Frequency (log) (HERTZ)

Figure 6.5: Fully-differential opamp: gain and phase

59

1g

opamp able to operate fast enough. Furthermore, the four buffers in the circuit
and the resistors (especially in the CMFB loop) are quite power-hungry.

60

Chapter 7
Conclusions
Although I did not achieve what I wanted, I learned quite a lot working on this
project. The fully-differential folded-cascode opamp I developed is theoretically
able to operate at frequencies of up to 10MHz for input signals of 9;AHB#D,B . Thus, the

opamp meets the PAL-TV norm and could be used for video applications (as it was
specified). For lower frequencies the opamp can even process larger signals up to

K OAHB#D,B

which equals q

ACB#D,B;D&E 4GF3F . As a result the opamp might also be useful for

some audio applications. Unfortunately, the power consumption is excessive so


that probably nobody would use this opamp. Furthermore, the circuit is supposed
not to work. Anyway, there are still lots of possibilities how this circuit could be
improved, although I could not realize them yet, because it took me quite long to
compensate the folded-cascode opamp, which is supposed to be solid as a rock.
Nevertheless, I am still interested in the field of circuit design and I would like
to work in that area, although it is often not an easy job to do. My respect to all
analog IC designer. Finally, I made a lot of new experiences working on the topic
of a fully-differential opamp.

61

Appendix A
BSIM3v3 Level 49 models
A.0.1

The NMOS transistor model

.include /usr/local/ee4408/hspice/cux/modn.mod
.model modn nmos level=49
* ----------------------------------------------------------********************* simulation parameters ******************
* ----------------------------------------------------------* format

: hspice

* model

: mos bsim3v3

* process

: cu[beqwavp]

* extracted : cue 41667; 1998-08; ese(487)


* doc#

: 9933011 rev_b

* created

: 1998-11-17

* -----------------------------------------------------------

62

typical mean condition

* ----------------------------------------------------------*
*

*** flags ***

+mobmod =1.000e+00 capmod =2.000e+00


*

*** threshold voltage related model parameters ***

+k1

=1.057e+00

+k2

=-1.23e-01 k3

=6.535e+00 k3b

+nch

=9.114e+16 vth0

=8.481e-01

+voff

=-1.16e-01 dvt0

=3.561e+00 dvt1

+dvt2

=-2.50e-01 keta

=-4.48e-02

=-2.02e+00

=8.652e-01

+pscbe1 =3.616e+08 pscbe2 =1.020e-05


+dvt0w
*

=-2.98e+00 dvt1w

=1.000e-12 ub

+u0

=4.269e+02

+dsub

=-9.24e-03

*** mobility related model parameters ***

+ua

=1.306e+06 dvt2w

=1.709e-18 uc

=-3.60e-11

*** subthreshold related parameters ***


=5.000e-01 eta0

=1.008e-02 etab

=-1.72e-02

+nfactor=6.529e-01
*
+em

*** saturation related parameters ***


=4.100e+07 pclm

=9.549e-01

+pdiblc1=2.750e-02 pdiblc2=1.069e-03 drout

=3.510e-01

+a0

=9.550e-01 a1

=0.000e+00 a2

=1.000e+00

+pvag

=0.000e+00 vsat

=8.665e+04 ags

=1.785e-01

+b0

=2.652e-07 b1

=0.000e+00 delta

=1.000e-02

+pdiblcb=2.306e-01

63

*** geometry modulation related parameters ***

+w0

=3.151e-08 dlc

=1.449e-07

+dwc

=-8.94e-09 dwb

=0.000e+00 dwg

=0.000e+00

+ll

=0.000e+00 lw

=0.000e+00 lwl

=0.000e+00

+lln

=1.000e+00 lwn

=1.000e+00 wl

=0.000e+00

+ww

=0.000e+00 wwl

=0.000e+00 wln

=1.000e+00

+wwn

=1.000e+00

*** temperature effect parameters ***

+at

=3.300e+04 ute

=-1.90e+00

+kt1

=-4.20e-01 kt2

=2.200e-02 kt1l

=0.000e+00

+ua1

=0.000e+00 ub1

=0.000e+00 uc1

=0.000e+00

+prt

=0.000e+00

*** overlap capacitance related and dynamic model


parameters

***

+cgdo

=3.400e-10 cgso

=3.400e-10 cgbo

+cgdl

=0.000e+00 cgsl

=0.000e+00 ckappa =6.000e-01

+cf

=0.000e+00 elm

=5.000e+00

+xpart

=1.000e+00 clc

=1.000e-15 cle

=1.300e-10

=6.000e-01

*** parasitic resistance and capacitance related


model parameters ***

+rdsw

=1.687e+03

+cdsc

=0.000e+00 cdscb

=0.000e+00 cdscd

=0.000e+00

+prwb

=0.000e+00 prwg

=0.000e+00 cit

=2.234e-04

*** process and parameters extraction related model


parameters ***

+tox

=1.270e-08 ngate

+nlx

=1.000e-10

=0.000e+00

64

+xl

=0.000e+00 xw

=0.000e+00

*** substrate current related model parameters ***

+alpha0 =0.000e+00 beta0


*

=3.000e+01

*** noise effect related model parameters ***

+af

=1.343e+00 kf

=6.896e-27 ef

=1.000e+00

+noia

=1.000e+20 noib

=5.000e+04 noic

=-1.40e-12

+nlev

=0

*** common extrinsic model parameters ***

+acm

=2

+rd

=0.000e+00 rs

=0.000e+00 rsh

+rdc

=0.000e+00 rsc

=0.000e+00

+lint

=1.449e-07

+ldif

=0.000e+00 hdif

=8.000e-07 wmlt

+lmlt

=1.000e+00 xj

=3.000e-07

+js

=2.000e-05 jsw

=0.000e+00 is

+n

=1.000e+00 nds

=1000. vnds

+cbd

=0.000e+00 cbs

=0.000e+00 cj

+cjsw

=4.300e-10 fc

=0.000e+00

+mj

=4.400e-01 mjsw

=2.500e-01 tt

+pb

=8.400e-01 php

=9.400e-01

A.0.2

wint

=3.000e+01

=-8.94e-09
=1.000e+00

=0.000e+00
=-1.000e+00
=3.800e-04

=0.000e+00

The PMOS transistor model

* ----------------------------------------------------------.include /usr/local/ee4408/hspice/cux/modp.mod
.model modp pmos level=49
* ----------------------------------------------------65

------********************* simulation parameters ******************


* ----------------------------------------------------------* format

: hspice

* model

: mos bsim3v3

* process

: cu[beqwavp]

* extracted : cue 41667; 1998-08; ese(487)


* doc#

: 9933011 rev_b

* created

: 1998-11-17

* ----------------------------------------------------------*

typical mean condition

* ----------------------------------------------------------*
*

*** flags ***

+mobmod =1.000e+00 capmod =2.000e+00


*

*** threshold voltage related model parameters ***

+k1

=5.626e-01

+k2

=-1.66e-02 k3

=1.485e+01 k3b

+nch

=5.948e+16 vth0

=-7.85e-01

+voff

=-1.12e-01 dvt0

=2.066e+00 dvt1

+dvt2

=-3.99e-02 keta

=-7.67e-03

=-1.40e+00

=5.015e-01

+pscbe1 =5.000e+08 pscbe2 =1.000e-10


+dvt0w
*

=0.000e+00 dvt1w

=0.000e+00 dvt2w

=0.000e+00

*** mobility related model parameters ***

66

+ua

=6.770e-11 ub

+u0

=1.115e+02

=1.040e-18 uc

=-1.16e-10

*** subthreshold related parameters ***

+dsub

=4.379e-01 eta0

=4.843e-02 etab

=-3.50e-05

+nfactor=2.220e-01
*

*** saturation related parameters ***

+em

=4.100e+07 pclm

=1.459e+00

+pdiblc1=5.872e-03 pdiblc2=3.394e-04 drout

=7.861e-02

+a0

=7.522e-01 a1

=0.000e+00 a2

=1.000e+00

+pvag

=0.000e+00 vsat

=9.496e+04 ags

=1.746e-01

+b0

=3.421e-07 b1

=0.000e+00 delta

=1.000e-02

+pdiblcb=-3.18e-01
*

*** geometry modulation related parameters ***

+w0

=7.289e-07 dlc

=9.927e-08

+dwc

=3.878e-08 dwb

=0.000e+00 dwg

=0.000e+00

+ll

=0.000e+00 lw

=0.000e+00 lwl

=0.000e+00

+lln

=1.000e+00 lwn

=1.000e+00 wl

=0.000e+00

+ww

=0.000e+00 wwl

=0.000e+00 wln

=1.000e+00

+wwn

=1.000e+00

*** temperature effect parameters ***

+at

=3.300e+04 ute

=-1.40e+00

+kt1

=-5.70e-01 kt2

=2.200e-02 kt1l

=0.000e+00

+ua1

=0.000e+00 ub1

=0.000e+00 uc1

=0.000e+00

+prt

=0.000e+00

*** overlap capacitance related and dynamic model


parameters

+cgdo

***

=3.400e-10 cgso

=3.400e-10 cgbo

67

=1.300e-10

+cgdl

=0.000e+00 cgsl

=0.000e+00 ckappa =6.000e-01

+cf

=0.000e+00 elm

=5.000e+00

+xpart

=1.000e+00 clc

=1.000e-15 cle

=6.000e-01

*** parasitic resistance and capacitance related


model parameters ***

+rdsw

=3.796e+03

+cdsc

=0.000e+00 cdscb

=0.000e+00 cdscd

=2.171e-04

+prwb

=0.000e+00 prwg

=0.000e+00 cit

=3.231e-04

*** process and parameters extraction related model


parameters ***

+tox

=1.270e-08 ngate

+nlx

=2.784e-07

+xl

=0.000e+00 xw

=0.000e+00

*** substrate current related model parameters ***

+alpha0 =0.000e+00 beta0


*

=0.000e+00

=3.000e+01

*** noise effect related model parameters ***

+af

=1.772e+00 kf

=1.126e-26 ef

=1.000e+00

+noia

=1.000e+20 noib

=5.000e+04 noic

=-1.40e-12

+nlev

=0

*** common extrinsic model parameters ***

+acm

=2

+rd

=0.000e+00 rs

=0.000e+00 rsh

+rdc

=0.000e+00 rsc

=0.000e+00

+lint

=9.927e-08

+ldif

=0.000e+00 hdif

=8.000e-07 wmlt

+lmlt

=1.000e+00 xj

=3.000e-07

+js

=2.000e-05 jsw

=0.000e+00 is

wint

=6.000e+01

=3.878e-08

68

=1.000e+00

=0.000e+00

+n

=1.000e+00 nds

=1000. vnds

+cbd

=0.000e+00 cbs

=0.000e+00 cj

+cjsw

=3.300e-10 fc

=0.000e+00

+mj

=4.400e-01 mjsw

=2.400e-01 tt

+pb

=8.400e-01 php

=9.400e-01

69

=-1.000e+00
=6.000e-04

=0.000e+00

Appendix B
Technical data
0  9;:C<=@?
peak-to-peak input voltage:
A 9/ACB;D,B

maximal operating frequency:

differential peak-to-peak voltage:

linear settling time:

power consumption:

AACB;D,B#D&E 4GF3F .

M  CI U P .
slew-rate downwards: j>9 I d r R

slew-rate upwards: jd e r R

unity-gain frequency 0/13254J687 d U <>=@?
phase margin: PM = 77.3
Q E 4GR%R  q :WYX

For lower frequencies the opamp works even for larger differential signals.

70

Appendix C
Software
Below is a short list of the software I used for the project.
Most time I typed in the hspice netlists instead of using the schematic entry. This
method has the advantage that changes in the circuit can be realised much easier and faster. All changes can be made in the netlist at once and devices can be
copied or out-commented which is quite handy to insert or delete whole devices.
Using the schematic entry, each device has to be selected to change its values and
it is more complicated to insert respectively delete devices. On the other hand the
schematic entry has the benefit that you always can see how the circuit looks like.
It is more difficult to see how all the devices are connected by reading the netlist
of a circuit.

UNIX Sun solaris 2.6:


Star-Hspice98.2
avant! AvanWaves98.2
Cadence Design Framework II 4.4.2
Netscape 4.51 (for reading the HSpice online-manual)
71

xv 3.10 (screengrabber)
xEmacs
LATEX
xdvi

Adobe AcrobatReader
Suse-Linux 6.3:
xEmacs
LATEX
xdvi

Adobe AcrobatReader
Windows NT/98:
Orcad 9 PSpice Demo

72

Bibliography
[1] David. A. Johns, Ken Martin; Analog integrated circuit design
[2] Adel S. Sedra, Kenneth C. Smith; Microelectronic Circuits
[3] Kenneth R. Laker, Willy M.C. Sansen; Design of analog integrated circuits
and systems
[4] Ulrich Ludemann; script of the lecture "Halbleiterschaltungstechnik" (corresponding to Active Circuit Design)
[5] Winfried Soppa; working sheets of the lecture "Schaltkreissimulation mit
SPICE"
[6] Norbert Emeis; script of the lecture "Bauelemente der Elektronik"
[7] Oliver McCarthy; notes of the lecture "Analog Integrated Circuit Design"
[8] Ian Grout; notes of the lecture "ASICs II"
[9] online manual of the Star HSpice 99.2 simulator
[10] META-SOFTWARE; HSpice, Quick Reference Guide
[11] C. Beccari, M. Biey, P.P. Civvalleri, M. Gilli; European Conference on Circuit Theory and Design 99

73

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