Computer Organization and Architecture

Indian Institute of Technology, Guwahati

Assignment:
Booths Algorithm for Signed Multiplication

Booths Algorithm is an elegant way to multiply signed numbers using the same
hardware as before and save cycles and can handle multiple bits at a time.

Group Details:
Bhavya Madan
Chaitanya Agarwal
Sanket Garg

Assignment Guide:
Dr. Santosh Biswas
Dept CSE
IIT Guwahati

11010113
11010115
11012335

Dept. CSE
Dept. CSE
Dept. MNC

Booths Algorithm for Signed Multiplication

Since, the multiplication of numbers gives the same absolute value whether
they are positive or negative. So we just have to take care whether the numbers
finally give a positive output or negative output. This is taken care by following
preprocessing and post processing. Other than that we follow the same
algorithm for normal unsigned multiplication.
Preprocessing:
Find the Signed bit of the Product AQ. This can be done using an Ex-OR gate
with signed bits of both the numbers as the input for the Ex-OR gate.
Let the signed bits of numbers be F1 and F2 respectively, and F as the signed bit
for product.
F = F1 F2
Post processing:
If F = 0, the product is what is calculated.
If F = 1, the product we get is the 2s complement of the product (as a negative
number), it can be converted back to the normal representation by putting - as
its prefix.

We have an alternate representation for the numbers to avoid preprocessing

and post processing.

Booths Algorithm for Signed Multiplication

Use the 2s complement signed representation for the negative numbers.
Example: -7 is represented as 1001 (1 in the MSB signifies the negative number).
How to have this representation working for Booths Algorithm ?
Algorithm:
Let the multiplicand be M, Multiplier be Q and a four-bit register be A.
Add a zero to the end of the number Q (an Extra bit)
Example: 0111 is written as 0111| 0
Read the last two bits of Q including that extra bit, and corresponding symbol
on right is used:
00

01

10

11

When we get 1, we take A = A + M (ADD)

When we get , we take A = A M (Subtract)
Right Shift the cumulative register made up of A and Q.
Note: after shifting, the MSB of the number A gets the same serial input as the
original signed bit.
Repeat the process until the MSB of Q reaches the extra bit.

Flowchart of the Booths Algorithm

The following Illustrations will help you understand the Algorithm better.

Illustration 1
1. Multiplicand = 0100
Multiplier

= 0111

Here,
We are multiplying 4 and 7
So,
M = 0100
Q = 0111
We start by initializing A with 0000
M

0100

0000

0111 0

Putting

zero
(2s comp.
Of -4)

Last 2 digits of Q are 10 so we do A=A-M

Therefore A = (0000)-(0100) = 1100

We shift one position.

We put 1 in the MSB as the no. before shifting was negative

1110

0011 1

Last 2 digits of Q are 11.We just shift and not

add.
We put 1 in the MSB as the no. before shifting was negative

1111

0001 1

Last 2 digits of Q are 11.We just shift and not

add.
We put 1 in the MSB as the no. before shifting was negative

1111

1000 1

Last 2 digits of Q are 01 so we do A=A+M

A=(1111)+(0100)=0011

We shift one position

0001

1100 0

00011100 is 28 in binary our desired product.

Illustration 2
2. Multiplicand = 1100
Multiplier

= 0111

Here,
We are multiplying -4 and 7
(1100 is 2s complement of -4)

So,
M = 1100
Q = 0111
We start by initializing A with 0000
M

1100

0000

0111 0

Putting zero

(2s comp.
Of -4)

Last 2 digits of Q are 10 so we do A=A-M

Therefore A = (0000)-(1100) = 0100
We shift one position

0010

0011 1

Last 2 digits of Q are 11.We just shift and not

add.
0001

0001 1

Last 2 digits of Q are 11.We just shift and not

add.
0000

1000 1

Last 2 digits of Q are 01 so we do A=A+M

A=(0000)+(1100)=1100
We shift one postion
We put 1 in the MSB as the no. before shifting was negative

1110

0100 0

11100100 is -28 in 2s complement representation and our

desired product

Illustration 3
3. Multiplicand = 0111
Multiplier

= 1100

Here,
We are multiplying -4 and 7
(1100 is 2s complement of -4)

So,
M = 0111
Q = 1100
We start by initializing A with 0000
M
0111

A
0000

Q
1100 0 Putting zero

(2s complement Of -4)

Last 2 digits of Q are 00 so we just shift and not

add.

0000

0110 0

Last 2 digits of Q are 00.We just shift and not

add.
0000

0011 0

Last 2 digits of Q are 10 so we do A=A-M

A=(0000)-(0111)=1001
We shift one position
We put 1 in the MSB as the no. before shifting was negative

1100

1001 1

Last 2 digits of Q are 11. We just shift and not

add.
We put 1 in the MSB as the no. before shifting was
negative

1110

0100 1

11100100 is -28 in 2s complement representation and our

desired product

Illustration 4
4. Multiplicand = 1100
Multiplier

= 1101

Here,
We are multiplying -4 and -3
(1100 is 2s complement of -4 and 1101 is 2s complement of -3)

So,
M = 1100
Q = 1101
We start by initializing A with 0000
M

1100

0000

1101 0

Putting zero

(2s complement Of -4)

Last 2 digits of Q are 10 so we do A=A-M

Therefore A = (0000)-(1100) = 0100
We shift one position
0010

0110 1

Last 2 digits of Q are 01 so we do A=A+M.

A = (0010)+(1100) = 1110
We shift one position
We put 1 in the MSB as the no. before shifting was negative
1111

0011 0

Last 2 digits of Q are 10 so we do A=A-M

Therefore A = (1111)-(1100) = 0011
We shift one position

0001

1001 1

Last 2 digits of Q are 11. We just shift and not add

0000

1100 1

00001100 which is 12 in binary is our desired product.

Hope you would have developed a good understanding of how the Booth
algorithm works. Now, Let us have a look at its Control Path design.

Basics of Control Path Design for Booth Multiplier

We have already seen the Data path which tells us all about how the data flows
in the Booths Algorithm and what Arithmetic or Shifting operations are
performed. Now how all this stuff in managed in the Hardware?
For this well see the Control Path Design for the Booths Algorithm.
Types of Hardware Blocks required:
A.
B.
C.
D.

Adder Subtractor
Counter
Multi-Function Register
Comparator

Lets start with an example:

M

1100

0000

01110

100

-4
1100

7
0100

01110

011

0010

00111

1100

0001

00011

010

1100

0000

10001

001

1100

1100

10001

000

1100

1110

01000

L is counter as we need to make sure we do only four iterations.

We need a control signal to freeze the value in A and Q when L is 000. In the
beginning, we need to reset A to 0000, load M and Q. So we need a control path
design.
Value of M is available is in external memory or incoming data bus.

The algorithm:

A<-0;

M<-Inbus;

L<-4;

Rest

Load

Load

Q [4:1] Inbus;

Q[0] 0;

Load

Load

Loop: if Q[1:0]=01 go to Add

If Q[1:0]=10 go to Sub
Go to Rshift (for 00 or 11)

Add: A A+M;

go to Rshift

Sub: A A-M

go to Rshift

Rshift: Shift (AQ);

LL-1;

shift puts MSB as old MSB

Decrement

If L<>0 (Comparator)
go to loop;

Output: AQ;

HALT;

So we require a register which can load, reset, intelligent shift, decrememnt,

although not all.

Clear

Load

Right shift

Decrement by
1

Freeze

Multifunction register

Although Q required only load and shift, L required load, decrement, etc. then
also we use a register with all five operations in all registers for simplicity.
Although we have only five operations, we could have done using 3 bits also but
then we would require a decoder. So we use a flat design. Also its easier to
debug.

Tri state buffer

The terminals of AQ are always connected to output trio but required stable
output is obtained only after freeze (i.e. Halt). As we dont want output to
change as AQ changes, we cut the signal using tri-state buffer, like a switch.

Bidirectional bus

When C=0, 1 gets control signal 0 and 2 gets the inverted signal i.e. 1. So 2 allow
flow. Hence data flows from Y1 to X1. When C=1, data flows from X1 to Y1.