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Testability
Mikael Olausson & Daniel Wiklund
Electronic Devices, IFM
Outline
Introduction
DFT techniques
Scan types
Scan cells
Scan designs
Conclusions
Introduction
Costs of test?
Testability
Abstract measure of costs in testing
Major factors in test generation cost
Controllability
Observability
Predictability
General observations
Improving testability
Two methods to improve testability
Redesign and/or resynthesis
Additional hardware
Discussion
To what extent should we use DFT?
Area aspects?
Time aspects?
Fault coverage?
Outline
Introduction
DFT techniques
Scan types
Scan cells
Scan designs
Conclusions
Ad hoc DFT
Test points
Initialization of sequential circuits
One-shots, clocks, and oscillators
Counters and shift registers
Partitioning
Redundancy
Global feedback paths
Discussion
Drawbacks with these rules?
More ad hoc rules for DFT?
How about tri-state signals?
Outline
Introduction
DFT techniques
Scan types
Scan cells
Scan designs
Conclusions
Scan types
Simultaneous C/O
Separate C/O
Observability only
Controllability only
C1
Mux
T
C2
Boundary scan
Isolation of modules or chips
Provide scan on I/O connections
Standardized for chips
IEEE 1149.1 (JTAG)
Scan-based designs
Integrated serial scan
Isolated serial scan
Nonserial scan
Outline
Introduction
DFT techniques
Scan types
Scan cells
Scan designs
Conclusions
Scan cells
Q1
Memory type
Single or double latch
Flip-flop
D
Si
L1
L2
Clk T
Clocking
Single clock
Multiple nonoverlapping clocks
Q2
Q1
D
Si
L1
Clk1 T
Clk2
L2
Q2
Scan cell
Shift operation
Separate shift clock
Shift enable using system clock
Random access
Polarity hold addressable latch
Cell structure
0
SA
rst
scanin
scanout
sysout
1
sel
sel
sysin
0
L
1
en
sel
sel
Discussion
Cell for nonserial scan in CMOS?
Is it worth the overhead to be able to do atspeed testing?
Outline
Introduction
DFT techniques
Scan types
Scan cells
Scan designs
Conclusions
Scan designs
LSSD
Full serial integrated scan architecture
Three styles
Single latch
Double latch design
L2* single latch design
VSC concept
Core
Sclk
Si
So
LFSR
Scan chain
MUX
Scan chain
MUX
Scan chain
Sel
MISR
SC
LFSR
VSC
Test cycles reduction
ISCAS 89 benchmarks
Up to 70% with same ATPG
Up to 50% using Compactest for normal scan
Drawbacks
May get less coverage due to aliasing in MISR
More complex than normal scan
Outline
Introduction
DFT techniques
Scan types
Scan cells
Scan designs
Conclusions
Conclusions
Questions?
References
Brakel, Xing, and Kerkhoff. Scan cell design for enhanced delay fault
testability. Proc of the fifth annual IEEE intl ASIC conference and
exhibition. IEEE 1992.
Jas, Pouya, and Touba. Virtual scan chains: A means for reducing
scan length in cores. Proc of the 18th IEEE VLSI test symposium.
IEEE 2000.