Philips Semiconductors

Product specification

PowerMOS transistor
Logic level TOPFET
DESCRIPTION
Monolithic temperature and
overload protected logic level power
MOSFET in a 5 pin plastic
envelope, intended as a general
purpose switch for automotive
systems and other applications.

APPLICATIONS
General controller for driving
lamps
motors
solenoids
heaters

FEATURES
Vertical power DMOS output
stage
Low on-state resistance
Logic and protection supply
from separate pin
Low operating supply current
Overload protection against
over temperature
Overload protection against
short circuit load
Latched overload protection
reset by protection supply
Protection circuit condition
indicated by flag pin
5 V logic compatible input level
Separate input pin
for higher frequency drive
ESD protection on input, flag
and protection supply pins
Over voltage clamping for turn
off of inductive loads
Both linear and switching
operation are possible

PINNING - SOT263
PIN

BUK104-50L/S
BUK104-50LP/SP
QUICK REFERENCE DATA
SYMBOL

PARAMETER

VDS
ID
Ptot
Tj
RDS(ON)

Continuous drain source voltage

Continuous drain current
Total power dissipation
Continuous junction temperature
Drain-source on-state resistance
VIS = 5 V
VIS = 7 V

SYMBOL

PARAMETER

VPSN

Protection supply voltage

BUK104-50L
BUK104-50S

MAX.

UNIT

50
15
40
150

V
A
W
C

125
100

m
m

NOM.

UNIT

5
10

V
V

FUNCTIONAL BLOCK DIAGRAM

PROTECTION SUPPLY

DRAIN

FLAG

O/V
CLAMP

POWER

INPUT

MOSFET

LOGIC AND
PROTECTION

SOURCE

Fig.1. Elements of the TOPFET.

PIN CONFIGURATION

SYMBOL

DESCRIPTION
tab

input

flag

drain

protection supply

source

tab

D
TOPFET
P
F
I

leadform
263-01

1 2345

Fig. 2. Type numbers ending with

suffix P refer to leadform 263-01.

Fig. 3.

drain

January 1993

Rev 1.200

Philips Semiconductors

Product specification

PowerMOS transistor
Logic level TOPFET

BUK104-50L/S
BUK104-50LP/SP

LIMITING VALUES
Limiting values in accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL
VDSS
VIS
VFS
VPS

PARAMETER

CONDITIONS

Voltages
Continuous off-state drain source
voltage1
Continuous input voltage
Continuous flag voltage
Continuous supply voltage

MIN.

MAX.

UNIT

50

0
0
0

11
11
11

V
V
V

VIS = 0 V
-

Currents

VIS =

ID
ID
IDRM

Continuous drain current

Continuous drain current
Repetitive peak on-state drain current

Tmb 25 C
Tmb 100 C
Tmb 25 C

15 13
9.5 8.5
60 54

A
A
A

Ptot
Tstg
Tj

Thermal
Total power dissipation
Storage temperature
Junction temperature2

Tmb = 25 C
continuous

-55
-

40
150
150

W
C
C

Tsold

Lead temperature

during soldering

250

OVERLOAD PROTECTION LIMITING VALUES

With the protection supply
connected, TOPFET can protect
itself from two types of overload over temperature and short circuit
load.
SYMBOL

An n-MOS transistor turns on

between the input and source to
quickly discharge the power
MOSFET gate capacitance.

PARAMETER

For internal overload protection to

remain latched while the control
circuit is high, external series input
resistance must be provided. Refer
to INPUT CHARACTERISTICS.

CONDITIONS

MIN.
VIS =

UNIT

4.4
5.4

4
5

V
V

VPSP

Protection supply voltage

VDDP(T)

Over temperature protection

VPS = VPSN
Protected drain source supply voltage VIS = 10 V; RI 2 k
VIS = 5 V; RI 1 k

50
50

V
V

VDDP(P)

Short circuit load protection

VPS = VPSN; L 10 H
Protected drain source supply voltage4 VIS = 10 V; RI 2 k
VIS = 5 V; RI 1 k
Instantaneous overload dissipation

25
45
0.8

V
V
kW

MIN.

MAX.

UNIT

kV

PDSM

for valid protection

BUK104-50L
BUK104-50S

MAX.

ESD LIMITING VALUE

SYMBOL

PARAMETER

CONDITIONS

VC

Electrostatic discharge capacitor

voltage

Human body model;

C = 250 pF; R = 1.5 k

1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy.
2 A higher Tj is allowed as an overload condition but at the threshold Tj(TO) the over temperature trip operates to protect the switch.
3 The minimum supply voltage required for correct operation of the overload protection circuits.
4 The device is able to self-protect against a short circuit load providing the drain-source supply voltage does not exceed VDDP(P) maximum.
For further information, refer to OVERLOAD PROTECTION CHARACTERISTICS.

January 1993

Rev 1.200

Philips Semiconductors

Product specification

PowerMOS transistor
Logic level TOPFET

BUK104-50L/S
BUK104-50LP/SP

OVERVOLTAGE CLAMPING LIMITING VALUES

At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients.
SYMBOL

PARAMETER

IDRRM
EDSM

Repetitive peak clamping drain current RIS 100

Non-repetitive inductive turn-off
IDM = 15 A; RIS 100
energy2
Repetitive inductive turn-off energy
RIS 100 ; Tmb 95 C;
IDM = 4 A; VDD 20 V;
f = 250 Hz

EDRM

IDIRM

CONDITIONS

MIN.

MAX.

UNIT

15
200

A
mJ

20

mJ

50

mA

MIN.

MAX.

UNIT

15

Repetitive peak drain to input current3

RIS = 0 ; tp 1 ms

REVERSE DIODE LIMITING VALUE

SYMBOL

PARAMETER

CONDITIONS

IS

Continuous forward current

Tmb = 25 C;
VIS = VPS = VFS = 0 V

THERMAL CHARACTERISTICS
SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2.5

3.1

K/W

60

K/W

MIN.

TYP.

MAX.

UNIT

50

65

50

70

0.5
1

10
20

A
A

10

100

75
95

100
125

m
m

Thermal resistance
Rth j-mb

Junction to mounting base

Rth j-a

Junction to ambient

in free air

STATIC CHARACTERISTICS
Tmb = 25 C unless otherwise specified
SYMBOL

PARAMETER

CONDITIONS

V(CL)DSR

Drain-source clamping voltage

RIS = 100 ; ID = 10 mA

V(CL)DSR

Drain-source clamping voltage

IDSS
IDSR
IDSR
RDS(ON)

RIS = 100 ; IDM = 1 A; tp 300 s;

0.01
Zero input voltage drain current VDS = 12 V; VIS = 0 V
Drain source leakage current
VDS = 50 V; RIS = 100 ;
Drain source leakage current
VDS = 40 V; RIS = 100 ;
Tj = 125 C
Drain-source on-state
resistance

IDM = 7.5 A;
tp 300 s; 0.01

VIS = 7 V
VIS = 5 V

1 The input pin must be connected to the source pin by a specified external resistance to allow the power MOSFET gate source voltage to
become sufficiently positive for active clamping. Refer to INPUT CHARACTERISTICS.
2 While the protection supply voltage is connected, during overvoltage clamping it is possible that the overload protection may operate at
energies close to the limiting value. Refer to OVERLOAD PROTECTION CHARACTERISTICS.
3 Shorting the input to source with low resistance inhibits the internal overvoltage protection by preventing the power MOSFET gate source
voltage becoming positive.

January 1993

Rev 1.200

Philips Semiconductors

Product specification

PowerMOS transistor
Logic level TOPFET

BUK104-50L/S
BUK104-50LP/SP

OVERLOAD PROTECTION CHARACTERISTICS

With adequate protection supply
voltage TOPFET detects when one
of the overload thresholds is
exceeded.
SYMBOL

Provided there is adequate input

series resistance it switches off
and remains latched off until reset
by the protection supply pin.

PARAMETER

Refer also to OVERLOAD

PROTECTION LIMITING VALUES
and INPUT CHARACTERISTICS.

CONDITIONS
1

Short circuit load protection

VPS = V
; Tmb = 25 C; L 10 H;
RI 2 k
VDD = 13 V; VIS = 10 V
VDD = 13 V; VIS = 10 V

MIN.

TYP.

MAX.

UNIT

150
375

mJ
s

150

2
PSN

EDS(TO)
td sc

Overload threshold energy

Response time

Tj(TO)

Over temperature protection VPS = VPSN; RI 2 k

Threshold junction temperature from ID 0.65 A3

TRANSFER CHARACTERISTICS
Tmb = 25 C
SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

gfs

Forward transconductance

VDS = 10 V; IDM = 7.5 A tp 300 s;

0.01

ID

Drain current4

VDS = 13 V;

25
40

A
A

MIN.

TYP.

MAX.

UNIT

Tj = 150 C

1.5
1.0

0.2
0.4
2.5
-

0.35
1.0
3.5
-

mA
mA
V
V

IP = 1.35 mA

11

13

MIN.

TYP.

MAX.

UNIT

VIS = 5 V
VIS = 10 V

PROTECTION SUPPLY CHARACTERISTICS

Tmb = 25 C unless otherwise specified
SYMBOL
IPS,
IPSL

VPSR
V(CL)PS

PARAMETER
Protection supply
Protection supply current

CONDITIONS
normal operation or
protection latched
BUK104-50L
BUK104-50S

Protection reset voltage5

Protection clamp voltage

VPS = 5 V
VPS = 10 V

REVERSE DIODE CHARACTERISTICS

Tmb = 25 C
SYMBOL

PARAMETER

CONDITIONS

VSDS

Forward voltage

IS = 15 A; VIS = VPS = VFS = 0 V;

tp = 300 s

1.0

1.5

trr

Reverse recovery time

not applicable6

1 The short circuit load protection is able to save the device providing the instantaneous on-state dissipation is less than the limiting value for
PDSM, which is always the case when VDS is less than VDSP maximum.
2 At the appropriate nominal protection supply voltage for each type. Refer to QUICK REFERENCE DATA.
3 The over temperature protection feature requires a minimum on-state drain source voltage for correct operation. The specified minimum ID
ensures this condition.
4 During overload condition. Refer also to OVERLOAD PROTECTION LIMITING VALUES and CHARACTERISTICS.
5 The supply voltage below which the overload protection circuits will be reset.
6 The reverse diode of this type is not intended for applications requiring fast reverse recovery.

January 1993

Rev 1.200

Philips Semiconductors

Product specification

PowerMOS transistor
Logic level TOPFET

BUK104-50L/S
BUK104-50LP/SP

INPUT CHARACTERISTICS
Tmb = 25 C unless otherwise specified
SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1.0
0.5
11

1.5
10
13

2.0
100
-

V
V
nA
V

55
95
35
60

VDS > 30 V

100

VII = 5 V
VII = 10 V

1
2

k
k

Normal operation
VIS(TO)

Input threshold voltage

IIS
V(CL)IS

Input current
Input clamp voltage

VDS = 5 V; ID = 1 mA
Tmb = 150 C
VIS = 10 V
II = 1 mA

Overload protection latched

RISL

Input resistance1

VPS = 5 V

II = 5 mA;
Tmb = 150 C
II = 5 mA;
Tmb = 150 C

VPS = 10 V

RIS
RI

Application information
External input resistances for
internal overvoltage clamping2
3

internal overload protection

(see figure 29)

RI = ;
RIS = ;

SWITCHING CHARACTERISTICS
Tmb = 25 C; RI = 50 ; RIS = 50 (see figure 29); resistive load RL = 10 . For waveforms see figure 28.
SYMBOL

PARAMETER

CONDITIONS

td on

Turn-on delay time

VDD = 15 V; VIS: 0 V 10 V

tr

Rise time

td off

Turn-off delay time

tf

Fall time

VDD = 15 V; VIS: 10 V 0 V

MIN.

TYP.

MAX.

UNIT

ns

13

ns

100

ns

45

ns

MIN.

TYP.

MAX.

UNIT

CAPACITANCES
Tmb = 25 C; f = 1 MHz
SYMBOL

PARAMETER

CONDITIONS

Ciss

Input capacitance

VDS = 25 V; VIS = 0 V

415

600

pF

Coss

Output capacitance

VDS = 25 V; VIS = 0 V

275

400

pF

Crss

Reverse transfer capacitance

VDS = 25 V; VIS = 0 V

55

80

pF

Cpso

Protection supply pin

capacitance

VPS = 10 V

30

pF

Cfso

Flag pin capacitance

VFS = 10 V; VPS = 0 V

20

pF

1 The resistance of the internal transistor which discharges the power MOSFET gate capacitance when overload protection operates.
The external drive circuit should be such that the input voltage does not exceed VIS(TO) minimum when the overload protection has
operated. Refer also to figure for latched input characteristics.
2 Applications using a lower value for RIS would require external overvoltage protection.
3 For applications requiring a lower value for RI, an external overload protection strategy is possible using the flag pin to tell the control circuit to
switch off the input.

January 1993

Rev 1.200

Philips Semiconductors

Product specification

PowerMOS transistor
Logic level TOPFET
FLAG DESCRIPTION
The flag pin provides a means to
detect the presence of the
protection supply and indicate the
state of the overload detectors.
The flag is the open drain of an
n-MOS transistor and requires an
external pull-up resistor1. It is
suitable for both 5 V and 10 V logic.
Flag may be used to implement an
external protection strategy2 for
applications which require low input
drive impedance.

BUK104-50L/S
BUK104-50LP/SP
TRUTH TABLE
CONDITION

DESCRIPTION

FLAG

NORMAL

Normal operation and adequate

protection supply voltage

LOGIC LOW

OVER TEMP.

Over temperature detected

LOGIC HIGH

SHORT CIRCUIT

Overload condition detected

LOGIC HIGH

SUPPLY FAULT

Inadequate protection supply

voltage

LOGIC HIGH

FLAG CHARACTERISTICS
Tmb = 25 C unless otherwise stated
SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

VFS
IFSS

Flag low
Flag voltage
Flag saturation current

normal operation
IF = 1.6 mA
VFS = 10 V

0.15
15

0.4
-

V
mA

IFS
VPSF

Flag high
Flag leakage current
Protection supply threshold
voltage

overload or fault
VFS = 10 V
VFF = 5 V; RF = 3 k;

10

2.5
3.3

3.3
4.2

4
5

V
V

V(CL)FS

Flag clamping voltage

IF = 1 mA; VPS = 0 V

11

13

VFF =5 V
VFF =10 V

1
2

10
20

50
100

k
k

MIN.

TYP.

MAX.

UNIT

3.5

nH

4.5

nH

7.5

nH

BUK104-50L
BUK104-50S

Application information
RF

Suitable external pull-up

resistance

ENVELOPE CHARACTERISTICS
SYMBOL

PARAMETER

CONDITIONS

Ld

Internal drain inductance

Ld

Internal drain inductance

Ls

Internal source inductance

Measured from contact screw on

tab to centre of die
Measured from drain lead 6 mm
from package to centre of die
Measured from source lead 6 mm
from package to source bond pad

1 Even if the flag pin is not used, it is recommended that it is connected to the protection supply via a pull-up resistor. It should not be left
floating.
2 Low pass filtering of the flag signal may be advisable to prevent false tripping.

January 1993

Rev 1.200

Philips Semiconductors

Product specification

PowerMOS transistor
Logic level TOPFET

120

BUK104-50L/S
BUK104-50LP/SP

Normalised Power Derating

PD%

BUK104-50L/S

Zth / (K/W)

10

110
100
90

D=
0.5

80

70

0.2

60
50

0.05

0.1

40

0.1

0.02
PD

30
20
10

D=

tp
T

0
0

20

40

60

80
100
Tmb / C

120

1E-05

1E-03
t/s

1E-01

1E+01

Fig.7. Transient thermal impedance.

Zth j-mb = f(t); parameter D = tp/T

Normalised Current Derating

ID%

0.01
1E-07

140

Fig.4. Normalised limiting power dissipation.

PD% = 100PD/PD(25 C) = f(Tmb)

120

tp

50

ID / A

BUK104-50L/S

110

VIS / V =

100
90

10

40

80
70

30

60
50

20

8
7
6
5

40
30

3
2

0
0

20

40

60

80
Tmb / C

100

120

140

Fig.5. Normalised continuous drain current.

ID% = 100ID/ID(25 C) = f(Tmb); conditions: VIS = 5 V

100

10

20
10

D
S/I

=V

20

12

16
VDS / V

VIS / V =

10 us

O
S(

20

ID / A

tp =

N)

24

28

32

Fig.8. Typical output characteristics, Tj = 25 C.

ID = f(VDS); parameter VIS; tp = 250 s & tp < td sc

BUK104-50L/S

ID & IDM / A

10

BUK104-50L/S
7
6
5

RD

15

10

100 us

4
1 ms
DC

10

10 ms

100 ms

5
3
Overload protection characteristics not shown
0.1

0
1

10

100

VDS / V

Fig.6. Safe operating area. Tmb = 25 C

ID & IDM = f(VDS); IDM single pulse; parameter tp

January 1993

1
VDS / V

Fig.9. Typical on-state characteristics, Tj = 25 C.

ID = f(VDS); parameter VIS; tp = 250 s

Rev 1.200

Philips Semiconductors

Product specification

PowerMOS transistor
Logic level TOPFET

BUK104-50L/S
BUK104-50LP/SP

RDS(ON) / mOhm

150

BUK104-50L/S
VIS / V =

Normalised RDS(ON) = f(Tj)

1.5

5
6

100

1.0

10
50

0.5

0
0

10
ID / A

12

14

16

18

20

BUK104-50L/S

ID / A

20

40 60
Tj / C

80

100 120 140

Fig.13. Normalised drain-source on-state resistance.

a = RDS(ON)/RDS(ON)25 C = f(Tj); ID = 7.5 A; VIS 5 V

Fig.10. Typical on-state resistance, Tj = 25 C.

RDS(ON) = f(ID); parameter VIS; tp = 250 s

50

-60 -40 -20

230

Tj(TO) / C

BUK104-50L/S

220

40

210
200

30

190

20

BUK104-50S

180
170

10

BUK104-50L

160

150

6
VIS / V

10

12

Fig.11. Typical transfer characteristics, Tj = 25 C.

ID = f(VIS) ; conditions: VDS = 10 V; tp = 250 s

10

gfs / S

6
VPS / V

10

Fig.14. Typical over temperature protection threshold

Tj(TO) = f(VPS); conditions: VDS > 0.1 V
PDSM%

BUK104-50L/S
120

9
8

100

7
80

6
5

60

4
40

3
2

20

1
0

10

20

30

40

-60

50

ID / A

Fig.12. Typical transconductance, Tj = 25 C.

gfs = f(ID); conditions: VDS = 10 V; tp = 250 s

January 1993

-40

-20

20

40
60
Tmb / C

80

100

120

140

Fig.15. Normalised limiting overload dissipation.

PDSM% =100PDSM/PDSM(25 C) = f(Tmb)

Rev 1.200

Philips Semiconductors

Product specification

PowerMOS transistor
Logic level TOPFET

50

BUK104-50L/S
BUK104-50LP/SP

VDDP(P) / V

BUK104-50L/S

0.5

40

Energy & Time

BUK104-50L/S

0.4

max
30

0.3

20

0.2

10

0.1

Time / ms

Energy / J
Tj(TO)

6
VIS / V

-60

10

20

60

100
Tmb / C

140

180

220

Fig.19. Typical overload protection characteristics.

Conditions: VDD = 13 V; VPS = VPSN, VIS = 7 V; SC load

Fig.16. Maximum drain source supply voltage for

SC load protection. VDDP(P) = f(VIS); Tmb 150 C
VPSP / V

-20

BUK104-50L/S

0.4

ESC(TO) / J

BUK104-50L/S

10

0.3

BUK104-50L
VIS / V = 5

min

BUK104-50S

10

0.2
5

10
BUK104-50L

0.1

BUK104-50S

0
0

6
VIS / V

10

TIME / ms

6
VPS / V

10

Fig.20. Typical overload protection energy, Tj = 25 C

ESC(TO) = f(VPS); conditions: VDS = 13 V, parameter VIS

Fig.17. Minimum protection supply voltage

for SC load protection. VPSP = f(VIS); Tmb 25 C

10

BUK104-50L/S

20

ID / A

BUK104-50L/S

15

typ.

10

1
PDSM

0.1

0
0.1

1
POWER / kW

50

10

Fig.18. Typical overload protection characteristics.

td sc = f(PDS); conditions: VPS VPSP; VIS 5 V

January 1993

60
VDS / V

70

Fig.21. Typical clamping characteristics, 25 C.

ID = f(VDS); conditions: RIS = 100 ; tp 50 s

Rev 1.200

Philips Semiconductors

Product specification

PowerMOS transistor
Logic level TOPFET

BUK104-50L/S
BUK104-50LP/SP

VIS(TO) / V

IS / A

20

BUK104-50L/S

max.

15
typ.

10

min.

0
-60

-40

-20

20

40
60
Tj / C

80

100

120 140

1.5

VSD / V

Fig.25. Typical reverse diode current, Tj = 25 C.

IS = f(VSDS); conditions: VIS = 0 V; tp = 250 s

Fig.22. Input threshold voltage.

VIS(TO) = f(Tj); conditions: ID = 1 mA; VDS = 5 V
IPS / mA

1.0

0.5

BUK104-50L/S

EDSM%

120
110
100
90
80
70

0.5

60
50
40
30
20
10

0
0

10

12

14

20

40

60

VPS / V

Fig.23. Typical DC protection supply characteristics.

IPS = f(VPS); normal or overload operation; Tj = 25 C
IISL / mA

BUK104-50L/S

140

V(CL)DSR
VDD

VIS

VDS

+ VPS

RF

TOPFET

VDD

ID

50

120

VDS

10

100

100

Fig.26. Normalised limiting clamping energy.

EDSM% = f(Tmb); conditions: ID = 15 A

150
VPS / V = 11

80
Tmb / C

RI = RIS

P
F
I

-ID/100

D.U.T.

R 01
shunt

0
0

6
VIS / V

10

Fig.27. Clamping energy test circuit, RIS = 100 .

EDSM = 0.5 LID2 V(CL)DSR /(V(CL)DSR VDD )

Fig.24. Typical latched input characteristics, 25 C.

IISL = f(VIS); after overload protection latched

January 1993

10

Rev 1.200

Philips Semiconductors

Product specification

PowerMOS transistor
Logic level TOPFET

BUK104-50L/S
BUK104-50LP/SP

VIS / V & VDS / V

BUK104-50L/S

1 mA

Idsr

15
VDS

100 uA

VIS
10

10 uA

typ.
5

1 uA

100 nA
0

0.5
time / us

20

40

60

80
Tj / C

100

120

140

Fig.31. Typical off-state leakage current.

IDSR = f(Tj); Conditions: VDS = 40 V; RIS = 100 .

Fig.28. Typical resistive load switching waveforms

RI = RIS = 50 ; RL = 10 ; VDD = 15 V; Tj = 25 C

Ips normalised to 25 C

VII
1.5
D

RI

TOPFET
P
F
I

VIS

1
S

RIS

0.5
-60

Fig.29. External input resistances RI and RIS,

generator voltage VII and input voltage VIS.

10000

Capacitance / pF

-20

20

60
Tj / C

100

140

180

Fig.32. Normalised protection supply current.

IPS/IPS25 C = f(Tj); VPS = VPSN

BUK104-50L/S

1000
Ciss

Coss
100
Crss

10
0

10

20

30

40

50

VDS / V

Fig.30. Typical capacitances, Ciss, Coss, Crss.

C = f(VDS); conditions: VIS = 0 V; f = 1 MHz

January 1993

11

Rev 1.200

Philips Semiconductors

Product specification

PowerMOS transistor
Logic level TOPFET

BUK104-50L/S
BUK104-50LP/SP

MECHANICAL DATA
Dimensions in mm

4.5
max

Net Mass: 2 g

10.3
max
1.3

3.6
2.8
mounting
base

5.9
min

15.8
max

2.4
max
(2)

3.5 max
not tinned

0.5

(1)

13.5
min

0.6
min (4 x)
1.7

1 2 3 4 5

0.6
2.4

(4 x)

0.4

(1)
M

0.9 max
(5 x)
NOTES (1)
(2)

positional accuracy of the terminals

is controlled in this zone only.
terminal dimensions in this zone
are uncontrolled.

Fig.33. SOT263 ( 5-pin TO220 );

pin 3 connected to mounting base.
Note
1. Refer to mounting instructions for TO220 envelopes.
2. Epoxy meets UL94 V0 at 1/8".

January 1993

12

Rev 1.200

Philips Semiconductors

Product specification

PowerMOS transistor
Logic level TOPFET

BUK104-50L/S
BUK104-50LP/SP

MECHANICAL DATA
Dimensions in mm

4.5
max

Net Mass: 2 g

10.3
max
1.3

3.6
2.8

5.9
min

mounting
base

15.8
max
5

in

2.4
max
R

0.

(2)

3.5 max
not tinned

5.6
9.75
0.

0.6
min (4 x)

0.6

1 2 3 4 5

in

0.5

(1)

1.7

2.4
4.5

(4 x)

0.4

(1)
M

0.9 max

8.2

(5 x)
NOTES (1)
(2)

positional accuracy of the terminals

is controlled in this zone only.
terminal dimensions in this zone
are uncontrolled.

Fig.34. SOT263 leadform 263-01;

pin 3 connected to mounting base.
Note
1. Refer to mounting instructions for TO220 envelopes.
2. Epoxy meets UL94 V0 at 1/8".

January 1993

13

Rev 1.200

Philips Semiconductors

Product specification

PowerMOS transistor
Logic level TOPFET

BUK104-50L/S
BUK104-50LP/SP

DEFINITIONS
Data sheet status
Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification

This data sheet contains final product specifications.

Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.

January 1993

14

Rev 1.200