Microprocessor and Interfaces

MicroprocessorandInterfaces
Interrupts

Interrupts
Interruptisaprocesswhereanexternaldevicecanget
attentionofthemicroprocessor
tt ti
f th
i
TheprocessstartsfromtheI/Odevice
Theprocessisasynchronous

ClassificationofInterrupts
Maskable Interrupts(CanbedelayedorRejected)
NonMaskable Interrupts(CannotbedelayedorRejected)

ClassificationofInterrupts
p
Vectored(theaddressoftheserviceroutineishardwired)
Nonvectored(theaddressoftheserviceroutineneedstobesupplied
externallybythedevice)

Interrupts
Aninterruptisconsideredtobeanemergency
p
g y
signalthatmaybeserviced
TheMicroprocessormayrespondtoitassoonas
possible

WhathappenswhenMPisinterrupted?
pp
p
WhentheMicroprocessorreceivesaninterruptsignal,
itcompletesthecurrentlyexecutingprogramand
then jumps to an Interrupt Service Routine (ISR) to
thenjumpstoanInterruptServiceRoutine(ISR)to
respondtotheincominginterrupt
EachinterruptwillmostprobablyhaveitsownISR

Responding to Interrupts
RespondingtoInterrupts
Responsetoaninterruptmaybeimmediateordelayed
dependingonwhethertheinterruptismaskable or
nonmaskable andwhetherinterruptsarebeing
maskedornot
Therearetwowaysofredirectingtheexecutiontothe
ISR depending on whether the interrupt is vectored or
ISRdependingonwhethertheinterruptisvectoredor
nonvectored.
Vectored:Theaddressofthesubroutineisalreadyknown
to the Microprocessor
totheMicroprocessor
NonVectored:Thedevicewillhavetosupplytheaddress
ofthesubroutinetotheMicroprocessor

The 8085 Interrupts

The8085Interrupts
Whenadeviceinterrupts,itactuallywantstheMPto
p ,
y
giveaservicewhichisequivalenttoaskingtheMPto
callasubroutine.ThissubroutineiscalledISR
(Interrupt Service Routine)
(InterruptServiceRoutine)
TheEIinstructionisaonebyteinstructionandisused
p
toEnablethemaskable interrupts
TheDIinstructionisaonebyteinstructionandisused
toDisablethemaskable interrupts
The8085hasasingleNonMaskable interrupt(TRAP)
Thenonmaskable interruptisnotaffectedbythevalueof
the Interrupt Enable flip flop
theInterruptEnableflipflop

The 8085 Interrupts

The8085Interrupts
The8085has5interruptinputs
The 8085 has 5 interrupt inputs
TheINTRinput
TheINTRinputistheonlynonvectoredinterrupt
p
y
p
INTRismaskable usingtheEI/DIinstructionpair

RST5.5,RST6.5,RST7.5areallautomaticallyvectored
RST5.5,RST6.5,andRST7.5areallmaskable

TRAPistheonlynonmaskable interruptinthe8085
TRAPisalsoautomaticallyvectored
TRAP is also automatically vectored

The 8085 Interrupts

The8085Interrupts
Interruptname

Maskable

Vectored

INTR

Yes

No

RST5.5

Yes

Yes

RST6.5

Yes

Yes

RST7.5

Yes

Yes

TRAP

No

Yes

The 8085 Interrupts

The8085Interrupts

Interrupt Vectors and the Vector Table

InterruptVectorsandtheVectorTable
An
Aninterruptvectorisapointertowherethe
interrupt vector is a pointer to where the
ISRisstoredinmemory
Allinterrupts(vectoredorotherwise)are
All interrupts (vectored or otherwise) are
mappedontoamemoryareacalledthe
InterruptVectorTable(IVT)
TheIVTisusuallylocatedinmemorypage00
(0000H 00FFH)
ThepurposeoftheIVTistoholdthevectorsthat
redirectthemicroprocessortotherightplace
when an interrupt arrives
whenaninterruptarrives

Example
Example
Let
Let,adeviceinterruptstheMicroprocessorusing
a device interrupts the Microprocessor using
theRST7.5interruptline.
RST
RST7.5interruptisvectored
7.5 interrupt is vectored
Microprocessorknows,inwhichmemorylocationit
hastogousingacallinstructiontogettheISRaddress
RST7.5isknowsasCall003ChtoMicroprocessor
Microprocessorgoesto003Clocationandwillgeta
JMPinstructiontotheactualISRaddress
TheMicroprocessorwillthen,jumptotheISRlocation

The8085NonVectoredInterrupt
Process
Theinterruptprocessshouldbeenabledusing
e te upt p ocess s ou d be e ab ed us g
theEIinstruction
p
g
The8085checksforaninterruptduringthe
executionofeveryinstruction
IfINTRishigh,MPcompletescurrentinstruction,
disablestheinterruptandsendsINTA(Interrupt
acknowledge)signaltothedevicethat
interrupted
INTAallowstheI/OdevicetosendaRST
instruction through data bus
instructionthroughdatabus

The8085NonVectoredInterrupt
Process
UponreceivingtheRSTinstruction,MPsavesthe
p
g
,
memorylocationofthenextinstructiononthe
stackandtheprogramistransferredtocall
location (ISR Call) specified by the RST instruction
location(ISRCall)specifiedbytheRSTinstruction
MicroprocessorPerformstheISR
ISRmustincludethe
ISR must include the EI
EI instructiontoenablethe
instruction to enable the
furtherinterruptwithintheprogram
RETinstructionattheendoftheISRallowsthe
MP
MPtoretrievethereturnaddressfromthestack
i
h
dd
f
h
k
andtheprogramistransferredbacktowherethe
p g
programwasinterrupted
p

The8085NonVectoredInterrupt
Process
The8085recognizes8RESTARTinstructions:RST0
g
RST7
eachofthesewouldsendtheexecutiontoapredeterminedhard
wiredmemorylocation:
RestartInstruction

Equivalentto

RST0

CALL0000H

RST1

CALL 0008H
CALL0008H

RST2

CALL0010H

RST3

CALL0018H

RST4

CALL0020H

RST5

CALL0028H

RST6

CALL0030H

RST7

CALL0038H

Restart Sequence
RestartSequence
Therestartsequenceismadeupofthree
e esta t seque ce s ade up o t ee
machinecycles
Inthe1stmachinecycle:
ThemicroprocessorsendstheINTAsignal
WhileINTAisactivethemicroprocessorreadsthedatalines
expectingtoreceive,fromtheinterruptingdevice,the
p
g
p g
opcode forthespecificRSTinstruction

Inthe2ndand3rdmachinecycles:
the
the16bitaddressofthenextinstructionissavedonthe
16 bit address of the next instruction is saved on the
stack
Thenthemicroprocessorjumpstotheaddressassociated
with the specified RST instruction
withthespecifiedRSTinstruction

Timing Diagram of Restart Sequence

TimingDiagramofRestartSequence

Hardware Generation of RST Opcode

HardwareGenerationofRSTOpcode
How
Howdoestheexternaldeviceproducethe
does the external device produce the
opcode fortheappropriateRSTinstruction?
Theopcode
The opcode issimplyacollectionofbits
is simply a collection of bits
So,thedeviceneedstosetthebitsofthedatabus
to the appropriate value in response to an INTA
totheappropriatevalueinresponsetoanINTA
signal

Hardware Generation of RST Opcode

HardwareGenerationofRSTOpcode
The following is an
example of
generating RST 5:
RST 5s opcode
p
is EF
D7D6D5D4D3D2D1D0
1 1 1 0 1 1 1 1

Hardware Generation of RST Opcode

HardwareGenerationofRSTOpcode
Duringtheinterruptacknowledgemachinecycle,
u g t e te upt ac o edge ac e cyc e,
(the1stmachinecycleoftheRSToperation):
TheMicroprocessoractivatestheINTAsignal
ThissignalwillenabletheTristatebuffers,whichwill
placethevalueEFHonthedatabus
Therefore,sendingtheMicroprocessortheRST5
Therefore sending the Microprocessor the RST 5
instruction

TheRST5instructionisexactlyequivalenttoCALL
0028H

Issues in Implementing INTR Interrupts

IssuesinImplementingINTRInterrupts
HowlongmustINTRremainhigh?
ThemicroprocessorcheckstheINTRlineoneclockcyclebeforethe
lastTstateofeachinstruction
TheINTRmustremainactivelongenoughtoallowforthelongest
The INTR must remain active long enough to allow for the longest
instruction
Thelongestinstructionforthe8085istheconditionalCALLinstruction
which requires 18 Tstates
whichrequires18T
states

Therefore,theINTRmustremainactivefor17.5Tstates
Iff=3MHZthenT=1/fandso,INTRmustremainactivefor[
(1/3MHZ) * 17 5 5 8 i
(1/3MHZ)*17.55.8microseconds]
d]

Issues in Implementing INTR Interrupts

IssuesinImplementingINTRInterrupts
HowlongcantheINTRremainhigh?
How long can the INTR remain high?
TheINTRlinemustbedeactivatedbeforetheEIis
executed Otherwise the microprocessor will be
executed.Otherwise,themicroprocessorwillbe
interruptedagain
Oncethemicroprocessorstartstorespondtoan
Once the microprocessor starts to respond to an
INTRinterrupt,INTAbecomesactive(=0)

Therefore,INTRshouldbeturnedoffassoon
as the INTA signal is received
astheINTAsignalisreceived

Issues in Implementing INTR Interrupts

IssuesinImplementingINTRInterrupts
Ca
Canthemicroprocessorbeinterruptedagain
t e c op ocesso be te upted aga
beforethecompletionoftheISR?
Assoonasthe1stinterruptarrives,allmaskable
interruptsaredisabled
TheywillonlybeenabledaftertheexecutionoftheEI
instruction

Therefore,theansweris:onlyifweallowitto.
,
y
IftheEIinstructionisplacedearlyintheISR,other
interruptmayoccurbeforetheISRisdone

Multiple Interrupts & Priorities

MultipleInterrupts&Priorities
How
Howdoweallowmultipledevicestointerrupt
do we allow multiple devices to interrupt
usingtheINTRline?
Themicroprocessorcanonlyrespondtoone
The microprocessor can only respond to one
signalonINTRatatime
Therefore,wemustallowthesignalfromonlyone
Therefore we must allow the signal from only one
ofthedevicestoreachthemicroprocessor
Wemustassignsomeprioritytothedifferent
We must assign some priority to the different
devicesandallowtheirsignalstoreachthe
microprocessoraccordingtothepriority

The Priority Encoder

ThePriorityEncoder
The
Thesolutionistouseacircuitcalledthe
solution is to use a circuit called the
priorityencoder(74LS148)
Thiscircuithas8inputsand3outputs
This circuit has 8 inputs and 3 outputs
Theinputsareassignedincreasingpriorities
according to the increasing index of the input
accordingtotheincreasingindexoftheinput
Input7hashighestpriorityandinput0hasthelowest

The3outputscarrytheindexofthehighest
The 3 outputs carry the index of the highest
priorityactiveinput

RST instructionssopcodes
RSTinstruction
opcodes
Instruction

Opcode

RST0

C7(11000111)

RST1

(
)
CF(11001111)

RST2

D7(11010111)

RST3

DF(11011111)

RST4

E7(11100111)
(
)

RST5

EF(11101111)

RST6

F7(11110111)

RST7

FF(11111111)

The Priority Encoder

ThePriorityEncoder
Opcodes
p
forthedifferentRSTinstructionsfollow
asetpattern
BitD5,D4andD3oftheopcodes changeinabinary
sequencefromRST7downtoRST0.
q
Theotherbitsarealways1.
Thisallowsthecodegeneratedbythe74366tobeused
directlytochoosetheappropriateRSTinstruction.

Theonedrawbacktothisschemeisthattheonly
waytochangethepriorityofthedevices
t h
th
i it f th d i
connectedtothe74366(Tristatedbuffer)isto
reconnectthehardware

The Priority Encoder

ThePriorityEncoder

Priority Encoder TruthTable

PriorityEncoderTruth
Table
I7

I6

I5

I4

I3

I2

I1

I0

A2

A1

A0

The8085Maskable/Vectored
Interrupts
The8085has3Maskable/Vectoredinterruptinputs
/
p p
RST5.5,RST6.5,RST7.5
Theyareallmaskable
Theyareautomaticallyvectoredaccordingtothefollowingtable:
They are automatically vectored according to the following table:
Interrupt

Vector

RST5.5

002CH

RST6.5

0034H

RST7.5

003CH

ThevectorsfortheseinterruptfallinbetweenthevectorsfortheRST
instructions.ThatswhytheyhavenameslikeRST5.5(RST5andahalf)

Masking RST 5.5, RST 6.5 and RST 7.5

MaskingRST5.5,RST6.5andRST7.5
These
Thesethreeinterruptsaremaskedattwo
three interrupts are masked at two
levels:
ThroughtheInterruptEnableflipflopandthe
Through the Interrupt Enable flip flop and the
EI/DIinstructions
The
TheInterruptEnableflipflopcontrolsthewhole
Interrupt Enable flip flop controls the whole
maskable interruptprocess

Throughindividualmaskflipflopsthatcontrolthe
availabilityoftheindividualinterrupts
Theseflipflopscontroltheinterruptsindividually

Maskable Interruptsandvector
locations

The8085Maskable/VectoredInterrupt
Process
Theinterruptprocessshouldbeenabledusing
p p
g
theEIinstruction
The8085checksforaninterruptduringthe
execution of every instruction
executionofeveryinstruction
Ifthereisaninterrupt,andiftheinterruptis
enabled using the interrupt mask, the
enabledusingtheinterruptmask,the
microprocessorwillcompletetheexecuting
instruction,andresettheinterruptflipflop
Themicroprocessorthenexecutesacall
Th
i
h
ll
instructionthatsendstheexecutiontothe
pp p
p
appropriatelocationintheinterruptvectortable

The8085Maskable/VectoredInterrupt
Process
Whenthemicroprocessorexecutesthecall
e t e c op ocesso e ecutes t e ca
instruction,itsavestheaddressofthenext
instructiononthestack
Themicroprocessorjumpstothespecificservice
routine
Theserviceroutinemustincludetheinstruction
EItoreenabletheinterruptprocess
Attheendoftheserviceroutine,theRET
At th
d f th
i
ti th RET
instructionreturnstheexecutiontowherethe
program was interrupted
programwasinterrupted

Manipulating the Masks

ManipulatingtheMasks
The
TheInterruptEnableflipflopismanipulated
Interrupt Enable flip flop is manipulated
usingtheEI/DIinstructions
TheindividualmasksforRST5.5,RST6.5and
The individual masks for RST 5 5 RST 6 5 and
RST7.5aremanipulatedusingtheSIM
instruction
Thisinstructiontakesthebitpatterninthe
Accumulator and applies it to the interrupt mask
Accumulatorandappliesittotheinterruptmask
enablinganddisablingthespecificinterrupts

How SIM Interprets the Accumulator

HowSIMInterpretstheAccumulator

SIM and the Interrupt Mask

SIMandtheInterruptMask
Bit0isthemaskforRST5.5,bit1isthemaskforRST6.5
andbit2isthemaskforRST7.5
Ifthemaskbitis0,theinterruptisavailable
Ifthemaskbitis1,theinterruptismasked

Bit3(MaskSetEnable MSE)isanenableforsettingthe
mask
Ifitissetto0themaskisignoredandtheoldsettingsremain
g
g
Ifitissetto1,thenewsettingareapplied
TheSIMinstructionisusedformultiplepurposesandnotonly
forsettinginterruptmasks
ItisalsousedtocontrolfunctionalitysuchasSerialDataTransmission
Therefore,bit3isnecessarytotellthemicroprocessorwhetherornot
theinterruptmasksshouldbemodified

SIM and the Interrupt Mask

SIMandtheInterruptMask
TheRST7.5interruptistheonly8085interruptthathasmemory
IfasignalonRST7.5arriveswhileitismasked,aflipflopwill
rememberthesignal
WhenRST7.5isunmasked,themicroprocessorwillbeinterrupted
When RST7.5 is unmasked, the microprocessor will be interrupted
evenifthedevicehasremovedtheinterruptsignal
Thisflipflopwillbeautomaticallyresetwhenthemicroprocessor
responds to an RST 7.5 interrupt
respondstoanRST7.5interrupt

Bit4oftheaccumulatorintheSIMinstructionallowsexplicitly
resettingtheRST7.5memoryevenifthemicroprocessordidnot
respond to it
respondtoit
Bit5isnotusedbytheSIMinstruction

UsingtheSIMInstructiontoModify
theInterruptMasks
h
k
Example:
Example:Settheinterruptmaskssothat
Set the interrupt masks so that
RST5.5isenabled,RST6.5ismasked,and
RST7 5 is enabled
RST7.5isenabled
First,determinethecontentsoftheaccumulator

Triggering Levels
TriggeringLevels
RST7.5ispositiveedgesensitive
RST 7.5 is positive edge sensitive
WhenapositiveedgeappearsontheRST7.5line,a
logic1isstoredintheflipflopasapendinginterrupt
Sincethevaluehasbeenstoredintheflipflop,theline
h
l h b
d
h fl fl
h l
doesnothavetobehighwhenthemicroprocessor
checksfortheinterrupttoberecognized
Thelinemustgotozeroandbacktoonebeforeanew
interruptisrecognized

RST6.5andRST5.5arelevelsensitive
RST 6 5 and RST 5 5 are level sensitive
Theinterruptingsignalmustremainpresentuntilthe
microprocessorchecksforinterrupts

Determining the Current Mask Settings

DeterminingtheCurrentMaskSettings
RIMinstruction:ReadInterruptMask
RIM instruction: Read Interrupt Mask
Loadtheaccumulatorwithan8bitpattern
showing the status of each interrupt pin and mask
showingthestatusofeachinterruptpinandmask

HowRIMsetstheAccumulators
d ff
differentbits
b

The RIM Instruction and the Masks

TheRIMInstructionandtheMasks
Bits02showthecurrentsettingofthemaskfor
ts 0 s o t e cu e t sett g o t e as o
eachofRST7.5,RST6.5andRST5.5
Theyreturnthecontentsofthethreemaskflipflops
Theycanbeusedbyaprogramtoreadthemasksettingsin
ordertomodifyonlytherightmask

Bit3showswhetherthemaskable interrupt
processisenabledornot
ItreturnsthecontentsoftheInterruptEnableFlipFlop
Itcanbeusedbyaprogramtodeterminewhetherornot
interrupts are enabled
interruptsareenabled

The RIM Instruction and the Masks

TheRIMInstructionandtheMasks
Bits
Bits4
46
6showwhetherornottherearepending
show whether or not there are pending
interruptsonRST7.5,RST6.5,andRST5.5
Bits4and5returnthecurrentvalueoftheRST5.5and
RST6.5pins
Bit6returnsthecurrentvalueoftheRST7.5memoryflip
flop

Bit7isusedforSerialDataInput
Bit 7 is used for Serial Data Input
TheRIMinstructionreadsthevalueoftheSIDpinonthe
microprocessorandreturnsitinthisbit

Pending Interrupts
PendingInterrupts
Since
Sincethe8085hasfiveinterruptlines,
the 8085 has five interrupt lines
interruptsmayoccurduringanISRandremain
pending
UsingtheRIMinstruction,itispossibletoreadthe
status of the interrupt lines and find if there are
statusoftheinterruptlinesandfindifthereare
anypendinginterrupts

TRAP
TRAP
TRAPistheonlynonmaskable
st eo y o
as ab e interrupt
te upt
Itdoesnotneedtobeenabledbecauseitcannotbe
disabled

Ithasthehighestpriorityamongstinterrupts
Itisedgeandlevelsensitive
Itneedstobehighandstayhightoberecognized
Onceitisrecognized,itwontberecognizedagain
until it goes low then high again
untilitgoeslow,thenhighagain

TRAPisusuallyusedforpowerfailureand
emergency shutoff
emergencyshutoff

The 8085 Interrupts

The8085Interrupts
Interrupt
Name

Maskable

Masking
Method

Vectored

Memory

Triggering
Method

INTR

Yes

DI / EI
DI/EI

No

No

Level
S ii
Sensitive

RST5.5/
RST6.5

Yes

DI/EI
SIM

Yes

No

Level
Sensitive

RST7.5

Yes

DI/EI
SIM

Yes

Yes

Edge
Sensitive

TRAP

No

None

Yes

No

Level&Edge
Sensitive