PROJECT 1

CARRY LOOK AHEAD ADDER

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cla3 is
Port ( a : in STD_LOGIC_VECTOR (15 downto 0);
b : in STD_LOGIC_VECTOR (15 downto 0);
ci : in STD_LOGIC;
s : out STD_LOGIC_VECTOR (15 downto 0);
cout : out STD_LOGIC);
end cla3;
architecture Behavioral of cla3 is
component fa
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
ci : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end component;
signal g:std_logic_vector(15 downto 0);
signal p:std_logic_vector(15 downto 0);
signal z:std_logic_vector(16 downto 0);
begin
z(0) <= ci;
l:for i in 0 to 15 generate
g(i) <= a(i) and b(i);
p(i) <= a(i) xor b(i);
z(i+1) <= g(i) or (p(i) and z(i));
m:fa port map(a(i),b(i),z(i),s(i));
end generate l;

cout <= z(16);

end Behavioral;
TIMING DETAILS:
Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 6.67 secs
-->
Total memory usage is 307428 kilobytes
Number of errors :
Number of warnings :
Number of infos

0 ( 0 filtered)
0 ( 0 filtered)

: 16 ( 0 filtered)

RTL SCHEMATIC

SIMULATION RESULT:

PROJECT 2

CARRY SELECT ADDER:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity csa32 is
Port ( a : in STD_LOGIC_VECTOR (31 downto 0);
b : in STD_LOGIC_VECTOR (31 downto 0);
cin : in STD_LOGIC;
s : out STD_LOGIC_VECTOR (31 downto 0);
cout : out STD_LOGIC);
end csa32;
architecture Behavioral of csa32 is
component csa_block
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
cin : in STD_LOGIC;
s : out STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end component;
component rcgen
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
cin : in STD_LOGIC;
s : out STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end component;
signal Co:std_logic_vector(8 downto 1);
begin
L1:RCGEN PORT MAP(a(3 downto 0),b(3 downto 0),cin,s(3 downto 0),Co(1));
L:FOR i IN 1 TO 7 GENERATE

M4:csa_block PORT MAP(a((4*i+3) downto 4*i),b((4*i+3) downto 4*i),Co(i),s((4*i+3)

downto 4*i),Co(i+1));
END GENERATE L;
cout <= Co(8);
end Behavioral;

RTL SCHEMATIC

SIMULATION RESULT:

TIMING REPORT:
Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 3.73 secs
-->
Total memory usage is 239388 kilobytes
Number of errors :
Number of warnings :
Number of infos

0 ( 0 filtered)
0 ( 0 filtered)

: 0 ( 0 filtered)

PROJECT 3

CARRY SKIP ADDER

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cska is
Port ( a : in STD_LOGIC_VECTOR (15 downto 0);
b : in STD_LOGIC_VECTOR (15 downto 0);
cin : in STD_LOGIC;
s : out STD_LOGIC_VECTOR (15 downto 0);
cout : out STD_LOGIC);
end cska;
architecture Behavioral of cska is
component cskb
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);

b : in STD_LOGIC_VECTOR (3 downto 0);

cin : in STD_LOGIC;
s : out STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end component;
signal z:std_logic_vector(4 downto 0);
begin
z(0) <= cin;
l:for i in 0 to 3 generate
j:cskb port map(a(4*i+3 downto 4*i),b(4*i+3 downto 4*i),z(i),s(4*i+3 downto
4*i),z(i+1));
end generate;
cout <= z(4);
end Behavioral;
TIMING REPORT:
Total REAL time to Xst completion: 11.00 secs
Total CPU time to Xst completion: 10.80 secs
-->
Total memory usage is 265636 kilobytes
Number of errors :
Number of warnings :
Number of infos

0 ( 0 filtered)
0 ( 0 filtered)

: 0 ( 0 filtered)