Konstadinos Mourtziapis

Curriculum Vitae, update: February 23, 2015

Konstadinos Mourtziapis
Address: Mavrokordatou 98, Volos, Greece, 38221
Tel:+30 6984159335
Nationality: Greek
e-mail: conmourtz@hotmail.com
Skype: akonstanttinos
LinkedIn profile name : Konstadinos Mourtziapis

SUMMARY
I am a final year undergraduate Student at the Electrical and Computer
Engineering department of the University of Thessaly. My final year project is
on the VLSI design and fabrication of an AHB-lite slave circuit.

AREAS OF INTEREST
EDA/CAD tools (Simulation, Front-end, Back-end)
ASIC/SOCs
Low Power Design

TECHNICAL SKILLS & EXPERTISE

Full overview of the complete flow from RTL to GDSII using Synopsys,
Mentor Graphics and Cadence tools:
Cadence SOC Encounter(advanced level)
Cadence Incisive(working knowledge)
Cadence Virtuoso(working knowledge)
Synopsys Design Compiler(advanced level)
Synopsys Prime Time(working knowledge)
Synopsys TetraMAX ATPG(working knowledge)
Synopsys IC compiler(working knowledge)
Synopsys VCS(advanced level)
Mentor Graphics Questasim (advanced level)

Konstadinos Mourtziapis

Curriculum Vitae, update: February 23, 2015

Cadence Tempus(working knowledge)

Cadence Voltus(working knowledge)
Cadence Encounter RTL compiler(working knowledge)

Programming/Design Languages:
C, Verilog, Tcl.

Operating Systems:
Microsoft Windows, Linux.

Additional expertise on:

Mercurial, PSpice, Pcspim, Mars (MIPS Assembler and Runtime Simulator),
Gtkwave, Iverilog, Matlab, AutoCAD, Dotty (for FSM graph creation), ADS
(Advanced Design System), Xilinx ISE, ARM protocols (AXI, AHB), LaTeX.

EXPERIENCE
July 2014
present

Design and fabrication of AHB-lite slave, University of Thessaly, Greece

The goal is to design from ARM AHB-lite slave specs the circuit and write
the RTL code for it, complete the full flow (RTL to GDS II) and send for
fabrication. For the implementation of the SOC chip of AHB-lite slave (ARM
protocols) the EDA tools that used are: Mentor Graphics Questasim,
Synopsys VCS, Cadence Simvision (for simulation), Synopsys Design
Compiler (for synthesis) and Cadence SOC Encounter (for physical design
and the GDSII extraction). Other tools that used are: Synopsys Prime Time
(for more accurate timing results) and Synopsys TetraMAX-ATPG (for
testing the design after the fabrication process). The design kit that used
for the design was the AMS C35B4C3 (350nm).
Instructor: John Moondanos

February 2014
- June 2014

Teaching Assistant / Lab Assistant of VLSI course (CE330), University

of Thessaly, Greece
Assistant for lectures and laboratory, weekly meetings with students

July 2013
August 2013

EDA tools training (RTL to GDSII), University of Thessaly, Greece

Training on Cadence, Synopsys and Mentor Graphics EDA tools

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Konstadinos Mourtziapis
February 2013
- June 2013

Curriculum Vitae, update: February 23, 2015

Teaching Assistant / Lab Assistant of VLSI course (CE330), University

of Thessaly, Greece
Assistant for lectures and laboratory, weekly meetings with students

July 2012
August 2012

EDA tools server, University of Thessaly, Greece

Setting up the server of Synopsys, Cadence and Mentor Graphics EDA
tools for the department of Electrical and Computer engineering of
University of Thessaly, writing scripts to run EDA tools and update license
files and license server of the department.

FOREIGN LANGUAGES

Greek Excellent (native speaker)

English Excellent - Michigan ECCE

EDUCATION
2007 - present

Undergraduate Student of Computer and Electrical

Engineering, University of Thessaly, Greece.
Grade Expected: 7.2/10

PROJECTS
Analog VLSI lab : PLL construction (CE536):, University of Thessaly,
September
2014 - January Greece
2015
The aim of this project was to construct the PLL circuit on breadboard and
check its functionality. To achieve the following components used:
LM-565 integrated circuit
Resistors, Capacitors
Lab equipment:
1. Analog / Digital Oscilloscope
2. Adjustable Power Supply
3. Waveform Signal Generator
4. Multimeter
Instructor: Fotios Plessas
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Konstadinos Mourtziapis
February 2014
- June 2014

Curriculum Vitae, update: February 23, 2015

Analog VLSI: Simulation of phase locked loop (PLL) with modified

voltage controlled oscillator (VCO) (CE433), University of Thessaly,
Greece
The purpose of this project was to check PLL functionality by simulating it
with the Advanced Design System (ADS 2008.02). First, the PLL circuit was
designed on the ADS software and then the functionality of the circuit
checked by set values to the reference input and observing the graphs that
was extracted.
Instructor: Fotios Plessas

Arm microarchitecture for mobile devices: a case study

September
2013 - January (CE432), University of Thessaly, Greece
2014
The purpose of this project was to read some papers, presentations, specs
and make a brief presentation for them. The contents of this project are:
Basics on arm architecture
Description of ARM Cortex-A9 processor
Description of ARM Cortex-A15 processor
ARM Cortex-A9 processor VS ARM Cortex-A15 processor
Instructor: Georgios Dimitriou

February 2012
- June 2012

AXI to AHB bridge - VLSI project (CE330), University of Thessaly, Greece

The purpose of this project was:
Study ARM protocols (AXI, AHB)
Check the functionality of circuit using simulation tools (Gtkwave, Synopsys
VCS)
Synthesis the design using Synopsys Design Compiler with the optimal:
1. Power
2. Area
3. Delay
Instructor: John Moondanos

REFERENCES

References available upon request.

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