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CHNG 3
Register Transfer
Specification And Design
Register-transfer design
Each standard or custom IC consists of one or more
Example
Design Model
Ones-counter specification
FSDM Definition
In Chapter 6 we defined an FSM as a quintuple < S, I, O, f, h >
o where S is a set of states, I and O are the sets of input and output
symbols: f : S I S , and h : S I O
o More precisely, I
A = A1 A2 Ak
S = Q1 Q2 Qm
O = Y1 Y2 Yn
FSDM Definition
With formal definition of expressions and relations over a
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State-action table
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Algorithmic-State-Machine
Graphic representation of FSMD model
Equivalent to state-action table
Similar to a flowchart used for program description
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ASM Symbols
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ASM rules
Rule 1: The chart must define a unique next state for
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State-based table
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Input-based table
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S1= s4 =Q2Q0
S0 = s2 + s4 = Q1Q0 + Q2Q0
E = s3 = Q1Q0
Load =s1 = Q2Q1Q0
Done = Output enable = s5 = Q2Q0
State-based version
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Input-based version
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Bi tp
Vit lc gii thut ASM cho bi sau: S = 1 + 2 + 3 +
+n
Vit lc gii thut ASM cho gii thut sau:
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Bi tp
Thit k lc ASM cho b nhn mc vt l ca 3
thanh ghi:
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Bi tp
Chuyn lc trng thi sau sang lc gii thut
w = 1
w = 0
A z = 0
B z = 0
w = 0
w = 1
w = 0
C z = 1
w = 1
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Bi tp
Chuyn lc sau sang gii thut ASM mealy
Reset
w = 1 z = 0
w = 0 z = 0
B
w = 0 z = 0
w = 1 z = 1
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Bi tp
Cho lc ASM sau. Hy v li lc trng thi (xc
r1
1
gnt1
1
g1
r2
gnt2
g2
r3
r1
r2
1
1
gnt3
g3
0
r3
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Register-transfer synthesis
Register sharing
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Variable usage
Operation usage
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(i) Adder
(j) Subtractor
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Connectivity requirements
Connectivity table
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design
Two algorithms:
o left-edge
o graph-partitioning
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Left-edge algorithm
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Datapath schematic
ASM Chart
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R1 = [ a , t1 , x , t7 ]
R2 =[b , t2 , y , t3 , t5 , t6 ]
R3= [ t4 ]
Register assignments
Datapath
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Non-shared design
Shared design
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Datapath connectivity
(a) Datapath schematic for unit allocation from figure 8.22 (c)
ASM Chart
(b) Datapath schematic for unit allocation from figure 8.22 (e)
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R1 = [ a, t1, x, t7 ]
R2 = [ b, t2, y, t3, t5, t6 ]
R3 = [ t4 ASM
] Chart
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Chapter summary
We introduced RT design:
o FSMD model
o RT specification with
Static-action
ASM
tables
charts
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Bi tp
Ti thiu ha s lng thanh ghi s dng cho cc bin t
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Bi Tp
Gom nhm cc node bng gii thut th thch hp. Gi
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Bi Tp
Cho php ton S = 1 + 2 + 3 + + n. Thc hin cc
bc sau:
o Vit gii thut thc hin php ton trn.
o Chuyn m gi sang lc ASM (based state hoc based
input).
o S dng gii thut left-edge algorithm hin thc hin chia s
thanh ghi.
o S dng gii thut phn hoch th (partition graph) thc hin
chia s chc nng (Function unit).
o S dng gii thut phn hoch th (partition graph) thc hin
chia s bus.
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Bi tp
Vit chng trnh to datapath tnh tng a2i (i = 1 .. 100).
o Vit gii thut bng m gi.
o Chuyn m gi sang s ASM.
o Lp bng trng thi
o Chia s thanh ghi ?(nu c).
o Chia s chc nng ?(nu c).
o Chia s bus ?(nu c).