LPC2148 Training Manual

TKBase + 2148 D-Board

APPLIED DIGITAL MICROSYSTEMS PVT LTD

D-216, ANSA INDUSTRIAL ESTATE, SAKI VIHAR ROAD,
ANDHERI EAST, MUMBAI 400 072.
Tel: (91-22-)28470817, 66924483/4
Email: admltd@mtnl.net.in
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JAN 01- 2015

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Introduction to LPC2148 - ARM7 CPU Core

TKBase is a VLSI/P design laboratory training board aimed at enabling
engineering students to learn complete P to VLSI technology from startup single
chip microcomputer to a complex FPGA platform.
To get started learning and developing software for ARM microcontrollers like the
LPC2148, you will need at least the following four items:
1. TKBase development board with 2148 Daughter Board.
2. CrossWare Compiler with USB JTAG Programmer/Debugger (Jaguar)
3. LG320/LGLite Logic Analyzer & Pattern Generator.
4. LPC 2148 - UM10139 User Manual / LPC 2148 Training Manual
The TKBase serve as platforms for developing and testing software, learning
about debugging tools like compiler, debugger and logic analyzer. This manual
does not cover every detail about programming of LPC2148 processors, but the
exercises intend to introduce basic LPC peripheral programming concept.
Day
1
2
3
4
5
6
7
8

Description
Arm Architecture
LGLite Intro & Interface
Simulator - Assembly
Simulator C, Pointers
LED Flash Assembly & C
Peripheral Clock PLL
Timer Interrupt Handling
External Interrupt - Counting

Day
9
10
11
12
13
14
15
16

Description
UART Serial Comm.
Pusle Width Modulation
Real Time Clock
Digital to Analog (DAC)
Analog to Digital (ADC)
Mux 7 segment
LCD Interfacing
I2C / SPI Protocol I/F

1. Software:
Fundamental assembly/C language programming skills.
2. Hardware: Computer architecture, functional hardware components
3. Applications: Skills to interface a variety of Int/external devices
The fundamental components of any CPU are ALU and Register banks.
Arithmetic/Logic Unit: performs basic operations on data elements. Registers are
used for fastest storage of temporary variables.
1.
2.
3.
4.
5.

CPU governs order of instruction execution.

Controls access to memory and I/O devices.
Performs arithmetic and logical operations.
Handles interrupt services.
Contains: ALU, control unit, internal registers, timers, internal buses

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The LPC2148 microcontrollers are based on a 32/16-bit ARM7TDMI-S CPU with

real-time emulation and high-speed flash memory ranging of 512 kB.

ARM is unlike previous microcontrollers in that all peripheral functions are not
built in. Its up to the manufacturer to add everything outside of the CPU functions
All peripheral functional units are memory mapped and not part of core.

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The ARM7 is a load-and-store architecture, so in order to perform any data

processing instructions the data has first to be moved from the memory into a
register, the data processing instruction has to be executed and then the data
can be stored back into memory.

There is also a status register: CPSR, which contains a number of flags, which
latches and control the operation of the ARM7 core. The top four bits of the
CPSR contain the condition codes, which are set by the CPU. The condition
codes report the result status of a data processing operation. The ARM7 CPU is
capable of executing two instruction sets; the ARM instruction set which is 32 bits
wide and the THUMB instruction set, which is 16 bits wide and is reported by the
T flag. The ARM7 has seven different operating modes defined by the mode
bits.

When an exception occurs, the CPU will change operating mode and the PC be
forced to an exception vector. The vector table starts from address zero with the
reset vector and then has an exception vector every four bytes.

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One of the most interesting features of the ARM instruction set is that every
instruction may be conditionally executed. Every ARM instruction set has the top
four bits of the operand compared to the condition codes in the CPSR. If they do
not match then the instruction is not executed and passes through the pipeline as
a NOP (no operation).

The first four bits of an instruction are condition code and if its 1110(E) then this
instruction is not conditional and would be always executed. Bit 24 of the
Instruction is Link Bit and if this bit is set then R14 is loaded with the next
instruction address.

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Each instruction has a result register and two operands. The first operand must
be a register, but the second can be a register or an immediate value. ARM7
barrel shifter allows the second operand to be shifted by full 32- bits.

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All programming techniques (Assembly / C) fit into one of three templates:

1. Sequence
2. If-Then-Else
3. Do-While

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The System Control Block includes several system features and control registers
for a number of functions that are not related to specific peripheral devices.

The LPC2148 includes four External Interrupt Inputs as selectable pin functions.
The External Interrupt Inputs can optionally be used to wake up the processor
from Power-down mode.

There are two PLL modules in the LPC2141/2/4/6/8 microcontroller. The PLL0 is
used to generate the CCLK clock (system clock) while the PLL1 has to supply
the clock for the USB at the fixed rate of 48 MHz.

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If a peripheral control bit is 1 in PCONP register, that peripheral is enabled. If a

peripheral bit is 0, that peripheral is disabled to conserve power.

The VPB Divider determines the relationship between the processor clock
(CCLK) and the clock used by peripheral devices (PCLK).

There is one bank of Flash memory with Memory Accelerator Module (MAM).
Each Data access that is not in the Data latch causes a Flash fetch of 4 words of
data, which are captured in the Data latch. This speeds up sequential Data
operations. After reset the MAM defaults to the disabled state.

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LPC2148 supports three (3) different data types as shown below.

The workshop directory in LPC2148 contains Ten (10) Assembly programs.

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LGLite Pattern Generator drives TKBase Peripherals

This workshop displays a moving 1-bit pattern on the LED Bar display. (Ch1-8)

The first step is to configure LGLite 32 channels as Pattern output or Analyzer

input. For Interface experiments we set Channel Number 1 thru 16 as Pattern
Generator and Channel 17 thru 32 as Logic Analyzer.
We then go ahead to create a moving 1 pattern in the Pattern Generator Memory
using Pattern Generator Menu. We select the Left Shift Moving bit pattern and
with a width of 2 clock cycle. We then hit the execute button to create the pattern
in the RAM.
We then set the output speed of clocking to user step mode by selecting the
clock menu (6).
Now we have the pattern ready and the clock also set. We start running the
LGLite using the GO/RUN menu (7). As there is no user clock the Go Capture
dialog box opens up and we press the user step button. This button allows us to
output the pattern to TKBase LED module. Use LGTKB10 interface board from
LGLite and 10-core flat cable for connection.
Run the output using internal clock and see the output. Also capture the same
using a logic analyzer. Perform the same experiment with clock speed up to
25Mhz.
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LGLite Pattern Generator drives Multiplexed 7 Segment LEDs (CH 1-16)

Seven-segment devices are often preferred in display applications where high
luminescence is required, both for indoor and outdoor applications. Segments
are marked with letters: a, b, c, d, e, f, g and DP, where DP is the decimal point.
A 7-segment display consists of 7 LEDs arranged in a figure-eight pattern, and
then by selectively powering-on various combinations of segments, alphanumeric
characters with additional dot may be displayed. With a common cathode
display, the common cathode must be connected to the 0V rail and the LEDs are
turned on with logic one.

To display hexadecimal digits (0 thru F) on the 7 segment display. Use the

Pattern->Interface->7-Segment dialog box and press execute. This fills up the
Pattern RAM with hexadecimal data. Fill Channel 9-16 with data pattern 00. This
enables all the four hexadecimal display.
Repeat the experiment for displaying a 4 different hexadecimal digit using the
Pattern->Interface->Mux7Seg (5) menu. Watch the pattern in waveform window
to make conclusions.

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LGLite Pattern Generator drives LCD display. (CH 1-16)

The LCD display Module has an inbuilt processor. The processor has two 8-bit
registers, an instruction register (IR) and a data register (DR). The Register
Select pin (RS) logic level selects either the IR or DR register.
When pulled low (RS=0) it is used to send commands to the LCD (like position to
move to, or clear the screen). This is referred to as writing to the instruction or
command register. When RS pin is pulled high (RS=1) it can send data to the
display.
Once the RS pin logic level is set, then the Enable (E) pin should toggle high-low
to "clock in" the data that is on the data pins. The Read Write (RW) pin should be
held at logic low to write into the register.

Connect Channel 1 thru 8 to the LCD data bus and Channel 9-15 to the LCD control bus.
Run the LGLite Pattern Generator at 1Khz sampling speed and monitor the display on
LCD.

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LPC2148 Pin Configuration and Peripherals

Crossware Wizard for Peripheral programming

The Crossware Jaguar provides on-chip debug support. The debugging of the
target system requires a host computer running the Crossware software. Jaguar
converts the Remote Debug Protocol commands to the JTAG data needed to
access the ARM7TDMI-S core present on the target system for debugging.
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LPC2148 APB Peripheral

A Power Control for Peripherals feature allows individual peripherals to be turned
off if they are not needed in the application, resulting in additional power savings.
There are over 30 experiments introducing how to program in C and peripheral
interfacing.

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LPC2148 Pin connect block / GPIO use Wizard

The pin connect block allows selected pins of the microcontroller to have more
than one function. Configuration registers control the multiplexers to allow
connection between the pin and the on chip peripherals. Selection of a single
function on a port pin completely excludes all other functions otherwise available
on the same pin.
LPC2148 has two 32-bit General Purpose I/O ports. Total of 30 input/output and
a single output only pin out of 32 pins are available on PORT0. PORT1 has up to
16 pins available for GPIO functions. PORT0 and PORT1 are controlled via two
groups of 4 registers IOPIN, IOSET, IODIR and IOCLR.

LPC2148 Peripheral Clock & Phase Locked Loop (PLL)

The APB Divider determines the relationship between the processor clock
(CCLK) and the clock used by peripheral devices (PCLK).

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There are two PLL modules in the LPC2141/2/4/6/8 microcontroller. The PLL0 is
used to generate the CCLK clock (system clock) while the PLL1 has to supply
the clock for the USB at the fixed rate of 48 MHz. Structurally these two PLLs are
identical with exception of the PLL interrupt capabilities reserved only for the
PLL0

LPC2148 VIC User Wizard Very Important

The Vectored Interrupt Controller (VIC) takes 32 interrupt request inputs and
assigns them into 3 categories, FIQ, vectored IRQ, and non- vectored IRQ. Any
of the 32 requests can be assigned to any of the 16-vectored IRQ slots, among
which slot 0 has the highest priority and slot 15 has the lowest. The default
routine can read another VIC register to see what IRQs are active.

Following the completion of the desired interrupt service routine, clearing of the
interrupt flag on the peripheral level will propagate to corresponding bits in VIC
registers (VICRawIntr, VICFIQStatus and VICIRQStatus). Also, before the next
interrupt can be serviced, it is necessary that write is performed into the
VICVectAddr register before the return from interrupt is executed. This write will
clear the respective interrupt flag in the internal interrupt priority hardware.
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LPC2148 Timer use Wizard

The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or
an externally-supplied clock, and can optionally generate interrupts or perform
other actions at specified timer values, based on four match registers. It also
includes four capture inputs to trap the timer value when an input signal
transitions, optionally generating an interrupt.

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LPC2148 Pulse Width Modulation PWM

The PWM is based on the standard Timer block. The ability to separately control
rising and falling edge locations allows the PWM to be used for more
applications. Two match registers can be used to provide a single edge
controlled PWM output. One match register (PWMMR0) controls the PWM cycle
rate, while the other match register controls the PWM edge position.

LPC2148 UART
The LPC2148 features multiple serial interfaces including two UARTs (16C550),
with 16 byte FIFO, two Fast I2C-bus (400 kbit/s), SPI and SSP with buffering and
variable data length.

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The UART0 receiver block, U0RX, monitors RXD0, for valid input. The UART0
RX Shift Register (U0RSR) accepts bits via RXD0. The CPU passes it to the
UART0 RX Buffer Register FIFO to await access via the generic host interface.
The UART0 transmitter block, U0TX, accepts data written by the CPU and
buffers the data in the UART0 TX Holding Register FIFO (U0THR). The UART0
TX Shift Register (U0TSR) transmit the data via the serial output pin, TXD0.
The UART0 Baud Rate Generator block, U0BRG, generates the timing enables
used by the UART0 TX block. The U0BRG clock input source is the APB clock
(PCLK). The main clock is divided down per the divisor specified in the U0DLL
and U0DLM registers. Status information from the U0TX and U0RX is stored in
the U0LSR. Control information for the U0TX and U0RX is stored in the U0LCR.

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LPC2148 SPI
SPI is a full duplex serial interface with multiple masters and slaves being connected to a
given bus. Only the master device can control the clock line, SCK. During a data transfer
the master always sends 8 to 16 bits of data to the slave, and the slave always sends a
byte of data to the master.

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LPC2148 I2C-bus
There are two types of data transfers are possible on the I2C bus
1. Data transfer from a master transmitter to a slave receiver. The first byte
transmitted by the master is the slave address. Next follows a number of
data bytes. The slave returns an acknowledge bit after each received byte.
2. Data transfer from a slave transmitter to a master receiver. The first byte
transmitted by the master is slave address. The slave then returns an
acknowledge bit. Next follows the data bytes transmitted by the slave to
the master. The master returns an acknowledge bit after all received bytes
other than the last byte.

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LPC214x WDT
The purpose of the watchdog is to reset the microcontroller within a reasonable
amount of time if it enters an erroneous state. When enabled, the watchdog will
generate a system reset if the user program fails to feed (or reload) the watchdog
within a predetermined amount of time.

LPC2148 Real Time Clock

The Real Time Clock (RTC) is a set of counters for measuring time when system
power is on, and optionally when it is off. It uses little power in Power-down
mode. On the LPC214x, the RTC can be clocked by a separate 32.768 KHz
oscillator or by a programmable prescale divider based on the APB clock.

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LPC2148 ADC / DAC

It includes dual 10-bit successive approximation analog to digital converter. The
APB clock provides basic clocking for the A/D converters. A programmable
divider is included in each converter, to scale this clock to the 4.5 MHz (max)
clock needed by the successive approximation process. A fully accurate
conversion requires 11 of these clocks.

The ARM is a Reduced Instruction Set Computer (RISC) system. A load/store

model of data processing where operations are on registers and not in memory.

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LAB01:A Program in Assembly

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C Primer
The C programming language was developed at Bell Labs during the early
1970's. Quite unpredictably it derived from a computer language named B and
from an earlier language BCPL.
As a programming language C program stores values in variables. Programs are
structured by defining functions. Program flow is controlled using loops, ifstatements and function calls. Related data can be stored together in arrays or
structure.
C is a so-called a compiled language. This means that once we write our C
program, we must run it through a C compiler to turn our program into an
executable that the CPU can run (execute). The C program is the humanreadable form, while the executable that comes out of the compiler is the
machine-readable and executable form (i.e. a list of CPU instructions).
A normal way of working is to compile our .c files into .obj files and link those,
together with other .obj files in (one or more) .lib files. After linking the file
extension in embedded systems the resulting executable could be a .hex file (an
actual flash memory image).

In practice the .c files are the source code, but the file startup.asm is an
assembler module provided by Crossware. As its name implies, the startup code
is located to run from the reset vector. It provides the exception vector table,
initializes the stack pointer, on-chip system peripherals and the on-chip RAM
before it jumps to the main function in your C code.

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Every C program must have a main; it defines which statements to execute upon
startup of the program. Functions define a series of statements to perform. A
function groups these statements and gives them a name (the function name).
One could say that functions are like black boxes that can perform some trick.
Calling the function performs the trick.
Once we have built some code and got it running on an LPC2148 device, it will at
some point be necessary to access the special function registers (SFR) in the
peripherals. As all the peripherals are memory mapped they can be accessed as
normal memory locations. Each SFR location can be accessed by hardwiring a
volatile pointer to its memory location as shown below.

The Crossware compiler comes with a set of include files (LPC2148.h), which
define all the SFRs in the LPC2148.
In addition to accessing the on-chip peripherals, your C code will have to service
interrupt requests. It is possible to convert a standard function into an ISR, as
shown below:

A string is a sequence of characters enclosed in " (double quotes). The C

compiler stores all characters of the string (but not the enclosing quotes), and it
always appends a 0 (null).

As a programmer, we will frequently want our program to "remember" values (for

later use). The way our program remembers things is by using variables. Before
a variable can be used in a function, it must be declared. Declaration of variables
in a function must occur as the first lines.

C programs consist of functions, which consist of statements most of which

contain expressions. Expressions denote computations, the activity that gave
computers their name.

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An expression computes something, but it doesnt do anything. Statements on

the other hands are the things that actually do something.
Sometimes, a program needs to take different steps when a certain condition
holds. This is achieved with an if statement, also known as selection statement,
conditional statement, or branch statement.

C introduced data types integers, floating point, characters, and strings. These
types are known as standard types. C also provides means to build bigger types
from several smaller types, starting from these standard types.
The first major construct is called array; it is a series of objects of the same type.
The second major construct is a struct (i.e. a structure, also known as record); it
is a set of objects of multiple types. Structures in C allow us to group objects
(variables) of different type into one package.

Most languages allow one to create functions (subroutines, procedures) of some

sort. Functions let us chop up a long program into named sections so that the
sections can be reused throughout the program. It is even possible to group
popular functions into a separate C file(s) and convert them into a reusable
library.
Many coding conventions consider it good form to use function prototypes for all
functions in a program. A prototype declares the function signature, i.e. its name,
its parameters, and its return type to the rest of the program.

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LAB02: A Program in C: Introduction to Pointers

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LAB03: C Program: Comparator for a loop and Array

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LPC: System Peripherals (Most Example uses P0.0 - 8 bit Header)

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LAB 04:Flashing Lights (LEDs): Understanding Software Delay

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LAB05: Flashing LED: Compare C and Assembly Program

LAB06: Flashing LED: C Structure and Pointers for Flashing LEDs

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LAB07: Phase Lock Loop Boosting CPU Frequency to 60Mhz

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LAB08: Timer: Flashing LEDs using Timer and Timer Interrupt

LAB09: External Interrupt: Counting Key press using Interrupt

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LAB10: PWM: Single edge controlled PWM outputs

Pulse-width modulation is an effective method for adjusting the amount of power
delivered to an electrical load. A DC motor is given a fixed voltage value (say +5
V) and it starts spinning. The voltage is then removed and the motor "coasts". By
continuing this voltage on-off duty cycle, motor speed is controlled. Variables are
Duty Cycle & Period.
ALL PWM output goes high at beginning of PWM cycle.
Each PWM output will go low when its match value is reached, else high.

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LAB11: RTC: Understanding Operation of Real Time Clock

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LAB12: UART1: Understanding Serial Transmission

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LAB13: ADC: Understanding ADC1.1 working (P0.8)

ADC work by converting voltage to a numeric value which uC can understand.
For example, with an internal voltage of 3.3V (which is the Vref on the LPC2148)
and your ADC set to return the maximum 10-bit data (meaning you have possible
values between 0 and 1023), 0.0V would return 0, 3.3V (or higher) would return
1023, and 1.65V would return ~512.

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LAB14: DAC: Outputting DAC voltage to drive LED

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LAB15: STATE / Enumeration: How enum works for I2C

Trace the working of above function using new event as watch variable. Single step and
see how the variable changes state. This is very useful to understand working of I2C or
any state based protocols like USB or Ethernet. Monitor how do_event1 function changes
the state of the program. The state variable is maintained in new_event. I2C has to start
from a STOP state, Go to Start State, then to generate slave device Addr state, then
program the ADC control register to select one of the four ADC channel, this is the
Control state. Then go to stop state. The next state is to read the ADC conversion register.
Here again we go from Start, Addr, ADC with ack generation, ADC with nack generation
and then stop state.

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LAB16: SPI: Interfacing EEPROM - 25LC010A

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Trace the working of above routines by connecting serial port P0.8 and P0.9 to external
serial interface and flag magic terminal at 9600 baud. Pin P0,4,P0.5,P0.6, and P0,7 to
25LC010A eeprom. The system boots up with a prompt > and echos back any terminal
write . The sequence of operation is as follows:
1. Type a character on Terminal. The UART1 captures the data in variable
serial_val.
2. The serial_val data is then written to 25LC010A using function dev_write()
3. The 25LC010A is then read back using dev_read() function.
4. The read back data is then echoed back to the terminal .
5. The # command erases the entire EEPROM.

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Use LGLite to capture SPI frames. Set the trigger word with SCK=1 and CS=0
LGLite Trigger word (XXX0 XXX1)

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6. LAB17: I2C01: Interfacing External ADC - PCF8591

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