114

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 1, JANUARY 2006

Design Optimization of an Active Resonant

Snubber for High Power IGBT Converters
Frederik W. Combrink, Hendrik du T. Mouton, Member, IEEE, Johan H. R. Enslin, Senior Member, IEEE, and
Hirofumi Akagi, Fellow, IEEE

AbstractThe design optimization procedure for a new active

resonant snubber topology, specifically suited for high power insulated gate bipolar transistor (IGBT) converters, is introduced.
After the basic operation principles and certain implementation
consideration are discussed, the optimization strategy, based on an
analytical loss evaluation, is described. Experimental results obtained on an IGBT phase-arm fitted with an optimally designed
snubber are presented.
Index TermsActive resonant snubber topology, insulated gate
bipolar transistor (IGBT).

I. INTRODUCTION

ITH the availability of new high power insulated gate

bipolar transistor (IGBT) devices, power electronic
converters with ratings of several MVA are becoming feasible.
The maximum switching frequencies obtainable with these
converters are, however, limited due to excessive switching
losses and the associated thermal problems. In an attempt to
minimize these losses, various soft-switching topologies have
been introduced through the years. All of these topologies
offer some advantages in terms of reduced switching losses
and electromagnetic interference (EMI) improvements. Higher
switching frequencies are therefore obtainable with these
soft-switching schemes, resulting in better control bandwidth
and reduction in filter size. Disadvantages of these topologies
however include complicated circuitry, limitations on the control algorithms, increased current or voltage stresses on the
main converter switches and auxiliary switches with a high
peak voltage or current rating.
In [1], a new resonant turn-off snubber that makes use of
an auxiliary discharging circuit was introduced. This topology
forms part of a class of active resonant transition dc/ac converters known as auxiliary resonant pole (ARCP) converters [2],
[3]. One of the main disadvantages of this class of topologies
is that the auxiliary switches have peak current ratings that are
higher than the peak current rating of the main switches. The
proposed topology of [1] does not suffer from this disadvantage

Manuscript received September 11, 2003; revised May 19, 2005. This work
was presented in part at PESC00, Galway, Ireland. Recommended by Associate
Editor S. Bernet.
F. W. Combrink is with the Industrial Services and Solution Department,
Siemens Ltd., Johannesburg, South Africa.
H. du T. Mouton is with the Department of Electrical and Electronic Engineering, University of Stellenbosch, Matieland 7602, South Africa (e-mail:
dtmouton@sun.ac.za).
J. H. R. Enslin is with Kema, Raleigh, NC 27607 USA.
H. Akagi is with the Department of Electrical and Electronic Engineering,
Tokyo Institute of Technology, Tokyo 152, Japan.
Digital Object Identifier 10.1109/TPEL.2005.861199

Fig. 1.

Combined turn-on and turn-off snubber topology.

however and the peak current ratings of the auxiliary switches

are typically 30% of that of the main devices.
As a further step the integration of a turn-on snubber with
the existing resonant turn-off snubber was introduced in [4] and
[6]. The combination offers the full benefit of the reduction of
both turn-on and turn-off losses. The basic operation principles
and certain implementation consideration of the topology will
be discussed after which a design optimization strategy will be
described. The paper will be concluded with extensive experimental results obtained from a single-phase inverter fitted with
an optimally designed snubber.
II. BASIC OPERATION PRINCIPLES
In Fig. 1 the topology for the combined turn-on and turn-off
snubber is shown. The operation of the snubber for positive and
negative load current is totally symmetrical, therefore only posand
itive load current will be discussed. The values of
are equal and there will be referred to this value as
. The
inductor sets
and
and
and
will likewise be
and , respectively. For the purpose of dereferred to as
scribing the basic operation of the topology, a number of assumptions are made.
1) The main IGBTs, the auxiliary switches, and the diodes
are ideal. This implies that the transitions between states
are immediate and that there is no on-state voltage drop
across them.
2) All the passive snubber components are ideal.
3) All parasitic capacitance, inductance and resistance are
ignored.

0885-8993/$20.00 2006 IEEE

COMBRINK et al.: DESIGN OPTIMIZATION OF AN ACTIVE RESONANT SNUBBER

115

Fig. 2. Active parts of the combined snubber topology during different time intervals.

4) It is assumed that the output current remains constant

during a switching cycle.
5) An infinite dc bus is assumed.
6) A fixed blanking time is used in the converter.
The operation of the circuit is divided into different time intervals, as illustrated in Fig. 2.
Time interval
:
conducts the load current.
The top IGBT
:
Time interval 0
0
turns off instantaneously. The load current
At
is taken over by the top snubber capacitor
. The
voltage across the capacitor is given by
(1)
This voltage also appears across
and as a result the
main IGBT is switched off at a zero-voltage condition.
The time it takes for the voltage at the pole to swing from
the positive rail to the negative rail is a function of .
Depending on the magnitude of , two cases are posto reach the bus
sible. First, if the time necessary for
voltage is less than the blanking time of the converter, the
charging time can be calculated by

. The voltage across the snubber

where
capacitor during this period is given by

(5)
It is important to note that this voltage also appears across
and as a result extra voltage stresses on the main
IGBTs are introduced. The resonant cycle continues until
reaches zero and
turns off. At this
time when
instant the maximum voltage across the snubber capacitor
is also reached.
and
:
Time interval
and freeThe full load current is now carried by
wheeling diode
. This continues until
is switched
on again at time .
:
Time interval
, shifts to
The output current, which was carried by
at a rate determined by the value of the bus inductors.
The current through the top bus inductor, , can be expressed as
(6)

(2)

Time interval
:
At time the resonant cycle starts. The current in the
top bus inductor
is given by

This is also the current in , therefore the presence of the

inductance creates a zero-current turn-on condition for the
main IGBTs. The interval of current transfer between the
inductors comes to an end when the full load current is
at time .
taken over by
:
Time interval
Between times and the output current is carried
by
and
.
:
Time interval
, at time , starts
Triggering of the auxiliary switch
the resonant discharge cycle of the turn-off snubber capac. It is important to note that the auxiliary switches
itor
also turn-on at a zero-current condition due to the series
starts to discharge through
and
inductance.
is given by

(4)

(7)

becomes forward biAt , the free-wheeling diode

ased and a period of resonance between the bus inductors
and
) and the snubber capacitor
starts. If
(
is however too small to charge the snubber capacitor to
the bus voltage before the blanking time expires, the resis switched on. In this
onance cycle is started when
case is defined as equal to . The initial value of
at time can be expressed as

(3)

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Fig. 3. Simulation results for the combined snubber (V d

600 V,
20 kHz, t
5 s, C
150 nF, L
400 nH, L
10 H).

where
voltage across

. The corresponding
is given by

(8)
reaches zero.
The period comes to an end when
:
Time interval
reaches zero and is
At time the voltage across
clamped to that value by
. The current in
continues to decrease until it reaches zero at . For this pecan be expressed as
riod

(9)
:
Time interval
once again carries the full load current. The state of
the snubber is identical to the state for time smaller than
zero. The switching cycle will now start over again.
In Fig. 3, the operation of the topology is illustrated by simulated waveforms at two different magnitudes. These specific
magnitudes are chosen close to the boundary between case (1)
and (2) to demonstrate the difference between the cases.
III. IMPLEMENTATION CONSIDERATIONS
In the previous section, equations were derived to describe the
operation of the combined snubber under large and small output
current conditions [cases (1) and (2)]. This continuous discharge
of the snubber capacitor, without regard for the magnitude of
the output current, is not the only operation strategy that was
considered. In this section four possible operation strategies will
be described and evaluated.

1) Continuous snubber operation. Discharging of the

snubber capacitors even at low output current does have
the advantage of providing damping for voltage overshoot
as a result of extra bus inductance. This is especially important under large fault current conditions. The strategy
does however have a major disadvantage. At low positive
output current (case (2)) the blanking time expires before
is fully charged. The turn-on of
after the blanking
time expires will result in an excessive current in this device and the snubber capacitor and diode. The resonance
and the bus inductors will also result in
between
large voltage overshoot on the snubber capacitor and
.
This behavior can be observed in the simulation results
10 A) shown in Fig. 3. The
for small output current (
voltage stresses on the main devices will be the worst
at zero output current with voltage peaks equal to twice
the bus voltage. A possible solution to this problem is to
increase the blanking time according to the magnitude of
the output current. The nonlinearities introduced by this
scheme do however complicate control aspects.
2) Unidirectional charge assistance. To ensure that the
snubber capacitors are fully charged before the blanking
time expires, the charging can be assisted by means of
and
. One possible scheme is to
resonance with
just after
is switched off during periods
switch on
of both low positive and negative output current. The
,
and
that
result will be resonance between
will leave
charged and
discharged. Symmetrihas to be switched on just after
is switched
cally
off. This is equivalent to turn-off assistance of a normal
ARCP inverter.
3) Bidirectional charge assistance. As an alternative to unidirectional charge assistance, the auxiliary switches can
be expanded to have bi-directional current handling caduring periods of
pabilities. The charge assistance of
small positive current can then be achieved by resonance
and
without affecting
.
between
4) Discontinuous operation. Similar to the operation
strategy followed for the turn-off snubber topology in
[1], the discharge of the snubber capacitors can be discontinued at low output current conditions. With the total
absence of snubber capacitors extra voltage overshoot
across the main devices, due to bus inductors and parasitic capacitance resonance, can be expected. The snubber
capacitors, although not always discharged, will however
damp the voltage peaks as soon as the voltage rises high
and
. This will result in a
enough to forward bias
charge build-up on the snubber capacitors during periods
when the capacitor discharge is discontinued. However,
under normal operation the snubber capacitor voltage
increase, as a result of this charge build-up, is very small
(less than 10 V in the constructed experimental inverter)
and does not pose any problem for reliable operation.
Both unidirectional charge assistance and discontinuous
snubber operation strategies were verified experimentally, but
due to the simplicity of the discontinuous snubber operation
strategy it was used to obtain all experimental result presented
in Section VII.

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117

IV. EVALUATION OF LOSSES

In this section, the different loss mechanisms in the main devices and all the added snubber components are studied. To simplify the process two main assumptions are made.
First, although parasitic capacitive and inductive components
have a major influence on the effectiveness of the snubber (see
[5]), the dependence of these parasitics on actual component
values and snubber construction complicates modeling considerably. All parasitics are therefore ignored.
Second, tail-forming characteristics are assumed to model
both the turn-off and turn-on switching behavior of the main
devices and auxiliary switches [10]. For hard switching devices
this model is fairly accurate, but it does have a limitation in
predicting switching behavior of devices under soft switching
conditions. Although a number of detailed studies on the
switching behavior of IGBTs under soft switching conditions
can be found in the relevant literature [7], [8], the accurate prediction of the behavior of an IGBT under such conditions does
involve complicated simulations requiring device parameters
not readily available. The tail-forming switching characteristics
of the devices used to obtain the experimental results were
therefore measured under normal hard switching conditions
and it was then assumed that the addition of a snubber does
not alter this switching behavior of the main IGBTs. After
optimization and construction of the soft switching converter,
the modified switching behavior can again be measured and, if
necessary, the optimization process can then be repeated with
the adjusted parameters to obtain values that are more accurate.
The strategy followed to quantify losses in the main and auxiliary inverter components is to derive general analytical expressions to describe the losses in all these components. These expressions, which should be completely general, can then be used
to calculate the losses in the soft switching inverter for any combination of snubber component values and can then be used as
the basis of the optimization procedure.
In order to derive the general analytical expression describing
the losses in the inverter, the switching cycle will be separated
into three sections, namely the main IGBT turn-off cycle, main
IGBT turn-on cycle and snubber capacitor discharge cycle. The
possible cases that were considered for each of these sections
and the procedure of deriving expressions will now be described
for the three sections.
1) Main IGBT turn-off cycle. The collector current of
the main devices during turn-off is modeled by the
tail-forming characteristics described by

for

for

(10)

is the knee-point current,

is the current
where
fall duration and
is the current tail duration. Using this

Fig. 4. Equivalent circuits used for loss calculation: (a) main IGBT turn-off
cycle, (b) main IGBT turn-on cycle, and (c) snubber capacitor discharge cycle.

model, expressions for voltage and other current waveforms are then derived for the active parts of the snubber
circuit. To simplify these voltage and current expressions,
it is assumed that all snubber components and diodes are
ideal. However, to derive expressions for losses that can
be used in the optimization procedure, these simplified
current and voltage expression are used in conjunction
with more accurate models for the passive snubber components and diodes. This is illustrated by the equivalent
circuit used for loss calculations shown in Fig. 4(a). The
on-state voltage
and series resistance
of
the snubber diode are used to calculate the losses in
and
. The ESR of the bus inductors
and snubber
capacitors
are used to calculate the losses in
,
,
and
, respectively.
For discontinuous snubber operation, three cases are
considered at turn-off. In general it is necessary to derive
separate sets of loss expressions for the different cases
because the expressions for voltages and currents in the
circuit differ greatly. Simulation results at specific operating conditions illustrating the different cases are shown
in Fig. 5. To differentiate between the cases the capacitor voltage rise time
is defined as the time when
reaches
and
as the time when resonance between the bus inductors and
is completed. In case (1)
and
. For
case (2) the constraints on
are the same, but
. In case (3)
and
are both larger than
.

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Fig. 5. Different cases at main IGBT turn-off (t =

+t

).

Fig. 6. Different cases at main IGBT turn-on (t =

+t

).

2) Main IGBT turn-on cycle. The collector-emitter voltage

of the main devices during turn-on is modeled by the tailforming characteristics described by

for

for

3) Capacitor discharge cycle. The auxiliary switches in the

constructed experimental inverter are implemented with
a small IGBT in series with a diode for reverse voltage
blocking. The analysis is however general and applies
to metal-oxide semiconductor field-effect transistors
(MOSFETs), thyristors, and gate turn-offs (GTOs). The
collector-emitter voltage of the auxiliary switch during
the start of capacitor discharge is described by

(11)

is the knee-point voltage,

is the voltage
where
fall duration and
is the voltage tail duration. Similar
to the previous interval, parasitic components, nonideal
diode characteristics and the ESR of the bus inductors are
neglected when deriving voltage and current waveforms.
The complete equivalent circuit used for the loss calculations, together with the simplified expressions for voltages and currents, does however include these elements
and is shown in Fig. 4(b). The ESR of the bus inductors is used to calculate the conduction losses in
and
. Depending on the magnitude of the output current,
three cases are again possible. Simulation results at specific operating conditions, illustrating the different cases,
are shown in Fig. 6. The main IGBT current rise time
can be defined as the time when
equals . In case (1)
. For case (2)
. In
case (3)
.

for

for

(12)

the difference between the peak voltage overwith

shoot on the snubber capacitor during the main IGBT
turn-off and half the bus voltage.
is once again
the knee-point voltage,
is the voltage fall duration
and
is the voltage tail duration. The equivalent circuit used for the loss calculations is shown in Fig. 4(c).
The losses in all the passive components are calculated
by using their ESR values. The auxiliary IGBTs [for
] and series diodes are, respectively, modand
) and
eled by their on-state voltages (
on-state resistances (
and
).

COMBRINK et al.: DESIGN OPTIMIZATION OF AN ACTIVE RESONANT SNUBBER

119

TABLE I
EXPERIMENTAL CONVERTER OPTIMIZATION AND DESIGN PARAMETERS

Fig. 7.

Optimization results with L

= 12  H.

variables, that can potentially be included in the design optimization, therefore has to be made before optimization can start.
These choices, together with their potential influence if included
as a design parameter, are briefly discussed.

V. OPTIMAL SNUBBER DESIGN PROCEDURE

The aim of the optimal snubber design procedure described in
this section is to determine those snubber component values that
will result in the lowest overall losses in an inverter fitted with
the combined snubber. A number of papers on similar snubber
optimization can be found in the relevant literature [9][12].
Loss optimization of the topology is complicated by to great
number of variables that contribute to the design restrictions and
overall reduction in losses that can be ultimately achieved with
the topology. To simplify the process, the number of optimization variables considered will be restricted to only the passive
snubber component values. A choice of values for the other

1) Blanking time. Variation of the blanking time will result

in the variation of the required load current magnitude
to fully charge the snubber capacitors during this period.
This will influence the point where snubber operation, depending on the operation strategy followed, is stopped
or charge assistance is started. The minimum blanking
time will be determined by the switching behavior of the
main IGBTs. The nonlinearities introduced by excessive
blanking time will place an upper boundary upon . A
practical value suited for high power IGBT converters of
8 s was selected for the constructed inverter.
2) Switching frequency and maximum duty cycle. The
switching frequency and maximum duty cycle will determine the actual time available for the snubber capacitor discharge cycle. It will therefore also influence the
peak current rating of the auxiliary switches and will place
upper bounds on the snubber capacitor and resonant inductor values. A switching frequency of 7.5 kHz and a
duty cycle of 0.85 was selected as design parameters for
the experimental converter.
3) Maximum allowable voltage overshoot on main devices. The maximum allowable voltage overshoot will depend on the ratings of the main devices and the desired dc
bus voltage. Similar to a normal hard-switching inverter,
a maximum voltage overshoot during fault current con2 can usually be tolerated. This value was
ditions of
then also selected as the maximum permissible voltage
overshoot for the constructed converter.
4) Peak current rating of auxiliary switches. The peak current rating of the auxiliary switches is typically chosen to
to
. For an inverter with a lower
be
switching frequency and modulation index, an even lower
was selected
rating will be suitable. A value of
to demonstrate the advantage this topology has over the
basic ARCP converter.

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Fig. 8. (a) Comparison of theoretical models during main IGBT turn-off and (b) comparison of measured and theoretical waveforms during main IGBT turn-off.
600 V, I
180 A).
(V

5) ESR of snubber components as functions of their

value. In order to implement the optimization algorithm,
an estimate of the ESR for the passive snubber components as functions of their values should be determined.
It is assumed that the optimal snubber capacitor can be
implemented with a number of smaller capacitors in
parallel. The ESR of the snubber capacitors as function
of their capacitance is expressed as
(13)
where
is a constant. A specific type and specific base
size capacitor therefore has to be pre-selected. For both
the bus and resonant inductors ferrite cores are used to
minimize size and limit stray fields. During the optimization it is assumed that the same core size is always used
for a specific inductor. A suitable ferrite core size and material should therefore also be pre-selected. For every inductance value the required air gap, number of turns, conductor cross-section area and ESR is calculated. The core
losses are estimated using datasheet values at the resonant
frequencies of the relevant snubber components. These
pre-selected components for the experimental converter
of the next chapter are described in Table I.
The optimization procedure followed was to calculate the
total losses occurring in the soft switching converter over a fundamental modulation period for a specific combination of ,
and . For switching periods in the fundamental cycle with
snubber operations the derived expressions, discussed in the previous section, are used. For periods of small output current,
when the snubber is not operational, the turn-off losses in the
main devices can be estimated with datasheet values. The derived expressions for the turn-on losses are however still valid
for these periods.
This calculation of losses over a fundamental modulation period is then repeated over and over again with different combinations of snubber component values. In this process a three
dimensional matrix is constructed, with each point representing
a specific combination of snubber component values with an as-

sociated total power loss value. Every combination of snubber

component values is also checked against the maximum voltage
overshoot, maximum discharge time and peak current rating of
auxiliary switches constraints to ensure that the specific combination is valid. These limitations were pre-selected as described
in the previous chapter.
After completion of the optimization process, the constructed
matrix is searched to find the combination of snubber component values that result in the lowest overall losses over one fundamental modulation period. This combination is regarded as
optimal in terms of limiting total power loss in the topology.
VI. DESIGN OF EXPERIMENTAL INVERTER
A single-phase converter, fitted with the combined resonant
snubber, has been constructed using a standard 200 A, 1200 V
integrated power module. The optimization and design parameters of the inverter are listed in Table I. The result of the optimization procedure, as described in the previous section, sugIS 18 H. The pre-selected
gests that the optimal value of
ferrite core was however too small to implement this value and
the maximum inductance value possible at the required current
12 H. The difference between the total losses
levels was
achieved with this value and the optimal value is however only
12 H is
1%. In Fig. 7 the optimization results with
shown.
Combinations of snubber component values that violate one
or more of the constraints discussed in the previous section are
shown in Fig. 7 to have zero losses. The optimal values for the
12 H are
bus inductors and snubber capacitors with
calculated as 135 nH and 150 nF, respectively. In the practical
inverter these components were implemented as 130 nH and
165 nF.
VII. EXPERIMENTAL RESULTS
In this section, waveforms obtained from the experimental
inverter will be compared to theoretical models. Two theoretical models will be used for this comparison. The first model

COMBRINK et al.: DESIGN OPTIMIZATION OF AN ACTIVE RESONANT SNUBBER

121

Fig. 9. (a) Comparison of theoretical models during main IGBT turn-on and (b) comparison of measured and theoretical waveforms during main IGBT turn-on.
600 V,
180 A).
(

V =

I =

is as was used for obtaining expressions for voltages and currents in the snubber circuit for loss evaluation, as described in
Section IV. The second model is more complete and includes
full component models, as shown in Fig. 4, as well as parasitic resistance, inductance and diode reverse recovery behavior.
Waveforms during the main IGBT turn-off cycle and the main
IGBT turn-on cycle will be discussed. The section will be concluded with efficiency measurements.
waveforms for
during turn-off,
In Fig. 8(a) predicted
together with the collector current model, are shown. There are
two areas where the predicted waveforms are substantially different. The first major difference occurs during the current fall
than
time of where model 2 predicts a higher value for
model 1. This can be attributed to the voltage drop across the
parasitic snubber loop inductance due to the rapid increase in
snubber capacitor current during this period. This will result
in more turn-off losses than predicted by the loss evaluation
expressions derived in Section IV. The second area where the
two models differ considerably is during the resonance cycle
0.7 s). The effect of damping and the reverse recovery
(
are clearly visible in the predicted waveform of model
of
2. In Fig. 8(b), the measured waveform is compared to the prediction of model 2. Within the limitations of the approximate
collector-current and diode reverse recovery models, the correlation is good.
during main IGBT
In Fig. 9(a), predicted waveforms for
turn-on are compared. The model used for
is also shown.
the difference between the waveforms are negliFor
gible. This demonstrates that the effect of parasitic resistance
and stray inductance during the turn-on cycle is very small.
However, when becomes equal or bigger than , a significant
difference between the models is observed. Model 1, not taking
into account, keeps the collector curthe reverse recovery of
once it has reached that value.
rent constant and equals to
However, the collector current continuous to grow according to
.
model 2 in order to supply the reverse recovery current of
The reverse recovery of the free-wheeling diodes will therefore
result in more turn-on losses than predicted by the loss evalu-

Fig. 10. Comparison of measured and predicted waveforms during the reverse
at
135 A.
recovery of

I =0

ation expressions derived in Section IV. In Fig. 9(b), the meawaveform are compared to the prediction of
sured and
model respectively. The curmodel 2 and the tail-forming
rent waveforms correspond fairly well and it can be seen that the
turn-off voltage tail-forming model is relatively accurate, except
for the tail-bump in the measured waveform that is common
in soft-switching applications [7], [8].
Beside the extra losses introduced by the reverse recovery
of the free-wheeling diodes, it also causes dangerous charge
build-up on the snubber capacitors. In Fig. 10 this mechanism is
illustrated. Shown in Fig. 10 are predicted and measured voltage
during the reverse recovery of diode
waveforms across
(negative load current). Also shown are the measured collector
and
. After the collector current has reached
current of
the load current (around 200 ns), it continues to rise in order to
. After a further 50-ns
supply the reverse recovery current of
period the voltage across the diode
starts to grow until it
.
will then bereaches the snubber capacitor voltage
will be clamped to
. At that
come forward biased and
, that is also equal to the curstage the collector current of

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TABLE II
COMPARISON OF MEASURED AND CALCULATED
LOSSES IN EXPERIMENTAL INVERTER

extended to include parasitic components and diode reverse recovery behavior.

REFERENCES

rent in
, is still substantially larger than the load current. A
large portion of this extra energy store in the bus inductor will
, resulting in a voltage increase.
be eventually dumped in
is also not discharged through
During negative load current
resonance and this charge build-up will therefore continue for
half a fundamental modulation cycle. In the experimental inverter it was necessary to add 90 k bleeding resistor for the
snubber capacitors to limit this voltage rise to safe levels.
A calorimetric technique (similar to [13]) is used to determine the effect of the snubber on the total converter losses. The
total converter losses were measured at conditions specified in
Table I. In Table II, the results of these measurements are shown.
It should be noted that the predicted turn-off losses are calculated with a more complete model that includes parasitic components [5]. It can be seen that the measured losses in the inverter
fitted with the combined snubber is higher than predicted. This
difference can mainly be attributed to the extra turn-on losses
due to free-wheeling diode reverse recovery. Although not as
high as predicted, the measurements still suggest an improvement in total switching losses of 48%.
VIII. CONCLUSION
A design optimization strategy for a resonant snubber is introduced in this paper. The basic operation of the snubber is
investigated and certain implementation considerations are discussed. The procedure of deriving analytical expressions for the
different loss mechanisms is presented. An optimization procedure, based on the derived expressions, is developed. An experimental version of the topology, operating at a power level of
22 kVA, was constructed. It is observed that parasitic inductance
in the turn-off snubber loop reduce the efficiency of the turn-off
snubber significantly, while the reverse recovery free-wheeling
diodes introduce more turn-on losses. Efficiency measurements
on the experimental inverter show that the combined snubber reduces the switching losses by 48%. To improve the performance
of the topology further, the model used in optimization can be

[1] H. du T. Mouton and J. H. R. Enslin, A resonant turn-off snubber for

high power IGBT converters, in Proc. IEEE ISIE Conf., vol. 2, Jul.
1998, pp. 519523.
[2] W. McMurray, Resonant snubbers with auxiliary switches, IEEE
Trans. Ind. Appl., vol. 29, no. 2, pp. 355362, Mar./Apr. 1993.
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Frederik W. Combrink received the B.Sc degree

in physics and computer science and the B.Sc.Eng
and M.Sc.Eng degrees in electrical and electronic
engineering from the University of Stellenbosh,
Matieland, South Africa, in 1996, 1998, and 2001
respectively.
He joined the Industrial Services and Solution
Department, Siemens, Ltd., Johannesburg, South
Africa, in 2001 as a Systems Engineer for industrial
automation projects.

Hendrik du T. Mouton (S98M00) was born in

Bloemfontein, South Africa, in 1965. He received
the B.Sc (with honors), M.Sc., and Ph.D. degrees in
mathematics from the University of the Free-State,
Cape Town, South Africa, in 1986 and 1991, respectively, and the B.Eng degree and Ph.D. degree
in electrical engineering from the University of
Stellenbosch, Matieland, South Africa, in 1996 and
2000, respectively.
He is currently an Associate Professor in electrical
engineering at the University of Stellenbosch and
leader of the Power Electronics Research Group. In 2003, he was a Visiting Professor at LEEI, ENSEEIHT, Toulouse, France. He has authored and co-authored
a number of international journal and conference papers in mathematics and in
power electronics. His research interests include multilevel converters, utility
applications of power electronics, and digital audio amplifiers.

COMBRINK et al.: DESIGN OPTIMIZATION OF AN ACTIVE RESONANT SNUBBER

Johan H. R. Enslin (M85SM92) received the

B.Eng and M.Eng degrees in electrical and electronic
engineering and the D.Eng degree from the Rand
Afrikaans University (RAU), Johannesburg, South
Africa, in 1981, 1983, and 1988, respectively.
From 1982 to 1983, he was with the Department
of Electrical and Electronics Engineering, RAU.
He joined the Department of Electrical Engineering,
University of Pretoria in 1986, after some industrial
experience at the SA Railways and SA Signal Corps.
At the University of Pretoria, he also served as
Professor and permanent Head of Department for three years. From 1991 to
1999, he held the Chair of Energy Systems in the Department of Electrical
Engineering, University of Stellenbosch, Matieland, South Africa, and SAPSSI
Director at ESKOM. Since 2000, he has been with KEMA, first in Arnhem,
The Netherlands and later in Raleigh NC as Principal Consultant and System
Planning and Analysis Group Leader. He was previously a Visiting Professor
with Oregon State University, Corvallis and LEEI, ENSEEIHT, Toulouse,
France. He is involved in consulting and research work in several fields of
power electronics. He wrote and co-authored more than 200 international
papers, of which holds nine patents and presented several international short
courses.
Dr Enslin received seven Prized Paper Awards. He is a member of the South
African Institute of Electrical Engineers (SAIEE) and a Registered Professional
Engineer with the South African Council of Professional Engineers.

123

Hirofumi Akagi (M87SM94F96) was born

in Okayama, Japan, in 1951. He received the B.S.
degree from the Nagoya Institute of Technology,
Nagoya, Japan, in 1974, and the M.S. and Ph.D.
degrees from the Tokyo Institute of Technology,
Tokyo, Japan, in 1976 and 1979, respectively, all in
electrical engineering.
In 1979, he joined the Nagaoka University of Technology, Nagaoka, Japan, as an Assistant and then
Associate Professor in the Department of Electrical
Engineering. In 1987, he was a Visiting Scientist at
the Massachusetts Institute of Technology (MIT), Cambridge, for ten months.
From 1991 to 1999, he was a Professor in the Department of Electrical
Engineering, Okayama University, Okayama, Japan. From March to August of
1996, he was a Visiting Professor at the University of Wisconsin-Madison and
then MIT. Since January 2000, he has been a Professor in the Department of
Electrical and Electronic Engineering, Tokyo Institute of Technology. He has
published about 170 peer-reviewed journal papers, including about 70 IEEE
TRANSACTIONS papers and an invited PROCEEDINGS OF THE IEEE paper. He has
made presentations many times as a keynote or invited speaker internationally.
His research interests include power conversion systems, ac motor drives,
active and passive EMI filters, high-frequency resonant-inverters for induction
heating and corona discharge treatment processes, and utility applications of
power electronics such as activefilters, self-commutated BTB systems, and
FACTS devices.
Dr. Akagi received two IEEE IAS TRANSACTIONS Prize Paper Awards in
1991 and 2004, two IEEE PELS TRANSACTIONS Prize Paper Awards in 1999
and in 2003, nine IEEE IAS Committee Prize Paper Awards, the IEEE William
E. Newell Power Electronics Award in 2001, and the IEEE IAS Outstanding
Achievement Award in 2004. He was elected as a Distinguished Lecturer of the
IEEE IAS and PELS from 1998 to 1999.