Analog Integr Circ Sig Process (2014) 79:7381

DOI 10.1007/s10470-013-0241-5

A 0.5 V tunable complex filter for Bluetooth and Zigbee using

OTAs
Richa Arya George Souliotis Spyros Vlassis
Costas Psychalinos

Received: 18 June 2013 / Revised: 4 December 2013 / Accepted: 10 December 2013 / Published online: 24 December 2013
Springer Science+Business Media New York 2013

Abstract A 12th-order low voltage tunable differential

complex filter for bluetooth and Zigbee applications is
proposed in this paper. The filter is based on improved
controllable transconductors operating with the ultra-low
supply voltage of 0.5 V. Simulation results using a triplewell 0.13 lm CMOS technology verify the filter operation
fulfilling all the requirements for the complex filtering
stage in bluetooth or Zigbee receivers. The in-band group
delay variation is 0.79 ls for bluetooth and 0.46 ls for
Zigbee. The image rejection ratio is greater than 71 dB and
the achieved in-band spurious free dynamic range is 42 dB.
Keywords CMOS analog integrated circuits  Ultra-low
voltage filters  Gm-C filters  Complex filters  Bluetooth/
Zigbee filters

1 Introduction
Bluetooth and Zigbee are widely used protocols for shortrange wireless communication between portable devices.
In RF receivers several architectures are used, such as high
intermediate frequency (IF), low-IF or direct conversion [1,
2]. Among them, low-IF architecture seems to be the most
suitable in terms of on-chip integration and performance.
Unfortunately, the high-IF architecture needs an external
filter to satisfy the required high quality factor and the
direct conversion architecture suffers from local oscillator
(LO) leakage and dc offset. Also, the low-IF architecture is
preferable because it needs a relaxed rejection of the image
signal which comes from the down-conversion operation
R. Arya  G. Souliotis (&)  S. Vlassis  C. Psychalinos
Department of Physics, University of Patras, Patras, Greece
e-mail: gsoul@physics.upatras.gr

[2]. The image frequency signal and the IF desired signals

are close to each other and therefore the first must be
removed after the down-conversion and before processing
of the desired signal. Unfortunately, due to their symmetric
response around dc, real filters are unable to remove image
signal. Several techniques, like the Hartley architecture, the
Weaver architecture, passive RC polyphase filters, active
polyphase filters [3, 4], and the complex RDADC architecture [5] are some potential options for on-chip image
rejection, but complex filters seem to be the most promising solution [6].
Complex filters use the I and Q (quadrature) signals
which are extracted after the down-conversion of the
modulated RF signal, by means of an LO which offers two
phases 0 and 90 of the same frequency xLO [79]. The
concept is shown at the block diagram of Fig. 1. The
complex filter rejects the image signal in the frequency of
x = -xIF while applies a selection mask around the frequency x = xIF for the desired signal.
A 12th-order Butterworth complex filter, easily reconfigurable, for Bluetooth and Zigbee applications is proposed in this paper. The Butterworth approximation is
preferred because it has small group delay variation within
pass-band and all poles have same angular frequency
leading to better matching in cross-coupled OTAs in the
entire filter [6]. The poles of a Butterworth lowpass filter
(LPF) with cut-off frequency xc are evenly spaced around
the circumference of a half-circle of radius xc centered
upon the origin of the s-plane. The proposed filter operates
in ultra-low supply voltage, making it ideal for portable
devices. Low voltage operation is very important in circuits
used in the portable devices [10] helping to reduce their
size, the power consumption and having extended operating life time without frequent battery recharging. To this
direction, some topologies of complex filters based on

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74

active RC bi-quads [10], current mirrors [11, 12], second

generation current conveyors [13], have been proposed.
Other topologies use quadrature receivers with gm-C filters
[14], gyrator lowpass filters [15], log domain filters [16],
and current feedback operational amplifiers [17].
The proposed filter is based on tunable low-voltage
operational transconductance amplifiers (OTA) [18], it has
no resistors and the center frequency and bandwidth are
orthogonally tunable. Although a gm-C filter based on that
transconductor has been presented in [19], the differential
transconductor used in the proposed realization has been
extensively modified due to the particular requirements for
the complex filter. The most important is that the complex
filters require transconductors with large transconductance
range which must cover all the time-constants variations of
the filter stages. Also, a double-input differential transconductor is required to realize a signal summation. This
filter meets the requirements for a complex filtering stage
in a Bluetooth and Zigbee receiver. The most important
benefit is the operation with the extremely low supply
voltage (VDD) of 0.5 V, although it is designed with a triple-well 0.13 lm CMOS process that offers relatively high

Fig. 1 Front-end stage block diagram of low-IF receiver using a

complex filter

Fig. 2 Lossy complex

integrator

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Analog Integr Circ Sig Process (2014) 79:7381

threshold voltage. The paper is organized as follows: in

Section II the concept of the complex filter is presented, in
Section III the employed low voltage OTA is described in
details and in Section IV the analysis of the proposed filter
and the simulated results are given. Also, a performance
comparison with relative published complex filter topologies is performed.

2 General concept of complex filtering

The block diagram of the front-end of a low IF receiver,
using a complex filtering is shown in Fig. 1. In this
receiver, the RF signal is mixed with the quadrature signal
of LO, in order to produce a complex signal. Complex
bandpass filter acting as a frequency shifted version of a
LPF, passes the desired signal at x = xIF, and attenuates
the image at x = -xIF.
The topologies of complex lossy and lossless integration/summation blocks based on transconductors are shown
in Figs. 2 and 3, respectively. The differential configuration is preferred for improving the performance in terms of
noise interference rejection.
Considering that xi = (vI1I? - vI1I- ? vI2I? - vI2I)
? j (vI1Q? - vI1Q- ? vI2Q? - vI2Q-) and xo = (vOI? vOI-) ? j (vOQ? - vOQ-) and after a routine analysis for
the circuit in Fig. 3, it is obtained that,


xo
xIF
xOI
xII 
xO
1a
s xo
xo Q


xo
xIF
x IQ
xO
1b
xOQ
s xo
xo I
where, xo = C/gmo and xIF = xo(gmIF/gmo).

Analog Integr Circ Sig Process (2014) 79:7381

75

Fig. 3 Lossless complex

integrator

ITA

I2 I +

In2+

I2 I -

In2-

gmo

O I+

O+
O-

O I-

C
In+

In-

gmIF

ITB

ITA

In1+

I1 Q -

In1-

I2 Q +

In2+

I2 Q -

In2-

gmo

Tuning currents ITA, ITB and ITC in Figs. 2 and 3 are used
to control the transconductance value of each transconductor as given by 2a2c,
gmo 2ITA = nVt

2a

gmIF 2ITB = nVt

2b

gmo0 2ITC = nVt

ITB

gmIF

O+

O-

I1 Q +

O-

In1-

In-

I1 I -

O+

In1+

In+

I1 I +

O-

O Q-

VDD
Vf.p
vp1

Inv1

Vf.n

io1
von

VDD

2c

where, n is the slope factor and Vt = kT/q is the thermal

voltage. The bandwidth and the center frequency of the
filter are controlled by gmo and gmIF. Although the transconductance gmo has the same value with the value of gmo,
the ability for independent control through the current ITC
can be used for compensation reasons.

O Q+

O+

Vf.p
vp2

Inv2

Vf.p
VDD

VDD VDD

Vf.p
VDD

Vf.n
Inv6

Inv5

Inv8

Inv7

VDD
Vf.p
Inv3

vn1

Vf.n

2.1 Low voltage differential transconductor

Vf.n

Vf.n
vop

VDD

The 1st-order complex blocks are realized by a modified ultralow-voltage differential OTA, based on the principle of Nautas transconductor [20]. In the modified configuration [18,
19] shown in Fig. 4, the transconductor is bulk-controlled,
through negative feedback loops incorporated into control
circuit, and it is constructed by inverters operated in weak
inversion region. This offers (a) low-voltage capability,
because cascode devices for tuning purposes are avoided and
(b) linear control of transconductance. The bulk terminals of
the transistors are not constant biased as in conventional circuit topologies, but they are used to adjust their quiescent
point. Inverters Inv1Inv4 form the double input differential
transconductor, inverters Inv5, Inv8 form the differential

io2

Vfp
Inv4

vn2

Vf.p
IT
Vfn

Vf.n
Control
circuit

Fig. 4 The modified transconductor

output load and inverters Inv6, Inv7 form the common mode
(CM) output load. All inverters are controlled through the bulk
voltages Vfp and Vfn which are generated by a suitable control
circuit using a control current IT, as it will be explained later.
Although in the original OTA [18] two different tuning

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Analog Integr Circ Sig Process (2014) 79:7381

Fig. 5 Schematic diagram of

the proposed technique

circuits allow better control over frequency and Q tuning, in

this filter only one tuning circuit is used in order to reduce the
power consumption and the area of the filter.
The transconductance control methodology is based on
the masterslave technique using the control circuit which
is shown in Fig. 5. The CMOS inverter which is formed by
Mp.s and Mn.s, is the slave or active transconductor element
in which the input voltage Vin is applied. The CM input
voltage is equal to middle supply (VDD/2) for achieving the
maximum voltage swing. The bulk terminals of both
transistors are modified by the control circuit generating
the voltages Vfp and Vfn which are appropriately adjusted in
order to bias the slave inverter with the desired quiescent
current. Transistors Mp.mMn.m and Mp.sMn.s are the
master and the slave devices, respectively. The aspect
ratios of the master devices are scaled down m times
compared with the corresponding slave devices to minimize the area and current consumption. Therefore, the
quiescent drain currents IDS,p(n),s of the slave devices are
m times larger (m.IT) than IDS,p(n).m of the master devices
which are both equal to IT.
Eventually, using this approach the transconductances
gm.p.s and gm.n.s of Mp.s and Mn.s, respectively, can be
adjusted by means of the controlling current IT. The feedback loops ensure also, that the output CM voltage is kept
constant, equal to VDD/2 and independent from the value of
IT. Concluding using this tuning technique both inverterss
quiescent current and output dc level are simultaneously
defined.
According to the above considerations and assuming
that all transistors operate in weak-inversion the transconductance of the slave inverter will be equal to,


gm:s gm:p:s gm:n:s ID;p:s ID;n:s =nVt
3
2mIT =nVt
where, gm.p.s, gm.n.s are the transconductances and ID,p.s,
ID,n.s are the quiescent drain currents of the Mp.s and Mn.s,
respectively, shown in Fig. 5. Also, n is the slope factor of
the weak inversion IV characteristic and Vt is the thermal

123

Fig. 6 Passive 6th-order filter

voltage. Then, the differential output current of the

transconductor in Fig. 4 can be found as,
idif io1  io2 vin:dif gm:d
vp1  vn1 vp2  vn2 gm:s

Details about the differential amplifier employed in

Fig. 5 are presented in [18]. Based on Fig. 5 the constant
voltage of VDD/2 is applied to the inverting inputs of the
differential amplifiers (amp) in the master circuit, while the
feedback loops ensure that the non-inverting inputs of the
differential amplifier will be locked at VDD/2, generating
also, the bias voltages Vfp and Vfn.
For extremely small ratios VDD/VTH, where VTH is the
threshold voltage, MOS devices operate deep in the subthreshold region. Therefore, the linearity of the proposed
transconductor is similar to a conventional differential pair
with weak-inverted MOS transistors. On the other hand, the
linearity performance can be improved as the bias current
increases. So, a trade-off between linearity and current
consumption should be fulfilled in order to meet the filters
specifications.
3 Filter design and simulation results
The 6th-order passive prototype filter used for the design of the
complex filter is shown in Fig. 6. The normalized element
values for the 6th-order Butterworth function are C1p = 0.518F,
L2p = 1.414H, C3p = 1.932F, L4p = 1.932H, C5p = 1.414F,
L6p = 0.518H and the transfer function is given by,
H s

s6

3:86s5

7:46s4

1
9:14s3 7:46s2 3:86s 1
5

Analog Integr Circ Sig Process (2014) 79:7381

The signal flow graph for the complex filter designed

following the leapfrog technique is shown in Fig. 7. The
final 12th-order filter is realized by employing the complex
lossy and lossless integrators of Figs. 2 and 3, as depicted
in Fig. 8. Each transconductor in the filter, takes a suitable
transconductance so that gmo = xLOC and gmIF = xIFC.
To verify the operation of the proposed filter, the circuit
was designed and simulated using a triple well 0.13 lm
CMOS process. The supply voltage was VDD = 0.5 V and
the power consumption 2.77mW. The important point to
this is that transistors with a normal threshold voltage (VTH)
have been used in the simulations and not the recently
offered low VTH transistors. The capacitors of the filter in
Fig. 8 have values C1 = C6 = 0.6C, C2 = 1.6C,

77

C5 = 1.7C, C3 = C4 = 1.9C, where C = 180pF for

Bluetooth and C = 90pF for Zigbee. Although the capacitors C2 and C5 should be identical, they are slightly different to compensate internal parasitic capacitances which
affect the response of the filter. Switching from Zigbee to
Bluetooth is easily realized by enabling capacitors through
a suitable capacitor bank.
The tuning current in Figs. 2 and 3 was ITA = 12.7 lA
for the input transconductors and for the feedback transconductor in Fig. 2 was ITC = 12.7 lA. The transconductors used for cross coupling have three different tuning
currents (ITB) in all six stages. The relationship between the
particular ITB in each stage of the filter, approximately, is
following the ratio of the normalized element values of the

Fig. 7 Signal flow graph of a complex leapfrog filter

Fig. 8 12th-order complex filter

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Fig. 9 Frequency response for signal and image for Bluetooth filter

Analog Integr Circ Sig Process (2014) 79:7381

Fig. 11 IIP3 Curve for in-band linearity for Bluetooth filter

Table 1 Performance characteristics of the proposed complex filter

Fig. 10 Group delay for Bluetooth filter

passive filter. So, the tuning current for the six stages are,
ITB for the 1st and 6th stage, 3.2ITB for 2nd and 5th stage,
and 4ITB for 3rd and 4th stage, where ITB = 13.8 lA.
The aspect ratio of transistors of the transconductor in Fig. 4
were (W/L)p.s14 = 100/0.2 lm, (W/L)n.s.14 = 50/0.2 lm for
Inv14, (W/L)p.s.58 = 100/0.2 lm, (W/L)n.s.58 = 50/0.2 lm
for Inv58. In Fig. 5, the aspect ratio of the transistors are (W/
L)13 = 100/0.5 lm, (W/L)4,5 = 30/0.2 lm for the amplifier.
Scale factor was m = 1, the bias current was IB = 1 lA, and
supply voltage was 0.5 V.
Simulated results at schematic level have been taken for
Bluetooth and Zigbee. Postlayout simulations would provide more realistic information about the effect of parasitics on the filter performance. Taking into account the
absence of the transconductors internal node parasitics and
the fact that the filter is electronically tunable, the schematic level simulation results provide reasonable information about the behavior of the filter in a real
implementation. The most important behavior factor in low
frequencies is the effect of MOS transistors mismatch and

123

Performance factor

Bluetooth

Zigbee

Supply voltage VDD (V)

0.5

0.5

Power dissipation (mW)

2.77

2.77

Current consumption (mA)

5.54

5.54

Center frequency fIF (MHz)

Bandwidth (MHz)

1
1

2
2

In-band group delay variation (ls)

0.8

0.46

Spot noise (V/sqrt(Hz) at center frequency

59.7n

55.3n

Output noise (lVrms)

15.96

21.09

IRR (dB) at center frequency

71.90

72.58

1st blocker attenuation (fIF ? Df) (dBc)

35.35

38.88

2nd blocker attenuation (fIF ? 2Df) (dBc)

72.84

74.50

3rd blocker attenuation (fIF ? 3Df) (dBc)

93.92

95.45

In-band IIP3 (dBm)

-4.4

-4.65

Out-of-band IIP3 (dBm)

9.74

6.15

In-band SFDR (dB)

43.84

42.26

Out-of-band SFDR (dB)

53.27

49.36

CMRR (dB) at center frequency

101.12

101.35

PSRR (dB) at center frequency

-44.34

-44.34

process parameters variations and this will be studied in the

next.
The bandwidth and center frequency were 1 and 2 MHz
for Bluetooth and Zigbee, respectively. The frequency
response for the Bluetooth configuration is shown in Fig. 9.
The image rejection ratio (IRR) of the filter is better than
70 dBc for both filters in their center frequency, and the inband group delay variation is 0.8 and 0.46 ls for Bluetooth
(shown in Fig. 10) and Zigbee, respectively. The filter has
in-band 3rd-order intercept point (IIP3) -4.4 dBm, as
shown in Fig. 11, and in-band spurious free dynamic range
(SFDR) better than 42 dB. Output integrated noise for
Bluetooth is 15.96 and 21.09lVrms for Zigbee. For both
Bluetooth and Zigbee, the common-mode rejection ratio

Analog Integr Circ Sig Process (2014) 79:7381

79

Fig. 12 Center frequency tuning for Bluetooth filter

Fig. 15 Bandwidth variation for the Bluetooth filter

Fig. 13 Bandwidth tuning for Bluetooth filter

Fig. 14 Frequency response variation for Bluetooth filter

(CMRR) is better than 101 dB at center frequency and

power supply rejection ratio (PSRR) is better than
44.43 dB. In Table 1 the filters performance characteristics for Bluetooth and Zigbee are summarized.

The center frequency and the bandwidth of this filter are

orthogonally tunable. The center frequency can be controlled by the current ITB. By changing the current from 10
to 30 lA, the center frequency is varied in the range from
0.84 to 1.22 MHz for Bluetooth as shown in Fig. 12 and
from 1.64 to 2.35 MHz for Zigbee. Also, the bandwidth
can be controlled by the current ITA. The current ITC is kept
equal to ITA to achieve a constant gain response. By
changing the current ITA from 10 to 22 lA, the bandwidth
is varied in the range from 0.78 to 1.72 MHz for Bluetooth
for ITB = 13.8 lA, as shown in Fig. 13. The bandwidth is
varied in the range from 1.56 to 3.72 MHz for Zigbee for
ITB = 13.8 lA.
In order to examine the influence of the process and
mismatch variations on the cutoff frequency of the filter,
Monte Carlo simulation are performed. The mean value is
at 1.002 MHz for Bluetooth and 1.991 MHz for Zigbee,
with a standard deviation r = 17.9 kHz for Bluetooth and
r = 35.4 kHz for Zigbee. The variation of frequency
response for the Bluetooth filter is shown in Fig. 14 and the
deviation of the center frequency in Fig. 15.
The parameters of this filter are compared with recently
published complex filters which are resistorless and operate
in low supply voltage, lower than 1.2 V. The comparison
results are summarized in Table 2. The proposed filter has
the lowest supply voltage of 0.5 V, dissipates significantly
less power and also shows the highest IRR. On the other
hand, SFDR is comparable with other works. The disability
for improving SFDR is probably the cost paid for the low
supply voltage with the good power consumption. Some
other topologies, not shown in the comparison table, may
show improved SFDR but all of them operated under
higher supply voltage. Finally, the improved CMRR make
the proposed filter a good choice for common noise
rejection.

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Analog Integr Circ Sig Process (2014) 79:7381

Table 2 Comparison with recent works

Performance factor

This work

[14]

[16]

[17]

Technology CMOS (lm)

0.13

0.09

0.35

0.35

Order

12

12

12

Type

gm-C

gm-C

Log-domain

Active RC

Supply voltage (V)

0.5

1.2

1.2

1.2

Power consumption (mW)

2.77

3.6

10.9LF/15.4W

Center frequency (MHz)

1BT/2ZB

Bandwidth (MHz)

0.51.5 (and 13)

BT

In-band group delay (ls)

0.8 /0.46

Input Ref. noise (lVrms)

69BT/90ZB

ZB

5.6
0.92BT/1.9ZB

(IF band 13 MHz)

1.542.50LF/1.592.40W

0.92BT/1.9ZB

1BT/0.5ZB

260

BT

ZB

71.9 /72.6

[45.7 /[46.1

1st blocker attenuation

(fIF ? Df) (dBc)

BT

ZB

35.3 /38.9

37

2nd blocker attenuation

(fIF ? 2Df) (dBc)

72.8BT/74.5ZB

73.5BT/71.5ZB

3rd blocker attenuation

(fIF ? 3Df) (dBc)

93.91BT/95.4ZB

94.5BT/91ZB

In-band IIP3 (dBm)

-4.4BT/-4.65ZB

-12.5 (prototype I)
-13 (prototype II coil free)

In-band SFDR (dB)

43.84BT/43.67ZB

55.5 (prototype I)

36.9LF/36.7W at 1.950 and 2.050 MHz

45BT/44ZB
50.2BT/47.6ZB

Image Rejection ratio (dB)

LF

41BT/40ZB

54.4 (prototype II coil free)

BT

ZB

Out-of-band SFDR (dB)

53.27 /49.36

49LF/43.2W

Independent tuning of center

frequency and BW

Yes

No

No

at 3 and 6 MHz
No

BT Bluetooth, ZB Zigbee, LF leapfrog, W wave

4 Conclusion
In this paper a 12th-order differential complex filter which
is suitable for Bluetooth and Zigbee protocol implementations is described. Employment of an improved low
voltage transconductor allows operation with supply voltage as low as 0.5 V. The filter meets the requirements for a
complex filtering stage embedded in Bluetooth or Zigbee
receivers. Also, it has the ability of independent tuning of
center frequency and bandwidth, it shows low power
consumption, and reasonable performance in terms of
noise, image rejection and linearity.
Acknowledgments This research is financially supported by Greek
State Scholarship Foundation (IKY).

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Richa Arya was born in Muzffarnagar, Uttar Pradesh, India in

1983. She received her B.Sc.
degree in 2003 and M.Sc.
degree in 2005, both in Physics,
from M.J.P. Rohilkhand University, Bareilly, India. She has
worked as a Part-time Lecturer
in Vardhman College, India
from 20052007. She had
earned scholarship from State
Scholarship Foundation (IKY)
for post-graduate studies in
2009. She is currently a PhD
candidate in the Electronics
Laboratory of University of Patras. Her current research interests
include VLSI circuits, analog filter design, Complex filters, gm-C
filter, Low voltage devices.
George Souliotis received the
B.Sc. degree in Physics from the
University of Ioannina, Greece
in 1993 and the M.Sc. and Ph.D.
degrees in Electronics from the
University of Patras, Greece, in
1998 and 2003, respectively. He
has been with international and
startup companies, designing
high-speed circuits for electronic systems. From 2002, he
serves as an part time Adjunct
Lecturer at the Department of
Electrical Engineering, Technological Educational Institute of
Patras, Greece. From 2004 to 2008 he worked as a Post-Doctoral

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Researcher with the Department of Physics, University of Patras,
Greece. He is currently a member of the technical staff of the
Department of Physics, University of Patras, Greece. Dr. Souliotis has
30 papers in international journal and conferences and holds an
international patent. He serves as a reviewer for many international
journals and he is a member of national and international professional
organizations. His research interests include analog and mixed-signal
integrated circuits for high-speed communication applications, current mode circuits, continuous time active filters and CMOS-BiCMOS VLSI design.
Spyridon Vlassis received the
B.Sc. in Physics in 1994, the
M.Sc. degree in Electronic
Physics in 1996 and the Ph.D.
degree in 2000, from Aristotle
University of Thessaloniki,
Greece. He was working as
senior engineer for VC funded
startup companies in the development and commercialization
of high-performance RFICs for
wireless communications and
RF MEMS for consumer applications. He has published over
50 papers in journals and conferences and holds one U.S. patent. He is currently Associate professor with Electronics Laboratory, Department of Physics.
University of Patras, Greece. His research interests are in analog and
RF integrated circuits and high-speed inter-chip interfaces.
Costas Psychalinos received
B.Sc. degree in Physics and
Ph.D. degree in Electronics
from the University of Patras,
Greece, in 1986 and 1991,
respectively. From 1993 to
1995, he worked as Post-Doctoral Researcher with the VLSI
Design Laboratory at the University of Patras. From 1996 to
2000, he was an Adjunct Lecturer with the Department of
Computer Engineering and
Informatics at the University of
Patras. From 2000 to 2004 he
was an Assistant Professor with the Electronics Laboratory, Department of Physics, Aristotle University of Thessaloniki, Greece. From
2004 to 2009 he was an Assistant Professor and currently he is an
Associate Professor with the Electronics Laboratory, Department of
Physics, University of Patras, Greece. His research area is in the
continuous and discrete-time analog filtering, including companding
filters, current amplifier filters, CCII and CFOA filters, and sampleddata filters, and in the development of ultra-low voltage building
blocks for biomedical applications. He also serves as a member of the
Editorial Board of the Analog Integrated Circuits and Signal Processing Journal and Associate Editor of the Circuits Systems and
Signal Processing Journal.

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