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HighLevelSynthesisUsers:ProductivityGainsBeckon,But
LearningCurveComesFirst
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SystemCbasedhighlevelsynthesis(HLS)toolshavegreatly
improvedinrecentyearsandareundergoingadoptionbymany
largesemiconductorcompanies.Buttogethighproductivityout
ofHLS,currentRTLdesignerswillfirstfacealearningcurve,
accordingtopanelistsattherecentDesignAutomation
Conference(DAC2012).
Thepanelwastitled,"HighLevelSynthesisProductionDeploymentAreWeReady?"ItwasmoderatedbyClem
MeasofquickStartConsulting.Panelistswereasfollows,inorderofpresentations:
MarkJohnstone,principalEDAtechnologist,Freescale
EliSingerman,principalengineer,IntelDesignTechnologyandSolutionsdivision
BenjaminSchafer,assistantmanageratR&DCentralLaboratories,NECCorp.
VinodKathail,distinguishedengineer,Xilinx
MarkWarren,engineeringgroupdirector,Cadence
AndresTakach,seniorarchitect,CalyptoDesignSystems(andchairofAccelleraSystemCSynthesis
WorkingGroup)
Measbeganthediscussionbynotingthat"fourofthesesixpanelistsresideinsemiconductorcompaniesand
haveresponsibilityforimplementinghighlevelsynthesisflows.Thepurposeofthepanelistomakesurewe
haveagoodunderstandingofwhereweareinthatprocess."Henotedthatittakes10yearsfortheindustryto
movetoanewlevelofabstraction,andsaidthatwithHLS"we're8yearsintoa10yearperiod."
MarkJohnstoneTheViewfromFreescale
JohnstonenotedthatFreescalemanagementhasdecidedthatit'stimetomoveaboveRTL.Why?Complexity!
"Todaywe'reseeing1.3billiontransistorsperdesign,"hesaid."In2020,attheprojectedendofMoore'sLaw,it
willbe21billiontransistors.ClearlythisisnotsustainablewithRTL."
ButHLSposessomechallenges."Ournumberoneproblemisthelearningcurve,"Johnstonesaid."RTL
engineersmayhavetakenoneCclassincollege25yearsago,andthat'stheextentoftheirexperience."Without
training,they'renotgoingtowritegoodCcodeorgetgoodhardwareoutofit.Healsonotedthat"weseealotof
CcodethattriestogetdowntotheVerilogRTLlevel."
Johnstonealsosaidthatsometoolshave"notwelldocumented"restrictionsoncodethetoolcanaccept,that
morelibrarycodeisneeded,andthatECOflowsneedtoimprove.Buthethinkstheseissuescanbesolved.To
demonstratetheimportanceofHLS,JohnstoneshowedsomeRTLcode,askedtheaudiencewhatitdoes,and
thenshowedhowHLSabstractsoutwhattheprogrammeristryingtosay."Andthatiswhythere'shigher
productivity,andwhyit'sawinningstrategy,"hesaid.
EliSingermanTheViewfromIntel
So,asthepaneltitleasks,isHLSreadyforproductiondeployment?"Theshortanswerisno,"Singermansaid,
"butIthinkwecangetthereandwewanttogetthere."HecitedIntel'sbeliefthatabstractionisthemostimportant
waytotacklecomplexity,andobservedthat"weareataninflectionpointwherethetraditionalRTL
designflowissimplynotgoodenoughforthelevelofcomplexityweneed."

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2015.3.6.

HighLevelSynthesisUsers:ProductivityGainsBeckon,ButLearningCurveComesFirstIndustryInsightsCadenceBlogsCadenceCommunity

IntelistakingactivestepstorealizethevisionofHLS,Singermansaid,andisrunninganumberofexperiments
withHLSdesignflows.Whilethecompanyis"encouragedbytheresultswesaw,"thereisasteeplearningcurve
forRTLdesignerswhomustsuddenlyunderstandmoreaboutsoftwaredevelopment,henoted.Healsosaid
thatcurrenttoolsandmethodologiesdon'tfullysupportverificationattheSystemClevel,andhecalleduponEDA
companiesto"startvalidatingSystemCmodelslikewe'vebeendoingforthepast20yearsinRTL."
SingermanalsonotedthechallengeofintegratingblocksdesignedwithHLSwithpreexistingRTLblocks.
"Integrationissuescanveryeasilyoffsetanybenefitwegetfromthisnewdesignparadigm,"hesaid."Ifwegeta
twomonthsavings,andittakesusfourmonthstointegrategeneratedRTLwiththerestofthesystem,welose
twomonths."
BenjaminSchaferTheViewfromNEC
HLSisnotnewtoNEC.ShafernotedthatthecompanydevelopeditsownHLStoolinthe1980sandhaditsfirst
HLStapeoutin1993.Evenso,mostdesignsareacombinationofHLSblocksandlegacyRTLIP,whichmustall
beverifiedtogether.
ShaferobservedthatHLSgivesrisetosomechallengingquestions,suchas:
WhatshouldbeimplementedinCandwhatshouldbeimplementedinRTL?
Howdoyouverifythesystem?(AtRTLyoulosetheadvantagesofHLS)
Howdoyoudealwithinterfacesandbusses?
Howisthecompanyorganized?ArethereseparateCandRTLdesignteams?
HowdoyouachievegoodQoR(qualityofresults)?
What'sthelearningcurve?
Whatarethecostsofswitchingtools?
Healsonotedthatvirtualplatformsarebecomingessential,buttheydon'tworkwithHLS."Canwemake[virtual
platform]SystemCTLMmodelssynthesizable?It'sabiggapinthedesignflow,"hesaid.
VinodKathailTheViewfromXilinx
HLSisimportantforFPGAsfortworeasons,Kathailsaid.Oneisthatit'sverytimeconsumingtodesignamulti
milliongateFPGA.AnotheristhatsoftwareprogrammerswanttouseFPGAfabricstoacceleratecertaintasks.
ThisisparticularlytruefortheXilinxZynqplatform,whichcombinesaprocessorwithanFPGAfabric.
XilinxrecentlyannouncedanHLScapabilitywithitsVivadotoolset.Kathailcitedanexampledesignthattook12
weekstohandcodeinVHDL,versusoneweekforVivadoHLS.QoRiscomparabletowithin1015%ofhand
codeddesigns,hesaid.Further,HLSallowsdesignspaceexploration.ButheacknowledgedthatHLSrequires
differentskillsets.
MarkWarrenWhatCadenceCustomersareSaying
WarrenofferedsomeobservationsbasedonexperiencescustomersarehavingwiththeCadenceCtoSilicon
Compiler.OneimportantpointisthatHLSrequiresfarfewerlinesofcodethanRTLsynthesistodescribe
functionality,makingitunnecessarytocommittoamicroarchitecture.This,inturn,makesitpossibletoexplorea
numberofdifferentmicroarchitecturesandevaluatearea,timing,andlatencytradeoffs.Anotherbigwinisthe
fasterfunctionalverificationavailablewithSystemC.Becausefewerlinesofcodearerequired,simulationis
fasteranddebuggingismoreefficient.
"Butit'snotallrosy,"Warrensaid."Theoverwhelmingfeedbackfromthispanelisthatthereisalearningcurve,
thereisanewskillsetthat'srequired."ItmaytakeseveralmonthsforanRTLdesignertolearnC++fromscratch,
althoughonceheorshelearnsC++,learningSystemCshouldonlytakeafewdays,hesaid."Wereallyneeda
lotmoredesignerswhoarecomfortableinC++.WeneedtopushbacktotheuniversitiestobringC++back."
Becauseoftheneedfornewskillsets,mostcompaniesdon'tgetfullproductivitybenefitsthefirsttimetheyuse
HLS."Butthesecond,thirdorfourthtimesthat'swhenyoureallystarttoseetheproductivitybenefits,"Warren
said.
AndresTakachCalyptoSurveysUserWants
TakachnotedthatanumberofproductiondesignshavealreadygonethroughHLS."Typicallyproductivitygains
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are4Xto20X,"hesaid."Inthefirstdesignit'sless,butasyoumoveupinexperienceyougetfurtherandfurther
improvement."Headdedthat"certainlypeopleneedtounderstandthelanguageandbecomfortablewithit."
TakachcitedacustomersurveythataskedaboutthethreemostimportanttechnologiestointegratewithHLS.
Theanswers:Formalverification,RTLsynthesis,andpoweranalysisandoptimization.Thesurveyalsoasked
aboutcriteriausedtoselectHLStools.Thenumberoneitemwas"reducedverificationtimeandeffort."
DoesSystemDesignRequireaNewClassofEngineer?
That'sthequestionIraisedinablogpostoverayearago,andthequestionisstillvalidtoday.TheidealHLSuser
isanengineerwithbothhardwareandsoftwareskills.HeorsheneedstobeabletowriteanefficientSystemC
(C++)modelthatexpressesdesiredsystemfunctionality,butremainsfarabovetheregistertransferlevelin
abstraction.This"hardwaresavvy"synthesizablemodelmustachieveQoRcomparabletohandwrittenRTLina
fractionofthetimethathandcodingwouldtake.
Hereinliesachallengeandanopportunityforthoseseekinganeworbettercareer.
RichardGoering

HighLevelSynthesis
TLM

DACpanel

ClemMeas
SystemC
C++

ECO

SoC

Intel

cadence

Vivado

SystemLevelDesign

CtoSiliconCompiler
ESL

DAC

QoR

xilinx

IndustryInsights
RTL

NEC
DAC2012

Freescale

zynq
Calypto

learningcurve
Synthesis

HLS

FPGA

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