Rev Date

Rev.

2005-06-16

Document ID

15205-891586

Prepared by

Approved by

BGA

OS

Common Tests for Plug In Units for IFU

Next Generation
Table of Contents

CONFIDENTIAL

1.
1.1
1.2
1.3
1.4

INTRODUCTION.............................................................................................................. 2
Purpose and scope........................................................................................................... 2
References....................................................................................................................... 2
Terminology and abbreviations.........................................................................................2
Open issues...................................................................................................................... 3

2.

UNIT DESCRIPTION........................................................................................................4

3.
3.1
3.2
3.2.1
3.2.2
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.4
3.4.1

TEST STATION DESCRIPTION.......................................................................................4

Test Station overview........................................................................................................4
Test Jig............................................................................................................................. 5
Test Board, PIUT.............................................................................................................. 5
Mechanical enclosure for PIUT.........................................................................................5
Test Station Equipment.....................................................................................................5
Nera Equipment................................................................................................................ 5
Instruments....................................................................................................................... 5
JTAG Equipment............................................................................................................... 6
General Equipment........................................................................................................... 6
Cables.............................................................................................................................. 6
Test Station Software........................................................................................................6
First time Set-up of Test Station........................................................................................6

4.
4.1
4.2
4.2.1
4.2.2
4.3
4.3.1
4.4
4.4.1
4.4.2
4.4.3
4.5
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
4.5.6
4.5.7
4.5.8

OPERATIONAL TESTS....................................................................................................7
Test overview.................................................................................................................... 7
Initial Process Tests.......................................................................................................... 8
Automatic Optical Inspection (AOI)...................................................................................8
In-Circuit Testing (ICT) (Flying Probe Test (FPT) / Bed of Nails).......................................8
Power-On Tests................................................................................................................ 8
Current Limit Test.............................................................................................................. 8
Boundary Scan Test.......................................................................................................... 9
Infrastructure Test............................................................................................................. 9
Interconnect Test.............................................................................................................. 9
Adapter Test...................................................................................................................... 9
Functional Tests.............................................................................................................. 10
Current Consumption......................................................................................................10
SBC Software download.................................................................................................10
SBC Address Detection..................................................................................................10
Front LED Test................................................................................................................ 11
Hot Swap Test (3.3v).......................................................................................................11
FPGA Software download...............................................................................................11
Inventory......................................................................................................................... 12
Secondary Voltages........................................................................................................12

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Next Generation

Confidential

Change Record
Rev

Date

A
B

2005-03-09
2005-06-16

Pages
affected
All
1,7,12
12
3

1.

INTRODUCTION

1.1

Purpose and scope

Changes
Initial issue
Confidential stamp added in header and footer.
25MHz detection test removed.
Altered revision format and serial no format in table 4-2.
Reduced no. of open issues

This Unit Test Requirement for Manufacturing describes the common tests for all the Plug-In Units (PIU) to
the IFU.
The purpose of this document is to:
Define test requirements for the PIU.
Describe (in some detail) how the tests shall be performed.
Describe necessary equipment, instruments and software to perform the tests.
Be a reference and input for test development and documentation (Test Instructions/-Results, etc.).

1.2

References

Nera specifications
Ref. No. / Document code
[1] NGP\00106
[2] In e-Matrix, various objects
[3] Test Board (PIUT) schematics and drawings
[4] NG-IFU\BASIC\00053
[5] NG-IFU\BASIC\00060
[6] NG-IFU\BASIC\00061

Title / description
IFU-System Design Specification
Board schematics and drawings
\\Nera64\Next_Generation_Prod\Detail Design
Phase\IFU\PIUT-PlugInUnitTest
IFU Software Download
Functional Test Station Description PIU
PIUT Board and FPGA Design Specification

Table 1-1: References

1.3

Terminology and abbreviations

Abbreviations
ADC
AOI
BGA
BIST
CMI
CMOS

Descriptions
Analogue to Digital Converter
Automatic Optical Inspection
Ball Grid Array
Built-in Self Test (Test performed without instruments)
Codec Mark Invertion
Complementary Metal Oxide Semiconductor

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Next Generation

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DAC
DXC
EMC
FET
FP
FPGA
ICT
IEEE
IF
IFU
I/O
JTAG
LIU
MDS
MODEM
MSOH
NROP
OHC Bus
PCB
PIU
PIUT
POD
PSU
QAM
RCVR
RIU
RPS
RSOH
SBC
SDH
SOH
SU
TCK
TDI
TDO
TMS
TRST
UBN
UUT
XCVR
XPIC

Digital to Analogue Converter

Digital Cross Connect
Electro Magnetic Compatibility
Field Effect Transistor
Frame Pulse
Field Programming Gate Array
In-Circuit Testing
Institute of Electrical and Electronics Engineers
Intermediate Frequency
InterFace Unit
Input/Output
Joint Test Action Group
Line Interface Unit
Main Data Switch
MOdulatorDEModulator
Multiplex Section OverHead
Nera Radio Overhead Processor
OverHead Connection Bus
Printed Circuit Board
Plug In Unit
Plug In Unit Test (Test Board for Supervisory Unit)
Connection Box used with JTAG Boundary Scan controller
Power Supply
Quadrature Amplitude Modulation
ReCeiVeR
Radio Interface Unit
Radio Protection Switching
Regenerator Section OverHead
Su Bus Controller
Synchronous Digital Hierarchy
Section OverHead
Supervisory Unit
Test Clock
Test Data In
Test Data Out
Test Mode Select
Test Reset
Nera Networks PCB
Unit Under Test
Transceiver
Cross Polar Interference Canceller

Table 1-2: Terminology and abbreviations

1.4

Open issues

Consider using fan for test of some PIU.

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2.

Rev Date

UNIT DESCRIPTION

The PIU interfaces the motherboard with user interface or radio equipment.

3.

TEST STATION DESCRIPTION

3.1

Test Station overview

Figure 3 -1: Test Station overview shows a general setup of a test-jig for a Plug-In Unit. The various units
might have minor changes to this setup. The boundary scan part of the test might be performed on a separate
test station. In such a station, the Ethernet and RS232 communication is not needed.

+ 3.3V (4)

P4
2-Pin D-Sub
48V Connector

48V Valid

48V Power Supply

Controllable
Agilent E3645A

-48V

IFU address (3)

GPIB

SLOT address (4)

Ref_CLK

P2
3M
20-Pin
3M
20-Pin
P8

SYNC(3)
PIU

OHC bus (4)

Main Data Bus#1 (10)
Serial Diag. (2)
RESET#

P5B

Ethernet
PIU (UUT)

P5A

Ethernet
PIUT

JTAG (6)
SU Bus
10/100 Ethernet A (4)
SU Bus
1G Ethernet (4) NC

P6

9-Pin D-Sub
DIAG-RS232PIU (UUT)

P11

9-Pin D-Sub
DIAG-RS232PIUT

P9

3M
20-Pin
Debug PIUT

P3

3M
20-Pin
Debug UUT

P10

USB-PIU
Type B

P12

USB-PIU
Type A

PIUT
ET5157A

SU Bus
10/100 Ethernet B (4) NC
HSWAP
J1
95-Pin

GND (22)

J1
95-Pin

UUT

P1
3M
10-Pin
3M
10-Pin
P7

TAP1 (UUT)

JTAG POD
JT2137/12

TAP2 (PIUT)

Ethernet 1
Ethernet 2

JTAG Cable

RS232

Switch
Boundary Scan
Controller
JT3727/PCI
JT3710/USB
JT3727/USB

Office
LAN

J2
55-Pin

Test Jig

ET5157A

Windows XP/2000 PC
Two LAN + GPIB
Barcode reader

Figure 3-1: Test Station overview

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3.2

Test Jig

The UUT will be placed in a Test Jig (Fixture) for the tests. The Test Jig will consist of a dedicated Test
Board named Plug-In-Unit-Test (PIUT) and a mechanical enclosure.

3.2.1 Test Board, PIUT

The Test Board (ET5157A) is normally referred to as the PIUT. The UUT connects to the PIUT via a 95-pin
and in some cases an additional 55-pin connector. The PIUT has an FPGA that needs to be programmed if
the units power has been off. The PIUT has several connectors for various test equipment; such as boundary
scan and software download. See Figure 3 -1. See also document [6] for details.
The main connectors are:
-48DC In
D-Sub connector
TAP1 (10-pin)
3M 10-Pin connector for accessing JTAG chain on UUT (PM3705 controller)
TAP1 (20-pin)
3M 20-Pin connector for accessing JTAG chain on UUT (JT 3710/37x7 controller)
TAP2 (10-pin)
3M 10-Pin connector for accessing JTAG chain on PIUT (PM3705 controller)
TAP2 (20-pin)
3M 20-Pin connector for accessing JTAG chain on PIUT (JT 3710/37x7 controller)
Ethernet1
LAN Connector for communicating with UUT
Ethernet2
LAN Connector for communicating with PIUT
RS-232
For serial communication with UUT.
RS-232
For serial communication with PIUT

3.2.2 Mechanical enclosure for PIUT

It is intended to use a similar enclosure on the PIUT as for the IFU. The PIUT is designed with similar
dimensions as the IFU Motherboard. UUT will be inserted into PIUT slot No. 3. Slot No. 1, 2, 4, and 5 will
be closed by blind panels. The mechanical enclosure will have an open top for easy access to test connectors
on the PIUT board.

3.3

Test Station Equipment

The following equipment is needed to do the common test for a PIU.

3.3.1 Nera Equipment

PIUT, ET5157A
PIUT frame including a vertical board

3.3.2 Instruments
48V Power Supply, GPIB Controllable.
GPIB Interface for PC

Ex. Agilent E3645A

Ex. Agilent 82357A/USB

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3.3.3

JTAG Equipment

Boundary Scan Controller.

Boundary Scan POD.

Ex. JT3727 (/ PCI or TSI) or JT3710 (/ PCI or USB)

Ex. JT2137/12 or JT2147

3.3.4 General Equipment

Test PC with Windows 2000 or newer and 2 LAN connections.
Ethernet Switch
Barcode reader

3.3.5 Cables

TP Cables (LAN cables)

GPIB Cable
RS-232 Cable
48V Cable
TAP Cables

3.4

Test Station Software

The following programs are needed to test and program the IFU PIU.
Test Type
Boundary scan
Functional test

Program type
JTAG test SW from JTAG
Technologies BV
Ethernet Server
TCL platform
TFTP server
TCL script

Name
PCA2176
PM3790
Bootp Server
ActiveTCL
(wish84.exe)
TFTPD32
xxx.tcl

TclDriver

UdpTclDriver.dll

LPC Code
FPGA code

sbcFlash.hex
fpga<xxx>.nff

Used for
Production package
Boundary Scan Diagnostics
Sets up the TCP/IP connection
Sending configuration
commands to UUT.
Server for software download
Various TCL script made
specifically for the tests.
TCL driver with basic TCL
commands.
Programming the LPC.
Programming the FPGA.

Table 3-3: Programs needed during testing

3.4.1 First time Set-up of Test Station

Check document [5] for details on first time station setup.

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4.

OPERATIONAL TESTS

This chapter shall define the performance parameters which are required to be tested in the manufacturing
test, and specify parameter values with sufficient margins to guaranteed values.
The test software used for the operational tests should record test results with at least article code, serial
number, test date, test point, and test results.
Boundary scan tests should work on the UUT regardless if the software is downloaded or not.
The UUT should be visually inspected before the tests are performed to eliminate obvious faults such as heat
sink not mounted correctly.

4.1

Test overview

Table 4 -4 below shows an overview of the tests to be done. Further description of the tests is given in the
chapters to follow.

Test
no.

Tests / operations

Initial Process Tests

1 Automatic Optical Inspection
(AOI)
2 In-Circuit Testing (ICT)
Power-On-Test
3 Current Limit Test
Boundary Scan Tests
4 Infrastructure Test
5 Interconnect Test
6 Adapter Test
Functional Tests
7 Current Consumption
8 SBC Software download
9 SBC Address Detection
10 Front LED Test
11 Hot Swap Test (3.3v)
12 FPGA Software download
13 Inventory
14 Secondary Voltages

Purpose / Comments

Automatic Optical Inspection

In Circuit Test
Ensure there are no short circuits
To verify the JTAG chain is operational
To verify all nets between Boundary Scan Circuits
To verify the J1 connection to the PIUT board
Check that the current consumption is within requirements.
Download SBC software to the UUT.
Check the SBC and address bus connectors.
Verify that front LED is working
Verify hot swap functionality
Download FPGA software to the UUT.
Set inventory data.
Checks the secondary voltages.
Table 4-4: Test Overview

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Initial Process Tests

These tests are performed before the UUT is inserted in the Test Station.

4.2.1 Automatic Optical Inspection (AOI)

Tests that correct components are mounted and that they have correct orientation.

4.2.2 In-Circuit Testing (ICT) (Flying Probe Test (FPT) / Bed of Nails)
Perform an ICT to at least test components not covered by boundary scan or functional tests.
The power circuits should be included in the test.

4.3

Power-On Tests

4.3.1 Current Limit Test

The purpose of this test is to verify that there are no major shot circuits either in the -48V supply or
secondary voltages. This should be checked before doing any boundary scan or functional tests.
Set the current limit to X mA on the power supply, where X depends on the PIU.
Check current consumption does not exceed 90% of the current limit.
If excessive current consumption:
Turn off power immediately.
Measure the resistance between GND and power circuits using a multimeter
Inspect board carefully for short circuits and components mounted incorrectly.
If this test is performed using a GPIB controlled power supply, test no 4.5.1 (Current Consumption) can be
done at this point in stead of later.

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4.4

Boundary Scan Test

1. Perform infrastructure test to verify the JTAG chain is operational.

2. Perform interconnect test to verify all nets between Boundary Scan Circuits.
3. Perform adapter test to verify the J1 connection to the PIUT board.
At the moment the SBC is not a Boundary Scan circuit even though its in the TDI-TDO chain.
The IC is therefore bypassed with a special BSDL-file.

4.4.1 Infrastructure Test

Test the JTAG chain, TDI-TDO. This verifies that the JTAG chain is operational.
The netlist is found in eMatrix.

4.4.2 Interconnect Test

Test signals between Boundary Scan circuits and input/output signals.
Test Pull-up and Pull-down nets.
This requires that PWR and GND nets must be defined in the .NIF file
(The main purpose of the .NIF file is to disable drivers which otherwise can cause bus conflicts.)
Handle all attentions in the .ECN-file.

4.4.3 Adapter Test

Test signals between Boundary Scan circuits on the UUT and Boundary Scan circuits on the Test Jig.
Define an adapter file (.ADP-file).

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Common Tests for Plug In Units for IFU
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Functional Tests

The following describes functional tests to be performed on each produced UUT. Some of the tests can be
performed in any order, but we suggest using the same order as the chapters in this document. To minimize
the test time, simultaneous testing of several test points should be used if possible.
Set up the test station as shown in Figure 3 -1.

4.5.1 Current Consumption

The purpose of this test is to check that the current consumption is within the requirements.
Set the current limit to Y mA on the power supply, where Y depends on the PIU.
Requirements: X mA where X depends on the PIU.
If excessive current consumption:
Turn off power immediately.
Measure the resistance between GND and power circuits using a multimeter.
Inspect board carefully for short circuits and components mounted incorrectly.

4.5.2 SBC Software download

The SBC controls, among others, the FTP communication and needs software before any other test can be
performed.
Procedure:
1. Download software to the SBC. See download document [4] for details.
2. Set slot address and unit address
3. Reset the UUT
4. Verify that the UUT has SBC downloaded

4.5.3 SBC Address Detection

The purpose of this test is to check that the SBC and connections are correct. This is verified by checking
that the SBC detects the correct addresses. This test assumes that the SBC software and FPGA code are
already downloaded to the PIUT and SBC software is downloaded to the UUT.
The test can be performed automatically by running a TCL script.
The script should do the following:
1.
2.
3.
4.

Verify that the UUT reads the address sat in the PIUT.
Alter the slot address in PIUT to 110.1110 (6.14) and verify that the address is detected in the UUT.
Alter the slot address in PIUT to 001.0001 (1.1) and verify that the address is detected in the UUT.
Return 0 if the test succeeds, and an error code if the test fails.

Check the return value from the TCL script to determine pass/fail status of the test.

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4.5.4 Front LED Test
The purpose of this test is to verify that the front LED is working. The LED is controlled from the SBC.
The LED can be set in different modes:
Green LED ON indicates no alarms on unit.
Red LED ON indicates critical alarms on unit.
Set the green LED to ON and verify by visual inspection that the green LED is green.
Set the red LED on and verify by visual inspection that the red LED is red.
Since this test requires interaction with the test engineer, the test should be put towards the beginning (after
SBC download) or end of the test sequence for the UUT.

4.5.5 Hot Swap Test (3.3v)

This test is used for verifying that the Hot Swap controller is working and the connection between PIUT and
UUT.
The Hot swap signal (HSWAP) is controlled from the PIUTs FPGA1 (IC300, pin 99) and can be strapped
with a jumper (P306) to 3.3 volt to set the signal high. (This strap is used in boundary scan test.) The signal
goes trough PIUTs connector J1 on pin no. 10C to the UUT. On the UUT the signal goes to the Hot Swap
controller to enable/disable the 3.3 volt to pass trough.
This test assumes that the SBC software and FPGA code are already downloaded to the PIUT and SBC
software is downloaded to the UUT.
This test can be done automatically by running a TCL script 1. The scrip should do the following:
1. Set the Hot Swap signal low from the PIUT and verify that UUT powers down.
2. Set the Hot Swap signal high from the PIUT and verify that UUT powers up.
3. Return 0 if the test succeeds, and an error code if the test fails.
The script should read the SBC software version to check if the UUT is running.

4.5.6 FPGA Software download

The FPGA needs to be downloaded every time you cold-boot the UUT.
1. Download the configuration file to the FPGA as described in [4].
2. Verify that the FPGA code is downloaded by writing and reading to the FPGA register.
If the download is OK, the test-LED should be blinking aprox. 1-2 Hz
If the download fails, the LEDs will not blink. In that case check that the 25MHz and 10MHz oscillator from
PIUT is correct.

On PIUT releases until M1A you have to remove the jumper from P306 (or set the jumper to 2-4) before running the

script.
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4.5.7 Inventory
Set the inventory data according to Table 4 -5. Check that the inventory is stored correctly.
Data to be set
Product code
Revision
Serial number
Manufacturing date

Value
[Product code]
[Current revision]
[Current serial number]
[Current date in format yyyy-mm-dd]

Example
FDM5559A
R1A
80130015
2005-05-25

Table 4-5: Inventory

4.5.8 Secondary Voltages

The SBC contains an A/D converter for measuring analogue values. This is used to verify key voltages on
the UUT. The secondary voltages might be measuring different voltages depending on the UUT.
Requirements for each unit is stated in their respectively UTRM document.
Check that the secondary voltages are within spec according to UUT specific UTRM document.

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