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The line/trunk group (LTG) is a hardware device that provides basic connectivity to other
network nodes. The functionality of the LTG can be split into two basic parts:
The LTG performs call processing functions.
The LTG additionally executes traffic switching and the insertion of tones and
All LTGs have a uniform basic structure and the same principles of operation. They
merely differ from each other as far as a few hardware units and the application
programs in the LTG type specific group processor are concerned. A difference is made
between the BSSAP/RANAP load type for connections to the mobile side and the trunk
load type for connections to the PSTN/ISDN.
Call processing
The line/trunk groups control and supervise incoming and outgoing calls with SS7 signaling
to and from:
The radio access network (RAN)
Other circuit-switched public networks (e.g., PSTN/ISDN or another PLMN)
Other core network nodes
Voice mail system centers (VMSC) or other CN centers/components based on
OEMs (e.g., SMS-IWMSC)
The LTGs also supports connections to fixed networks (PSTN/ISDN) with MFC signaling
by code receivers (CR) for multifrequency signaling.
The LTGs also control special call functions:
Interworking function (IWF) in the DSU
Loop functions (for example, loops for mobile-to-mobile calls)
Conferencing (in relation to the multiparty supplementary services)
User interaction (UI) function (for the IN/CAMEL implementation of a specialized
resource function (SRF) or standard announcements)
The LTGs support all the conventional signaling systems (e.g., SS7, MFC:R2) for calls
to fixed networks. The LTG contains the SS7 user software of different types depending
on the signaling used. Because the signaling methods used on various interfaces can
differ, the LTG has an internal signaling-independent interface to the switching network
and a common software system in the CP113 for all applications.
Bearer switching
The LTGs have incoming/outgoing digital PCM30 highways, which are called primary
digital carriers (PDCs) and which have 32 channels of 64 kbit/s each. The LTG is connected
to both planes of a duplicated switching network by means of a secondary digital
carrier (SDC), which has 128 channels of 64 kbit/s. The channels 0 and 1 are reserved
for communication with the CP. In the channels 2.....127, both SDCs transport the same
information for redundancy reasons.
Besides the mobile traffic interfaces, the LTG can control the following special connection
Connections to the node-internal hardware subsystem TRAU server card (TSC) of
the MP platform (for TDM to/from ATM conversion)
Connections to wired ISDN/analog subscribers served at the CSC within the 2GMSC/
VLR part
Connections to the remote access server (RAS) for the Mobile Internet Access
(MIA)/wireless application protocol (WAP)
For certain functions, the LTG is extended by supplementary hardware units:
For connections to the PSTN/ISDN, a digital echo compensator (DEC) can be
inserted to protect the mobile subscriber from electrical echoes when necessary.
To support speech conferences, the automatic test and conference unit (ATCO)
is added to the LTG equipment.
LTG hardware components
Depending on its functionality in the MSC, the LTG comprises the following hardware

parts (see Figure 8):

The group processor for LTG (GPP/GPN depending on the LTG variant) to integrate
the following functional parts:
An independent control unit for switching the received information to another
time slot and highway. This part matches the incoming information from other
network node areas to the internal message format of the system and controls
all other functional parts within the GP.
Units to match the connected lines to the LTG internal interfaces enabling to
connect PCM30 spans via a PDC. However, they also enable a digital interface
to be connected to the local DLU. The following signaling systems will then be
possible: analog E&M signaling or digital R1 and R2 line signals for basic
channel associated signaling (CAS).
A code receiver to receive and detect multifrequency signals such as DTMF,
A tone generator with programmed tones to be used as audible tones and
signals for call processing and safeguarding, control signals for the GP software
to control tone through connection, dial pulses.
A clock generator provides the clocks for the speech data and for the signaling;
their control is frame synchronized.
A link interface to both switching network planes SN enabling information to be
exchanged via the active plane.
A digital interface unit for the local DSU/DLU interface.
The LTG can be equipped with an optical interface (SNOPT).
The LTG can be equipped with an additional line trunk unit (LTU:S) with a digital
echo compensator (DEC), which can serve several PCM30 spans and is required to
protect the mobile subscriber from speech echo that is produced on the 2/4 wire connection
at the PSTN station.
The LTG can also be equipped with an additional line trunk unit (LTU:S), an automatic
test and conference unit (ATCO), allowing to build up speech conferences.
For normal and user interaction announcements, the LTG is equipped with an additional
line trunk unit (LTU:S) with operationally controlled equipment for announcement
(OCANEQ) with optional voice processing units (VPUs).

STM-1 Interface Integrated

The STM-1 interface integrated (STMI) offers an integrated synchronous transport
module level 1 (STM-1) interface to SDH-based transmission networks for trunk applications.
The STMI is implemented based on equipment of the LTG (GPP and LTU:S),
which is supplemented with STM-1 interface modules (STM1I) that provide optical (1300
nm short haul) and electrical (coax) STM-1 interfaces. A 1:1 redundant configuration is
used, with one STM1I worker module and one STM1I protector module per STMI.
Each group processor for STMI (GPS) houses four GPP units and is connected to the
STM1I boards via 63 PCM30 links, providing a connectivity of 1890 channels per GPS.
Four GPS are provided per STMI, with one GPP of each GPS connected to an LTU:S.
The STMI is connected to the SN(D) via an optical (via SNOPT) or electrical interface.

Coordination Processor 113

The coordination processor (CP) handles all system-wide and coordination functions,
e.g., routing and zoning. It also deals with most of the call processing tasks, and with the
MSC/VLR administration and maintenance.
The central multi-processor CP113 interacts with:
the message buffer (MB) to coordinate the internal signaling message traffic
between the CP113, the SN, the LTGs and the SSNC.
the central clock generator (CCG) providing for the various clock signals (e.g.,
8192 kHz) for synchronization.
the external memory (EM) for the storage of non-resident programs/data, an image

of the resident programs/data (for recovery), and the call charge and traffic measurement
the craft terminal local (CTL) is used for APS installation, recovery and other
administration tasks. It can be connected via TCP/IP, X.25 or V.24 and enables the
administration of Q3 tasks and MML commands.
For inter-processor communication, connections are set up between the GP and the CP
via the SN. These connections are set up during the MSC/VLR installation and are maintained
during normal operation, and are therefore referred to as semipermanent connections.
The CP113 handles the common functions within the MSC/VLR, such as the coordination
of the distributed microprocessor controls and the data transfer between them.
The CP113 comprises the following processor modules (PEXE):
The base processor (BAP) handles all administration and maintenance tasks and
a portion of the call processing functions. For reasons of reliability, the BAP is made
redundant. There is the BAP master (BAP0) and the BAP slave (BAP1). However,
the BAP1 does not carry out any administration or maintenance tasks during normal
operation. It only performs call processing functions. Only when the BAP0 fails, the
BAP1 takes over all administration and maintenance tasks.
The call processor (CAP) only deals with call processing tasks. The supported
number of CAPs depends on the type of CP113 processor used. The currently used
version CP113 E supports up to 18 CAPs. All installed CAPs operate in loadsharing.
The input/output controller (IOC) is the interface between the CP113 and the
peripheral hardware. It receives and forwards information without any processing
function. For redundancy reasons, minimum two IOCs are installed (a pair:
IOC0/IOC1). However, to increase the I/O capacity, a second IOC pair can be
inserted (IOC2/IOC3)
The ATM bridge processor (AMP) is connected to the CMY. Pairs of AMPs are
operated in the CP in order to increase availability (see chapter 4.2.1).
The common memory (CMY) stores the MSC/VLR databases. For reasons of reliability,
the CMY is duplicated (CMY0 and CMY1). Both CMYs are active and store
identical information.
The bus to I/O controller (B:IOC) is the interface between the IOCs and the IOPs.
The B:IOC transports information at a 1 Mbyte/s rate.
The input/output processor (IOP) controls the data exchange with the peripheral
equipment, such as the external memory, message buffer, magnetic tape and disk
devices, the operation and maintenance terminal or a data communication network. Up
to 16 IOPs are linked to an IOC pair via the bus (B:IOC). Duplicated operating and data
communication devices (e.g., the message buffer) are always connected to two different
IOCs via two different IOPs.

4.1.5 Message Buffer D

The message buffer type D (MBD) enables direct communication between the SSNC
and LTG. The MBD interprets the target address of the signaling messages and directly
routes them to the target LTG, hereby reducing the message traffic in the CP113. And
in order to communicate with the LTGs, the MBD translates the asynchronous transfer
mode format into a synchronous format, and vice versa, that is, the MBD converts data
into ATM cells and transmits the cells on the internal protocol of the global ATM platform.

4.1.6 Central Clock Generator E

In order to switch and transmit digital information, it is essential for all equipment
involved in the process to operate synchronously, which means that every switch in a
digital network must be supplied with timing signals that are extremely reliable, accurate
and constant. The central clock generator E (CCGE) supplies the MSC/VLR with a
highly accurate, stable clock. In order to provide time synchronization, every second the
system updates itself with the signal from the Hopf GPS satellite controlled clock system
with an accuracy of +/- 1second.
The CCGE locks onto an external reference. The clock is available even if all reference
signals fail.

The CCGE supplies the following MSC/VLR subsystems directly:

coordination processor (CP)
signaling system network control (SSNC)
message buffer D (MBD)
The following subsystems are supplied via a clock provided by the message buffer D
(MBD), which is synchronized with the CCGE:
switching network (SN)
line/trunk groups (LTG)
The clock provided by the message buffer D (MBD) is also supplied to external users,
e.g., transport systems of the call processing (synchronous digital hierarchy (SDH)).

4.1.8 Digital Line Unit G

The digital line unit G (DLUG) connects wired ISDN subscribers and PABXs to the
combined switching center (CSC). The DLUG can be used locally within the MSC/VLR
or remotely in the vicinity of groups of subscribers. For reliability reasons, all DLUG units
are duplicated. Each DLUG is connected to up to four LTGs.
g The DLUG also supports ADSL and SDSL subscriber lines and analog subscriber
lines. As these are not supported by the CSC at the moment, they are not described
in this document.
The main components of the DLUG are:
Central functional units
The central functional units of the DLUG are duplicated and together form DLU sides
0 and 1. The central functional units are:
Control for DLUG (DLUC), which comprises the digital interface unit (DIU)/local
DLUG interface (LDI) functions, the group clock generator (GCG) function, and
the external alarm set (ALEX) function.
Bus distributor module (BDG), which forms the link between the subscriber line
modules (SLM) and the central functional unit DLUC on one DLU side.
Bus systems (voice bus and data bus, CD bus), which support the communication
between the central functional units and the peripheral functional units.
The central functional units of the DLUG are failure units. If a fault occurs in a central
functional unit on one DLUG side, call processing is still able to continue via the
other DLUG side (load restriction).
Peripheral functional units
The peripheral functional units comprise the subscriber line module, digital (SLMD)
modules, which control the execution of functions inside the DLUG and perform
safeguarding tasks.
Functional units for remote operation

4.1.9 Data Service Unit

An interworking function (IWF) is implemented to support teleservices and bearer
services in the PLMN core network (CN). This function provides both transparent and
non-transparent network support control functions to handle both unrestricted digital
connections and connections based on modem transmission to the PSTN/ISDN. The
IWF ensures compatible connections between the two users of the basic services.
The IWF is implemented in the MSC/VLR as both hardware function and software function:
The hardware function is realized in interworking equipment (IWE) modules integrated
in the data service unit (DSU) as shown in Figure 14. The DSU supports connection
to the line/trunk group (LTG) by means of digital links. Such a link is made
up of 30 x 64 Kbit/s traffic channels from a PCM span (consists of 30 time slots for
data transfer). One IWE module uses two traffic channels.
The software function is called the IWF user part (IWUP) and is loaded into the group
processor of the LTG.

The structures of the DSU and the DLUG are similar. The DSU consists of central and
peripheral functional hardware units.
The central functional units consist of a duplicated DLUG (side 0/1); they act as failure
units sharing all tasks. If a fault occurs in one of the central units, call processing with
reduced traffic capacity will still be possible using the other DLUG side.
The peripheral functional units comprise interworking equipment (IWE) modules with
integrated on-board modem + DC/DC converters.
4096-kbit/s bus 0/1* (*parallel collision detection
Control bus 0/1

DLUG side

40 A50016-E1114-D2-2-7618
MSC/VLR Hardware
Both DLUSs and the IWE modules communicate via a redundant bus system originating
from the bus distributor in order to exchange information via:
a control bus: transmission of signaling data and commands/messages between the
DLUS and the IWE modules;
a PCM bus with 64 channels of 64 kbit/s: distribution of traffic data to and from the
IWE modules. There is a fixed assignment between the channels of the PCM bus
and those of the primary digital carrier (PDC) link to the LTG. The PCM bus also
supplies a system clock and a frame synchronization pulse to correctly time the
exchange of data.
The duplicated DLUS has two interfaces for the connection of two PDCs connecting the
DSUs to two different LTGs. The DLUS takes the control and OAM information arriving
from the LTG and passes it on. In the opposite direction, th
the information coming from
the DLUS is transmitted to the LTG
The DLUS provides the interface to the DSU PCM bus towards individual shelves by distributing
the digitized information received via this bus to the IWE modules.
The DLUS also controls the sequence of DSU-internal functions and either distributes
or concentrates the signaling between the IWE modules and the shelves.

4.2 Main Processor Platform Parts

4.2.1 Signaling System Network Control
Call processing requires continuous communication within the MSC/VLR, especially
between CP, LTG and SN. The signaling messages are structured into packets and
internally transmitted via the signaling channel (time slot 0) between the LTG and the
switching network. The signaling message exchange is based on signaling system
number 7 (SS7) protocols. The SSNC is an SS7 controller platform providing the
protocol functions of the MTP, the SCCP and the operation, maintenance and administration.
It is a future-proof system which also supports the connection of SS7 high-speed
signaling links (HSL).
The SSNC is a functional unit whose functions are spread over several hardware components
of which the main processor (MP) is the key unit. A scalable central MP
(MP:OAM) is responsible for the main control of the universal ATM platform. All processors

communicate via an ATM switching network using a common internal transport protocol.
For reasons of reliability, all hardware units in the SSNC are duplicated.
A maximum of 1500 signaling channels can be connected to the SSNC. Two types of
signaling links are used, one via LTG and one via LIC. In the first case, the channels
carry signaling data to and from the LTGs at a 1.5 or 2 Mbit/s rate (STM: synchronous
transfer mode), whereas, in the second case, the SSNC handles ATM (asynchronous
transfer mode) signaling links via several line interface cards (LICs), which may have
bandwidths of 2, 34 and 155 Mbit/s.
The message transfer is handled in the SSNC by the line interface card (LIC), the ATM
switching network (ASN) and the MP for signaling link termination (SLT). When the LTG
receives SS7 messages as an STM byte stream (Figure 15), it may transfer it via the
switching network (SN) to the peripheral units (LICs).
The SSNC includes the following main units:
The line interface card (LIC) packages the incoming bits contained in the time slot
belonging to a signaling channel into ATM cells. These cells are transported from
the LIC through the ASN to the relevant MP:SLT being responsible for the signaling
link. It converts message streams of the SS7 network from synchronous transfer
mode (STM) with 1.5 or 2 Mbit/s to internal ATM cell streams and vice versa.
The main processor for signaling link termination (MP:SLT) handles the procedures
for the reliable transfer of signaling messages over one signaling link. These
procedures are defined by MTP level 2 (data link layer). Moreover, the MP:SLT
ensures the transport of signaling messages from a specific origination point to the
associated destination point (network layer). These functions are handled by both
the MP:SLT and the MP:SM. The MP:SLT is responsible for message handling,
implying message routing to determine an outgoing signaling link for a message
signal unit. The MP:SLT also distinguishes the signaling messages received based
on their destinations: intended for either the own or a different network node. It also
identifies the user part to which the message is distributed.
The main processor for signaling management (MP:SM) is responsible for the
signaling network management, including the diversion of the signaling traffic in the
event of an error, activation/deactivation of link sets, and sending status information
regarding the signaling network and its own MTP.
The ATM bridge processor (AMP) is the interface between the ATM equipment
and the coordination processor (CP113). It converts the ATM data streams to the
CP communication mode. For functional purposes the AMP belongs to the SSNC,
even though it is located in the module frame of the CP.
The main processor for global title translation (MP:GTT) provides the functionality
for translating the address data contained in SS7 messages from users of the
signaling connection control part (SCCP). This allows SCCP users to use a centrally
administered address system that is independent of the MTP network.
The main processor for number portability (MP:NP) provides the functionality for
the feature number portability, which allows mobile subscribers to keep their
MSISDN when changing to another network provider.

4.2.2 ATM Switching Network

The ATM switching network 15 (ASN15) is a high-performance ATM switching network
with a maximum throughput of 15 Gbit/s. It is responsible for transporting ATM cells
between peripheral (access) units and for the internal communication with the control
subsystem. The ASN15 is housed in the frame (shelf) F:SXCE, which is combined with
the basic frame (shelf) F:SXCB (which houses the MP-SA for connections to Switch
Commander and/or MP-OAMD for connections to the accounting and billing center),
and the former extension frame (shelf) F:SCE
gives an overview of the hardware structure, which comprises the:
ATM switch and multiplexer (ASMX15),
ASN controller and clock generator (ACCG).
The central parts of the ASN15 (ASMX15, ACCG) are duplicated. The new Hard Metric
module connector uses three SE96/48 switching elements with special functions such

as split mode and doubling of output ports.

ATM switch and multiplexer
The module ATM switch and multiplexer (ASMX) comprises the following functional
The AMX part contains a 32/16 multiplexer in the upstream direction and a 16/32
demultiplexer in the downstream direction. Both are contained in only one ASIC
SE96/48 (split mode). The AMX part therefore covers the full functionality of the
module AMXE which is housed in shelf F:SCE. The ATM cells received from LICs
or MPUs at the peripheral Yb interfaces (data inputs) are multiplexed and routed to
a connector at the back plane of the shelf F:SXCE and via a MTX4 cable to the
ASN15 part. In the downstream direction, the ATM cells received at back plane connectors
from the ASN15 part via a MTX4 cable are routed to LICs/MPUs over the
SE96/48 and the back plane via Yb interfaces. To support point-to-multi-point connections,
a multicast RAM is integrated in the switching element. The peripheral Yb
ports of the ASMX15 for the pairs of LIC/MPU slots use the same routing addresses
as in the F:SCE (partly with an additional Yb port for the LIC slots).
The ASN15 part contains a 96/96 switch comprising two ASICs SE96/48. All 96 data
lines are connected to MTX4 cables over back plane connectors. To support pointto
multi-point connections, a multicast RAM is in the switching element.
ASN Controller and clock generator
The ASN Controller and clock generator (ACCG) monitors and controls the ASMX15. In
addition, it supports the clock pulse for the ASMX15 as well as for the peripheral units
LIC and MPU. The peripheral control platform (PCP) in the ACCG controls the configuration,
testing, OAM and communication with the MPU using the internal transport
protocol (ITP).

4.2.3 Main Processor

Depending on the software loaded, the main processor can be used for several applications:
The main processor for RANAP (MP:RANAP), also referred to as the main processor
for bearer control function (MP:BCF), manages bearer control for ATM connections.
The MP:RANAP/BCF interworks with the LTG:BSSAP/RANAP for
connections on the Iu interface, and the LTG:BICC.
The main processor for AAL2 control (MP:AAL2 ctrl) is used for transport signaling
from the AAL2 bearer control.
The main processor for OAM (MP:OAM) allows the MTP/SCCP/ATM/AAL2
master database to be administrated via the Q3 interface of the switch commander,
so it makes available the communication capability that is required for communication
between the MSC and the SC of the UMTS management system (UMS). That
also implies the handling of the appropriate measurements, monitoring and alarming,
database management system (DBMS) and maintenance. All SS7/IWU administration
functions run on the MP:OAM and affect the other MP platforms; so, no
administration is required on the other ATM HW components.
Optionally, IPsec can be used for the protection of the OAM interface to the SC.
IPsec traffic is terminated in the CISCO-based Ethernet VPN gateway PIX 515E (for
further details, see Technical Description CN GSM/UMTScs).
The main processor for accounting (MP:ACC) is used for charging data collection
by the general data collection (GDC) and charging gateway protocol (CGP).
The main processor for STATS (MP:STATS) collects the SSNC/IWU (MP system)
measurement data received from the providers, formats it and sends it at regular
intervals to the MP:OAM for writing it onto the local hard disk, from where the data
records are transferred to the relevant processing centers.
g The main processor for SM (MP:SM) and the main processor for SLT (MP:SLT),
already detailed in 4.2.1, are not listed here but are - of course - also concerned by
the following explanations.
As shown in Figure 17, each MP comprises two main processor units (MPUs). The two
main processor units operate microsynchronously, that is, each MPU processes the

same sequence of commands on the same clock cycle. To guarantee this, both MPUs
are initialized with identical states and all data is transmitted synchronously to the two
MPUs. The state of each MPU is checked at regular intervals. The result is transmitted
to the other MPU via the cross link (XLink) and compared with the test data generated
If a hardware fault occurs in one of the two MPUs leading to a loss of the microsynchronous
parallel operation, both of them perform routine tests. The MPU detecting that it is
faulty switches itself off. Once the faulty unit has been replaced, the new MPU must be
synchronized. Each MPU is responsible for detecting its own faults and reporting them
to the other MPU. This hardware self-fault detection function ensures that the faulty
MPU is taken out of operation. The two MPUs are connected to the ASN via the ATM
interface (ATM230) and receive ATM cells but only one of the two (the active MPU)
transmits ATM cells.
Main processor unit
The main processor unit (MPU) consists of the following major functional units located
on one hardware module:
central processing unit (CPU).
ATM interface chip (ATM230). The internal system communication and the loading
of the system software are performed via this chip.
cross link (XLink). This unit is a master/checker interface for communication and
synchronization of the two MPUs. In addition, the synchronization between ATM230
and processor activities is performed here along with checks on the clock generation.
boot flash EPROM (FEPROM). Each of the three FEPROMs has a capacity of 2
Mbytes. The FEPROMs contain the boot software and hardware test programs
needed for startup of the MPU. The FEPROMs are connected to the ATM230 bus.
small computer system interface (SCSI). Supports the connection of a magnetic disk
device (MDD) and magneto-optical disk device (MOD). The MOD is used to enable
the loading of software and configuration data into the MP:OAM.
Ethernet interface. This interface is used for connecting to a local area network
Alarm indication module
The variant is additionally equipped with an alarm indication module (ALI). Unlike the
MPU, the ALI is not duplicated. The ALI indicates the alarm status of the system. It is
connected to the two main processor units via two serial ports. Only the active MPU
controls the ALI.
The ALI has the following main interfaces:
16 inputs for external alarms
4 inputs for internal alarms, for example, to monitor the temperature
3 LEDs for critical (red), major (red) and minor (yellow) alarms
4 relays for critical, major, minor and PCM alarms
2 LEDs (red, green) for the status of the ALI (controlled by a watchdog and MPU)
combined V.24 external time of day and calendar date (ToD) interface
monitoring of total MPU failure

4.2.4 Line Interface Card

The line interface card (LIC) within the MP platform provides for connectivity of the
external line interfaces to the ATM switching network (AMX, ASN Core). It converts the
byte-oriented data stream on the external ATM/STM side to a packet-oriented data
stream on the internal ATM side, and vice versa. We can distinguish:
The LIC(TDM/ATM):E1 providing 8 lines with E1 standard interfaces. Each E1 line
is able to operate at 2.048 Mbit/s. It is used for SS7 signaling towards CN nodes.
The LIC(ATM):STM1 consists of two STM1 parts and provides multiport lines STM1 standard interfaces based on the SDH STM-1 (according to ITU-T). Each STM1
line (electrical or optical) is able to operate at 155 Mbit/s.
The LIC operates 1:1 redundantly, that is, both LICs receive ATM cells but only one LIC
sends these ATM cells to the ATM switching network (ASN). Each LIC has a common
and a specific hardware part. The common part (which is identical for all LICs) contains

the ATM part, the peripheral control platform (PCP) and clock distribution. Specific to the
LIC is the physical layer (PHY) for providing the physical interfaces.
Individual functions of the different hardware parts:
the ATM part implements the ATM layer functions. It is logically divided into an upstream
and a downstream part.
the peripheral control platform (PCP) is based on the INTEL 80386EX (PCP94) and
Elan SC520 (PCP2000) controllers, which are used for all LIC types and the ACCG.
The internal communication to the MPU is implemented with the help of the ATM
adaptation layer, type 5 (AAL5) and internal transport protocol (ITP).
the clock generator monitors one of the two ASN clock inputs from the ACCGs and
supplies the clock generators for the physical layer and ATM parts.
the physical layer contains the physical layer functions and also the ATM adaptation
layer no.1 (AAL1).