CHAPTER 7

FLIP-FLOPS
Objectives

Sequential circuits

SR, D and JK Flip-flops

Registers

Calculator

Flip-Flops
7.1

104

Sequential Circuit

Logic circuits are classified in two categories. The logic circuits considered
thus far have been combinational circuits, whose output is a function of only
the present input. The basic building block of combinational circuits is the
logic gate.
Input

Ouput

Combinational
Logic Gates

Most digital systems are made up of combinational circuits and memory

elements. This circuit is known as sequential logic circuits. The output of the
circuit depends not only on the present input but on previous inputs as well.
This history of a sequential circuits input is retained through the use of
storage devices, that is the memory.
Input

Ouput

Combinational
Logic Gates

Memory

In this chapter we introduce a number of common memory elements

including latches and flip-flops.
7.2 Set-Reset Latch (SR Latch)
The logical operation of the SR latch is summarized in the excitation table
below.
S

S
R

Input
S
0
0
0
0
1
1
1
1

R
0
0
1
1
0
0
1
1

Present
State
Q
0
1
0
1
0
1
0
1

Next
State
Q*
0
1
0
0
1
1
x
x

SR
Latch

Q
Q

The equation for SR latch is Q* = S + R.Q . We can classify the operation of the
latch into three modes.
Mode 1:
S=R=0. Q*=Q. The next state Q* is equal to the present state Q. So, there is no
change of state.
Mode 2:
S=1, R=0. Q* = 1, representing set operation.
Mode 3:
S=0, R=1. Q*=0, representing reset operation.
The truth table for SR latch can be written as:

S R Q Q

Mode

Q Q

Hold

Re set

Set

Pr ohibited(invalid)

Example 1:
Assume that Q=0 initially. Determine the Q waveform for the SR latch.
S
R
Q
Reset
Initial state
Q=0

Hold

Set

Hold

Reset

Hold

Output Q changes states

immediately when S or R
changes

The output of SR latch changes states immediately when S or R changes.

Flip-Flops

106

7.3 SR Flip-Flop
The operation of SR flip-flop is similar to that of the simple SR latch. The
characteristic equation is Q* = S + R.Q . The difference is that, the latch output
reacts immediately to any output changes, while the flip-flop output changes
are controlled by the clock pulse CLK. A flip-flop with a small triangle on its
CLK input indicates that this input is activated only when the clock changes
from a 0 to a 1 () occurs. This is known as the positive-going transition or
positive-edge triggered.
Input
S

SET

CLR

S
0
0
0
0
1
1
1
1

Present
State
Q
0
1
0
1
0
1
0
1

R
0
0
1
1
0
0
1
1

CLK

Next
State
Q*
0
1
0
0
1
1
x
x

The truth table can be written as

CLK S R Q Q
0 0 Q Q
0
1
1

1
0
1

0
1
0

1
0
0

Mode
Hold
Re set
Set
Pr ohibited (invalid )

Example 1:
Assume that Q=0 initially. Determine the Q waveform for the SR flip-flop.

CLK

Set

Set

Hold

Reset

S
R
Q
Hold Set

Hold Reset

Output Q changes states

(reacts) when the CLK
changes from 0 to 1

7.4 D Flip-Flop
The D flip-flop has only a single data input D and a clock input CLK. The SR
flip-flop can be converted to a D flip-flop by adding an inverter. Data is
transferred from the input D to the output Q on the 0 1 transition of the
clock pulse.
SET

S
R

CLR

SET

CLR

Q
Q

CLK D Q
0

Example 1:
Assume that Q=0 initially. Determine the Q waveform for the D flip-flop.
CLK

D
Q

7.5 D Latch
The edge-triggered D flip-flop in 7.4 will respond to the D input on the 0 to 1
clock transition. The D latch operates differently. It has an enable input E.
When E=0, the output Q is latch to the present state and cannot change even
if D changes. When E=1, the Q output is equal to D.
D

E D

Q
Q

0
1

x
0

Nochange
0

Example 1:
Assume that Q=0 initially. Determine the Q waveform for the D flip-flop.
1

E
D
Q

Output Q changes states

immediately when D
changes

Flip-Flops

108

7.6 Application of D flip-flop

Consider the simple calculator as shown below. When the number 7 is
pressed on the keyboard, a decimal 7 appears on the display. However,
when the key is released, the number 7 disappears from the output display.
To solve this problem, a 4-bit storage register has been added to store the
number. It can be said that the number 7 is latched on the display.

789
456
123
0

Encoder

Decoder

Without storage register

Gnd

DISP1

S9
74147

S8

S7

S6
S5
S4

S3
S2

S1

S0

I9
I8
I7
I6
I5
I4
I3
I2
I1

abcdefg.

74LS48
A3
A2
A1
A0

A3
A2
A1
A0

g
f
e
d
c
b
a

test
RBI RBO

789
456
123
0

4-Bit
Storage
Register

Encoder

Decoder

With memory (latch)

A 4-bit storage register can be constructed using 4 D flip-flop. The input data
is transferred into the D flip-flop on a 0 1 clock pulse.

9
4321
4321
D0
D1
D2
D3

5V
+V

Q0
Q1
Q2
Q3

CP

Load
TP1
R2
1k

9
4321

4321
D
CP
D
CP
D
CP
D
CP

V1
5V
+V

Load
R1
1k

Q
_
Q
Q
_
Q
Q
_
Q
Q
_
Q

Flip-Flops

110

SET

CLR

1
2
3
4
5
6
7
8
9
0

1
2
MSB
A
3
B
4
Enkoder
C
5
LSB
D
6
7
8
9

SET

CLR

SET

CLR

SET

CLR

Dekoder

When a number is pressed on the keyboard, the output of the OR gate is 1.

This 0 1 clock transition will transfer the data, from the encoder into the D
flip-flop. When the key is released, the number will remain lit on the sevensegment display. The number is latched on the display.

Gnd

S9
74147

S8

S7

S6
S5
S4

S3
S2

S1

S0

I9
I8
I7
I6
I5
I4
I3
I2
I1

abcdefg.

74LS48
A3
A2
A1
A0

D0
D1
D2
D3

Q0
Q1
Q2
Q3

CP

A3
A2
A1
A0

g
f
e
d
c
b
a

test
RBI RBO

7.7 Simple Calculator

This is a simple add and subtract calculator. It has two storage register A and
B. The Control Load input is used to load the number presses on the keyboard,
into register A or register B. The Add/Subtract Control = 1 for addition and 0
for subtraction.
Add two numbers 2+3.
1. Load 0 into register A and B.
Load A = 1 and Load B = 1.
Press 0.
Output of OR gate = 1. A clock transition 0 1 will transfer the
number 0 into register A and B.
Register A=0. Register B= 0. Number 0 is displayed.
2. To perform addition, Add/Sub Control = 0.
3. Load Register A = 2.
Load A = 1 and Load B = 0.
Press 2.
Output of OR gate = 1. A clock transition 0 1 will transfer the
number 2 into register A.
Number 2 is displayed.
4. Load Register B = 3.
Load B = 1 and Load A = 0.
Press 3.
Output of OR gate = 1. A clock transition 0 1 will transfer the
number 3 into register B.
5. Register A + Register B = 2+3. The answer 5 is displayed.

7 8 9
4 5 6
1 2 3
0
Encoder

Control
Load

Register
B

Register
A

Add/
Subtract
Control

4 Bit
Adder

Decoder
e

a
g

Flip-Flops
112

7 8 9
4 5 6
1 2 3
0

1
2
3
4
5
6
7
8
9
0

1
2
3
4
5
6
7
8
9

A MSB
B
C LSB
D

CLR

SET

CLR

SET

CLR

SET

CLR

SET

CLR

SET

CLR

SET

CLR

SET

CLR

SET

Register B

Control Load

Load B

Load A

Register A

Add/Subtract
Control

A1

B4

A4

B3

4 Bit Adder
A3

B2

A2

B1

C
D

1
7 Segment
Decoder

a
b
c
d
e
f
g

Flip-Flops

114

Exercises
1. Assume that Q=0 initially. Determine the Q waveform for the SR latch.
S
R
Q=0
Mode

2. Assume that Q=0 initially. Determine the Q waveform for the SR flip-flop.

CLK

S
R
Q=0
Mode

3. Assume that Q=0 initially. Determine the Q waveform for the D flip-flop.
CLK
D
Q=0
Mode