Spring 2015

Week 8 Module 44

Digital Circuits and

Systems
Pipelining Terminology + Methodology
Shankar Balachandran*
Associate Professor, CSE Department
Indian Institute of Technology Madras
*Currently a Visiting Professor at IIT Bombay

Acknowledgements

MITs Open Course Contents of 6.004

Pipelining Methodology

Pipeline Conventions

DEFINITION:

CONVENTION:

A K-Stage Pipeline(K-pipeline) is an acyclic circuit having

exactly K registers on every path from an input to an output.
A COMBINATIONAL CIRCUIT is thus a 0-stage pipeline.
Every pipeline stage, hence every K-Stage pipeline, has a register
on its OUTPUT(not on its input).

ALWAYS:
The CLOCK common to all registers must have a period sufficient
to cover propagation over
combinational paths + (input) register tPD + (output) register tSETUP

Pipelining Methodology

Latency and Throughput

The latency of a K-pipeline is K times the

clock period that is commonly fed to all
registers
Example:

Latency of 12 ns
More common, latency of so many cycles

Throughput of a K-Pipeline is the frequency

of the clock
How

many inputs can be processed per time

unit
Example: FLOPS, MIPS
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Ill-formed Pipelines

Bad Pipeline

For what values of K is the circuit a Kpipelined circuit?

Answer:

None
Pipelining Methodology

Reason:

Successive inputs get mixed:

A(Xi+1) and Yi will be processed by B

This is not a well formed pipeline

Some paths have 2 flipflops and some have one

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Pipelining Methodology

Pipelining Methodology

Pipelining Strategy

Step 1:

Step 2:

Draw a line that crosses every output in the circuit, and mark the
endpoints as terminal points.
Continue to draw new lines between the terminal points across
various circuit connections, ensuring that every connection
crosses each line in the same direction.
These lines demarcate pipeline stages.

Adding a pipeline register at every point where a

separating line crosses a connection will always generate
a valid pipeline
Strategy:

Focus on placing pipeline registers around bottleneck elements

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After Pipelining

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Pipeline Example

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Observations

1-pipeline improves neither Latency nor

Throughput.
Throughput improved by breaking long
combinational paths, allowing faster clock.
Too many stages cost Latency, dont improve
Throughput.
Back-to-back registers are often required to keep
pipeline well-formed.

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Summary of Pipelining

Advantages:

Allows us to increase throughput, by breaking up long

combinational paths and (hence) increasing clock
frequency

Disadvantages:
May increase latency...
Only as good as the weakest link: slowest step
constrains system throughput.

Isnt there a way around this weak link

problem?
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End of Week 8: Module 44

Thank You

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