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The course objective is to provide the student with a solid understanding of the
underlying mechanism and solution techniques to the above key design issues, so that
the student, when working as industrial designer, is capable of identifying the key
problem points and focus his creative attention and 90% of available resources to right
issues for 1% of the circuitry and leave the remaining 99% of circuitry to computer
automated tools or unqualified engineers.
Recap
In this course you have learnt the following
Motivation of the course
Course Objectives
It describes the areas where thin oxides are needed to implement the transistor gates
and allow implantations to form p/n type diffusions. A thin layer of SiO2is grown and
covered with SiN and this is used as mask. The bird's bead must be taken into account
while designing thin-ox.
Recap
In this lecture you have learnt the following
Gate Material
Parasitic Capacitances
Self-aligned silicon gate technology
Channel Stopper
Polysilicon deposition
Oxide Growth
Active mask or Isolation mask (thin-ox)
This technology offers advantages in the form of higher integration density (because of
the absence of well regions), complete avoidance of the latch-up problem, and lower
parasitic capacitances compared to the conventional n-well or twin-tub CMOS processes.
But this technology comes with the disadvantage of higher cost than the standard n-well
CMOS process. Yet the improvements of device performance and the absence of latchup problems can justify its use, especially in deep submicron devices.
12.4 N-well Technology
In this discussion we will concentrate on the well established n-well CMOS fabrication
technology, which requires that both nchannel and p-channel transistors be built on the
same chip substrate. To accomodate this, special regions are created with a
semiconductor type opposite to the substrate type. The regions thus formed are called
wells or tubs. In an n-type substrate, we can create a p-well or alternatively, an n-well is
created in a p-type substrate. We present here a simple n-well CMOS fabrication
technology, in which the NMOS transistor is created in the p-type substrate, and the
PMOS in the n-well, which is built-in into the p-type substrate.
Historically, fabrication started with p-well technology but now it has been completely
shifted to n-well technology. The main reason for this is that, "n-well sheet resistance
can be made lower than p-well sheet resistance" (electrons are more mobile than holes).
The simplified process sequence (shown in Figure 12.41) for the fabrication of CMOS
integrated circuits on a p-type silicon substrate is as follows:
N-well regions are created for PMOS transistors, by impurity implantation into the
substrate.
This is followed by the growth of a thick oxide in the regions surround the NMOS
and PMOS active regions.
The thin gate oxide is subsequently grown on the surface through thermal
oxidation.
After this n+ and p+ regions (source, drain and channel-stop implants) are
created.
The metallization step (creation of metal interconnects) forms the final step in this
process.
Negative photoresists are more sensitive to light, but their photolithographic resolution
is not as high as that of the positive photoresists. Hence, the use of negative
photoresists is less common in manufacturing high-density integrated circuits.
The unexposed portions of the photoresist can be removed by a solvent after the UV
exposure step. The silicon dioxide regions not covered by the hardened photoresist is
etched away by using a chemical solvent (HF acid) or dry etch (plasma etch) process.
On completion of this step, we are left with an oxide window which reaches down to the
silicon surface. Another solvent is used to strip away the remaining photoresist from the
silicon dioxide surface. The patterned silicon dioxide feature is shown in Figure 12.43
The first step of the process is the oxidation of the silicon substrate (Fig 12.44(a)),
which creates a relatively thick silicon dioxide layer on the surface. This oxide layer is
called field oxide (Fig. 12.44(b)). The field oxide is then selectively etched to expose the
silicon surface on which the transistor will be created (Fig. 12.44(c)). After this the
surface is covered with a thin, high-quality oxide layer. This oxide layer will form the
gate oxide of the MOS transistor (Fig. 12.44(d)). Then a polysilicon layer is deposited on
the thin oxide (Fig 12.44(e)). Polysilicon is used as both a gate electrode material for
MOS transistors as well as an interconnect medium in silicon integrated circuits. The
resistivity of polysilicon, which is usually high, is reduced by doping it with impurity
atoms.
Deposition is followed by patterning and etching of polysilicon layer to form the
interconnects and the MOS transistor gates (Fig. 12.44(f)). The thin gate oxide not
masked by polysilicon is also etched away exposing the bare silicon surface. The drain
and source junctions are to be formed (Fig 12.44(g)). Diffusion or ion implantation is
used to dope the entire silicon surface with a high concentration of impurities (in this
case donor atoms to produce n-type doping). Fig 12.44(h) shows two n-type regions
(source and drain junctions) in the p-type substrate as doping penetrates the exposed
areas of the silicon surface. The penetration of impurity doping into the polysilicon
reduces its resistivity. The polysilicon gate is patterned before the doping and it precisely
defines the location of the channel region and hence, the location of the source and
drain regions. Hence this process is called a self-aligning process.
The entire surface is again covered with an insulating layer of silicon dioxide after the
source and drain regions are completed (Fig 12.44(i)). Next contact windows for the
source and drain are patterned into the oxide layer (Fig. 12.44(j)). Interconnects are
formed by evaporating aluminium on the surface (Fig 12.44(k)), which is followed by
patterning and etching of the metal layer (Fig 12.44(l)). A second or third layer of
metallic interconnect can also be added after adding another oxide layer, cutting (via)
holes, depositing and patterning the metal.
Fig 12.44: Process flow for the fabrication of an n-type MOSFET on p-type silicon
We now return to the generalized fabrication sequence of n-well CMOS integrated
circuits. The following figures illustrate some of the important process steps of the
fabrication of a CMOS inverter by a top view of the lithographic masks and a crosssectional view of the relevant areas.
The n-well CMOS process starts with a moderately doped (with impurity concentration
typically less than 1015 cm-3) p-type silicon substrate. Then, an initial oxide layer is
grown on the entire surface. The first lithographic mask defines the n-well region. Donor
atoms, usually phosphorus, are implanted through this window in the oxide. Once the nwell is created, the active areas of the nMOS and pMOS transistors can be defined
The creation of the n-well region is followed by the growth of a thick field oxide in the
areas surrounding the transistor active regions, and a thin gate oxide on top of the
active regions. The two most important critical fabrication parameters are the thickness
and quality of the gate oxide. These strongly affect the operational characteristics of the
MOS transistor, as well as its long-term stability.
Chemical vapor deposition (CVD) is used for deposition of polysilicon layer and patterned
by dry (plasma) etching. The resulting polysilicon lines function as the gate electrodes of
the nMOS and the pMOS transistors and their interconnects. The polysilicon gates also
act as self-aligned masks for source and drain implantations.
The n+ and p+ regions are implanted into the substrate and into the n-well using a set
of two masks. Ohmic contacts to the substrate and to the n-well are also implanted in
this process step.
CVD is again used to deposit and insulating silicon dioxide layer over the entire wafer.
After this the contacts are defined and etched away exposing the silicon or polysilicon
contact windows. These contact windows are essential to complete the circuit
interconnections using the metal layer, which is patterned in the next step.
Metal (aluminum) is deposited over the entire chip surface using metal evaporation, and
the metal lines are patterned through etching. Since the wafer surface is non-planar, the
quality and the integrity of the metal lines created in this step are very critical and are
ultimately essential for circuit reliability.
The composite layout and the resulting cross-sectional view of the chip, showing one
nMOS and one pMOS transistor (built-in nwell), the polysilicon and metal
interconnections. The final step is to deposit the passivation layer (for protection) over
the chip, except for wire-bonding pad areas.
This completes the fabrication of the CMOS inverter using n-well technology.
Recap
In this lecture you have learnt the following
Motivation
N-well / P-well Technologies
Silicon on Insulator (SOI)
Twin well Technology
Wiring problems:
Diffusion: There is variation in doping which results in variations in resistance,
capacitance.
Poly, metal: Variations in height, width resulting in variations in resistance,
capacitance.
Shorts and opens.
Oxide problems:
Variations in height.
Lack of planarity.
Via problems:
Via may not be cut all the way through.
Undersize via has too much resistance.
Via may be too large and create short.
To reduce these problems, the design rules specify to the designer certain geometric
constraints on the layout artwork so that the patterns on the processed wafers will
preserve the topology and geometry of the designs. This consists of minimum-width and
minimum-spacing constraints and requirements between objects on the same or
different layers. Apart from following a definite set of rules, design rules also come by
experience.
13.2 Types of Design Rules
The design rules primary address two issues:
1. The geometrical reproduction of features that can be reproduced by the
maskmaking and lithographical process ,and
2. The interaction between different layers.
There are primarily two approaches in describing the design rules.
1. Linear scaling is possible only over a limited range of dimensions.
2. Scalable design rules are conservative .This results in over dimensioned and less
dense design.
3. This rule is not used in real life.
1. Scalable Design Rules (e.g. SCMOS, -based design rules):
In this approach, all rules are defined in terms of a single parameter . The rules
are so chosen that a design can be easily ported over a cross section of industrial
process ,making the layout portable .Scaling can be easily done by simply
changing the value of.
The key disadvantages of this approach are:
2. Absolute Design Rules (e.g. -based design rules ) :
In this approach, the design rules are expressed in absolute dimensions (e.g.
0.75m) and therefore can exploit the features of a given process to a maximum
degree. Here, scaling and porting is more demanding, and has to be performed
either manually or using CAD tools .Also, these rules tend to be more complex
especially for deep submicron.
The fundamental unity in the definition of a set of design rules is the minimum line
width .It stands for the minimum mask dimension that can be safely transferred to
the semiconductor material .Even for the same minimum dimension, design rules
tend to differ from company to company, and from process to process. Now, CAD
tools allow designs to migrate between compatible processes.
Two different substrates and/or wells: which are p-type for NMOS and n-type for
PMOS.
Diffusion regions (p+ and n+): which defines the area where transistors can be
formed. These regions are also called active areas. Diffusion of an inverse type is
needed to implement contacts to the well or to substrate.These are called select
regions.
Transistor gate electrodes : Polysilicon layer
Metal interconnect layers
Interlayer contacts and via layers.
The layers for typical CMOS processes are represented in various figures in terms of:
A color scheme (Mead-Conway colors).
Other color schemes designed to differentiate CMOS structures.
Varying stipple patterns
Varying line styles
An example of layer representations for CMOS inverter using above design rules is
shown below-
Recap
In this lecture you have learnt the following
Motivation
Types of Design Rules
Layer Representations
Stick Diagrams
As, Minimum line width of poly is 2 & Minimum line width of diffusion is 2
As It is necessary for the poly to completely cross active, other wise the transistor that
has been created crossing of diffusion and poly, will be shorted by diffused path of
source and drain.
Contact cut on metal
Contact window will be of 2 by 2 that is minimum feature size while metal deposition
is of 4 by 4 for reliable contacts.
In Metal
Two metal wires have 3 distance between them to overcome capacitance coupling and
high frequency coupling. Metal wires width can be as large as possible to decrease
resistance.
Buttering contact
Buttering contact is used to make poly and silicon contact. Window's original width is 4,
but on overlapping width is 2.
So actual contact area is 6 by 4.
The distance between two wells depends on the well potentials as shown above. The
reason for 8l is that if both wells are at same high potential then the depletion region
between them may touch each other causing punch-through. The reason for 6l is that if
both wells are at different potentials then depletion region of one well will be smaller, so
both depletion region will not touch each other so 6l will be good enough.
The active region has length 10 which is distributed over the followings 2 for source diffusion
2 for drain diffusion
2 for channel length
2 for source side encroachment
2 for drain side encroachment
Recap
In this lecture you have learnt the following
Background
-based Design Rules
Congratulations, you have finished Lecture 14.
The value of NMH is difference in magnitude between the minimum HIHG output voltage
of the driving gate and the minimum input HIGH voltage recognized by the receiving
gate.
Thus,
Where,
VIHmin = minimum HIGH input voltage.
VILmax = maximum LOW input voltage.
VOHmin= minimum HIGH output voltage.
VOLmax= maximum LOW output voltage.
We will describe about each regions in detailsRegion A: This region is defined by 0 =< Vin < Vtn in which the n-device is cut off
(Idsn =0), and the p-device is in the linear region. Since Idsn = IIdsp, the drain-tosource current Idsp for the p-device is also zero. But for Vdsp = Vout VDD, with
Vdsp = 0, the output voltage is Vout=VDD.
Region B: This region is characterized by Vtn =< Vin < VDD /2 in which the p-device
is in its nonsaturated region (Vds != 0) while the n-device is in saturation. The
equivalent circuit for the inverter in this region can be represented by a resistor for the
p-transistor and a current source for the n-transistor as shown in fig. 6 . The saturation
current Idsn for the n-device is obtained by setting Vgs = Vin. This results in
and
Vtn=threshold
voltage
of
n-device,
n=mobility of electrons Wn = channel width of n-device & Ln = channel length of
n-device
The current for the p-device can be obtained by noting that Vgs = ( Vin VDD ) and
Vds = (Vout VDD ). And therefore,
and Vtp =threshold
voltage of n-device, p=mobility of electrons, Wp = channel width of n-device and
Lp=channel length of n-device. The output voltage Vout can be expressed as-
This yields,
By setting,
Which implies that region C exists only for one value of Vin. We have assumed that a
MOS device in saturation behaves like an ideal current soured with drain-to-source
current being independent of Vds.In reality, as Vds increases, Ids also increases
slightly; thus region C has a finite slope. The significant factor to be noted is that in
region C, we have two current sources in series, which is an unstable condition. Thus
a small input voltage as a large effect at the output. This makes the output transition
very steep, which contrasts with the equivalent nMOS inverter characteritics.
characteritics. The above expression of Vth is particularly useful since it provides the
basis for defining the gate threshold Vinv which corresponds to the state where
Vout=Vin .This region also defines the gain of the CMOS inverter when used as a small
signal amplifier.
Region D:
Region E: This region is defined by the input condition Vin >= VDD -Vtp, in which the
pdevice is cut off (Idsp =0), and the n-device is in the linear mode. Here,
Vgsp= Vin - VDD
Which is more positive than Vtp. The output in this region is Vout=0 From the transfer
curve , it may be seen that the transition between the two states is very step.This
characteristic is very desirable because the noise immunity is maximized.
We will give an example of how to calculate quick estimate. From fig 16.22, we can write
following equations.
The expressions for the propagation delays as denoted in the figure (16.22) can be
easily seen to be
When the n-device begins to operate in the linear region, the discharge current is no
longer constant. The time tf1 taken to discharge the capacitor voltage from (VDD-Vtn)
to 0.1VDD can be obtained as before. In linear region,
From this expression we can see that the delay is directly proportional to the load
capacitance. Thus to achieve high speed circuits one has to minimize the load
capacitance seen by a gate. Secondly it is inversely proportion to the supply voltage i.e.
as the supply voltage is raised the delay time is reduced. Finally, the delay is
proportional to the n of the driving transistor so increasing the width of a transistor
decreases the delay.
Due to the symmetry of the CMOS circuit the rise time can be similarly obtained as; For
equally sized n and p transistors (where n=2p) tf=tr
Thus the fall time is faster than the rise time primarily due to different carrier mobilites
associated with the p and n devices thus if we want tf=tr we need to make n/p =1.
This implies that the channel width for the p-device must be increased to approximately
2 to 3 times that of the n-device.
The propagation delays if calculated as indicated before turn out to be,
Figure 16.35: Rise and Fall time graph of Output w.r.t Input
If we consider the rise time and fall time of the input signal as well, as shown in the fig
16.35 we have,
substituting the values of V1 and V2 and choosing the sign which puts V0 in the correct
range, we get
The nMOS is now in its linear mode of operation. The derived equation does not apply
beyond this input voltage.
Recap
In this lecture you have learnt the following
Introduction
Different Configurations with NMOS Inverter
Worries about Pseudo NMOS Inverter
Calculation of Capacitive Load
Where a1, a2 and a3 are weighing factor which are a function of technology
18.2 Design techniques for large fan in
as complementary CMOS, where the low and high level dont depend upon transistor
sizes. As a satisfactory level we keep RL>=4RD. To achieve this, (W/L)D/(W/L)L> 4.
19.2 Pass Transistor Logic
The fundamental building block of nMOS dynamic logic circuit, consisting of an nMOS
pass transistor is shown in figure 19.21.
The variation of the node voltage Vx(t)is plotted as a function of time in fig. 19.22. The
voltage rises from its initial value of 0 and reaches Vmax =VDD-Vtn after a large time.
The pass transistor will turn off when Vx = Vmax. Since Vgs= Vtn. Therefore Vx can
never attain VDD during logic 1 transfer. Thus we can use buffering to overcome this
problem.
these design logics is Dynamic logic, which reduces the number of transistors at the
same time keeps a check on the static power consumption.
Principle: A block diagram of a dynamic logic circuit is as shown in fig 19.31. This uses
NMOS block to implement its logic
The operation of this circuit can be explained in two modes.
1. Precharge
2. Evaluation
We can design the system at various layers, which are called design abstraction levels:
1. Architechture
2. Algorithm
3. Modules (or Functions)
4. Logic
5. Switch
6. Circuit
7. Device
In this course, we are only dealing with Logic, Switch and Circuit levels.
Representation examples
Behavioral
Representation
Structural Representation
Working: Notice that the input and output voltages of ig2 correspond to the output and
input voltages of ig1 respectively. It can be seen that the two voltage transfer
characteristics intersect at three points. Two of them are stable, while the middle point
is unstable. The gain at the stable points is less than unity. Thus if input is at any of
these points, it remains stable. The voltage gain at the third operating point is greater
than unity. However if the input has a small perturbation, it is amplified and led to any
of the two stable states. Hence this state is called metastable state. Since the circuit
has two stable operating points it is called bistable. The potential energy is at its
minimum at two of the three operating points, since the voltage gains of both inverters
are equal to zero. By contrast, energy attains maximum value at the operating point at
which the voltage gains of both inverters are maximum. Thus the circuit has two stable
states corresponding to the two energy minima, and one unstable state corresponding to
the potential energy maximum.
Consider the above circuit at vg1 =vg2=vinv, the unstable operating point. Assume that
input capacitance cg of each inverter is much more than output capacitance cd. The
drain current of each inverter is also equal to the gate current of other inverter.
--eq1
Where gm represents transconductance of inverter. The gate charges q1 and q2 are
--eq2
--eq6
--eq8
The initial condition is
--eq9
--eq9
Note that the magnitude of both the output voltages increases exponentially with time.
Depending on the polarity of the initial small perturbation dVo1(0) and dVo2(0) the
output voltages will diverge from there initial value of Vinv to either Vol or Voh
1. This same circuit can be used as static ram. After the data which is fed has
started circulating, the input can be removed since it keep on circulating.
2. This circuit is also called as transparent latch or level sensitive latch.
Recap
In this lecture you have learnt the following
Ratioed Logic
Pass Transistor Logic
Dynamic Logic Circuits
Solving this
We have,
Delays in a MOS gate are caused by the capacitive loads and due to the gate topology.
We will take an inverter as the unit gate and compare performance of other gates with
an inverter. A complex logic gate, which may have transistors connected in series, will
have more delay than an inverter with similar transistor sizes that drives the same load,
as they are poorer at driving current. The method of logical effort quantifies these
effects.
We will consider
as the delay unit that characterizes a given MOS process.
50ps for a typical 0.6 process.
is about
Fig 22.71: Logical efforts of basic gates with different input configurations
The electrical effort along a path through the network is simply the ratio of the
capacitance that loads the logic gate in the path to input capacitance of the first gate in
the path. We denote it by the letter 'H'.
When fanout occurs within a logic network, some of the available drive current is
directed along the path we are analyzing, and some are directed off that path. Branching
effort (b) at the output of a logic gate is defined as
Where
is the load capacitance along the path and
is the capacitance of
connections that lead off the path. If there is no branching in the path the branching
effort is unity.
Branching effort along the entire path 'B' is the product of branching effort at each of
the stages along the
path.-
Path effort (F) is defined asThe path branching and electrical effort are related to the electrical effort of each stage
as-
The path delay D is the sum of the delays of each of the stages of logic in the path.
where DF is path effort delay and P is path parasitic delay which are given as
Substituting
i.e. the product of logical effort and electrical effort of each stage should be equal to get
minimum delay. This is independent of scale of circuit and of the parasitic delay. The
delay in the two stages will differ only if the parasitic delays are different.
We can generalise this result for N stages as-
So,
Example of Minimizing delay: Consider the path from A to B involving three two input
NAND gates as in fig 23.22. The input capacitance of first gate is C and the load
capacitance is also C . Find the least delay in this path and how should the transistors be
sized to achieve least delay?
But the number of stages for minimum delay may not be the integer, so it is not feasible
to implement it. So we realise the circuit by either taking the number of stages greatest
integer of the obtained value or the one more then the greatest integer whatever gives
us the minimun delay.
Fig 23.32:
We will study about in more details in next chapter.
Recap
In this lecture you have learnt the following
Logical Effort of Multistage Logic Networks
Minimizing Delay along a Path
Few Examples
Let rbe the ratio of the delay when using sNstages to the delay when using best number
of stages, N. So,
Since
is LOW, the gate output q is set to the complement of the input d. The total logical
effort of this gate is 4; the logical effort per input for d is 2, and the logical effort of the
bundle is also 2. (Note
is 2)
. Similarly,
and
The input current to an optimized fork may divide unequally to drive its two legs. Even if
the load capacitances on the two legs of the fork are equal, it is not in general true that
the input capacitances to the two legs of the fork are equal. Because the legs have
different number of amplifiers but must operate with the same delay, their electrical
efforts may differ. The leg that can support the larger electrical effort, usually the leg
with more amplifiers, will require less input current than the other leg, and can therefore
have a smaller input capacitance. If we call the electrical efforts of the two legs
, using the notation of Fig 24.52, then
may not equal
and
and
and
. Even if
and
,
The design of a fork is a balancing act. Either leg of the fork can be made faster by
reducing its electrical effort, which is done by giving it wider transistors for its amplifier.
Doing so, however, takes input current away from the other leg of the fork and will
inevitably make it slower. A fixed value of
provides, in effect, only a certain total
width of transistor material to distribute between the first stages of the two legs; putting
wider transistors in one leg requires putting narrower transistors in the other leg. The
task of designing a minimum delay fork is really the task of allocating the available
transistor width set by
Recap
In this lecture you have learnt the following
Effect of Using Wrong Number of Stages
Dynamic Latch
Carry Propagation Gate
Dynamic Mular C-element
Fork
The logical efforts per input for inputs a and b, and the logical effort
(Eq 25.1)
(Eq 25.2)
(Eq 25.3)
Choosing the least value possible for s, such as 0.01, minimizes the logical effort of
input a. This design results in pull-down transistor of width 1.01 for input a and a
transistor of width 100 for input b. The logical effort of input a is then
almost exactly 1. The logical effort of input b becomes
total logical effort is about 35, again assuming
, or about 34 if
, or
. The
Extremely asymmetric designs, such as with s=0.1, are able to achieve a logical effort
for one input that almost matches that of an inverter, namely 1. The price of this
achievement is an enormous total logical effort, 35, as opposed to 8/3 for a symmetric
design. Moreover, the huge size of the pull-down transistor will certainly cause layout
problems, and the benefit of the reduced logical effort on input a may not be worth the
enormous area of this transistor.
Less extreme asymmetry is more practical. If s=1/4, the pull-down transistors have
widths 4/3 and 4, and the logical effort of input a is
, which is 1.1 if
. The
logical effort of input b is 2, and the total logical effort is 3.1, which is very little more
than 8/3, the total logical effort of the asymmetric design. This design achieves a logical
effort for the favored input, a, that is only 10% greater than that of an inverter, without
a huge increase in total logical effort.
25.2 Applications of Asymmetric Logic Gates
The principal application of asymmetric logic gates occurs when one path must be very
fast. For example, in a ripple carry adder or counter, the carry path must be fast. The
best design uses an asymmetric circuit that speeds the carry even though it retards the
sum output.
Paradoxically, another important use of asymmetric logic gates occurs when a signal
path may be unusually slow, as in a reset signal. Figure 25.21 shows a design for a
buffer amplifier whose output is forced LOW, when the reset signal,
, is LOW. The
buffer consists of two stages: a NAND gate and an inverter. During normal operation,
when
is HIGH, the first stage has an output drive equivalent to that of an inverter
with pull-down width 6 and pull-up width 12, but the capacitive load on the in input is
slightly larger than that of the corresponding inverter:
(Eq 25.4)
is LOW,
This circuit takes advantage of slow response allowed to changes on by using the
smallest pull-up transistor possible. This choice reduces the area required to lay out the
gate, partially compensating for the large area pull-down transistor. Area can be further
reduced by sharing the the reset pull-down among multiple gates that switch at different
times; this is known as Virtual Ground technique.
(Eq 25.7)
(Eq 25.8)
Equation 25.7 models the delay incurred when a network produces a rising output
transition. In this equation, the first sum tallies the delay of falling transitions at the
output of stages whose distance from the last stage is odd, and the second tallies the
delay of the rising transitions at the output of stages whose distance from the last stage
is even. Similarly Equation 25.8 models the falling output transition.
A reasonable goal is to minimize the average delay:
(Eq 25.9)
Then we have for the average delay:
(Eq 25.10)
Recap
by the
(Eq 26.1)
From this relation it can be seen that as temperature increases, it leads to increase in
the number of intrinsic carriers in the semiconductor. The majority carriers, contributed
by the impurity atoms, are less affected by increase in temperature. Hence the device
becomes more intrinsic.
As temperature increases, leakage current, which directly depends on minority carrier
concentration, increases which leads to further increase in temperature. Ultimately, the
device might break down, if the increase in temperature is not taken care of by time to
time removal of the dissipated heat.
A ON device wont be affected much by minority carrier increase, but will be affected by
VT and which decrease with increase in temperature and lead to change in ID. Hence
the device performance might not meet the required specifications. Also, power
where,
l = length, A = Area and c= thermal conductivity of the heat sink
From the above relation it can be seen that large c implies smaller . is also given by
the relation,
(Eq 26.3)
Using this relation, we can see that for a given power dissipation, PD
(Eq 26.4)
where,
Tj= junction temperature, and
Ta= ambient temperature.
Heat sink materials are generally coated black to radiate more energy
26.4 Components of Power Dissipation
Unlike bipolar technologies, here a majority of power dissipation is static, the bulk of
power dissipation in properly designed CMOS circuits is the dynamic charging and
discharging of capacitances. Thus, a majority of the low power design methodology is
dedicated to reducing this predominant factor of power dissipation.
There are three main sources of power dissipation:
Static power dissipation (PS)
Dynamic power dissipation (DS)
Short circuit power dissipation (PSC)
Thus the total power dissipation,
, is
(Eq 26.5)
Fig 26.51: CMOS inverter model for static power dissipation evaluation
When input = '0', the associated n-device is off and the p-device is on. The output
voltage is
or logic '1'. When the input = '1', the associated n-device is on and the
to
, the
, is zero.
However, there is some small static dissipation due to reverse bias leakage between
diffusion regions and the substrate. In addition, subthreshold conduction can contribute
to the static dissipation. A simple model that describes the parasitic diodes for a CMOS
inverter should be looked at in order to have an understanding of the leakage involved
in the device. The source-drain diffusions and the n-well diffusion form parasitic diodes.
In the model, a parasitic diode exists between n-well and the substrate. Since parasitic
diodes are reverse biased, only their leakage current contributes to static power
dissipation. The leakage current is described by the diode equation:
(Eq 26.6)
where,
is= reverse saturation current
V = diode voltage
q = electronic charge
k = Boltzmann's constant
T = temperature
The static power dissipation is the product of the device leakage current and the supply
voltage:
(Eq 26.7)
26.6 Dynamic Power Dissipation
During switching, either from '0' to '1' or, alternatively, from '1' to '0', both n- and ptransistors are on for a short period of time. This results in a short current pulse from
to
load. This latter term is usually the dominant term. The current pulse from
to
results in a 'short-circuit' dissipation that is dependent on the input rise/fall time, the
load capacitance and the gate design.
dissipated during switching for a square-wave input, Vin, having a repetition frequency
of
, is given by
(Eq 26.8)
where
= n-device transient current
= p-device transient current
For a step input and with
(Eq 26.9)
(Eq 26.10)
with
resulting in
,
(Eq 26.11)
Thus for a repetitive step input the average power that is dissipated is proportional to
the energy required to charge and discharge the circuit capacitance. The important
factor to be noted here is that Eq 26.11 shows power to be proportional to switching
frequency but independent of device parameters. The power dissipation also depends on
the switching activity, denoted by, .
The equation can then can be written as
(Eq 26.12)
As can be seen from Eq (26.12), the power dissipated can be reduced by reducing either
the clock frequency,
, or the load capacitance,
, or the rail voltage,
, or the
switching activity parameter, . Reducing the clock frequency is the easiest thing to do,
but it seriously affects the performance of the chip. Applications where power is
paramount, this is approach can be used satisfactorily. Another method to reduce the
dissipated power is to lower the load capacitance,
. But this method is more difficult
than the previous approach because it involves conscientious system design, so that
there are fewer wires, smaller pins, smaller fan-out, smaller devices etc.
Power dissipation can also be reduced by reducing the rail voltage,
. But this can be
done only through device technology. Also rail voltage is a standard agreed to in many
cases by the semiconductor industry, hence we do not have much control over this
parameter. Also rail voltage is strongly dependent on the threshold voltage and the
noise margin.
Some special techniques are also used to reduce power dissipation. The first one
involves the use of pipelining to operate the internal logic at a lower clock than the i/o
frequency. The other technique is to reduce switching activity, , by optimizing
algorithms, architecture, logic topology and using special encoding techniques.
26.8 Short-Circuit Power Dissipation
The short-circuit power dissipation is given by
(Eq 26.13)
For the input waveform shown in Fig 26.81a, which depicts the short-circuit (Fig26.81b)
in an unloaded inverter,
(Eq 26.14)
assuming that
With
and
where tp is the period of the waveform. This derivation is for an unloaded inverter. It
shows that the short-circuit current is dependent on and the input waveform rise and
fall times. Slow rise times on nodes can result in significant (20%) short-circuit power
dissipation for loaded inverters. Thus it is good practice to keep all edges fast if power
dissipation is a concern. As the load capacitance is increased the signifance of the shortcircuit dissipation is reduced by the capacitive dissipation PD.
Recap
In this lecture you have learnt the following
Motivation
Effect of Power Disipation
How to Reduce Temperature
Components of Power Disipation
Static Power Dissipation
Dynamic Power Dissipation
Methods to Reduce Power Disipation
Short-Circuit Power Dissipation
Congratulations, you have finished Lecture 26.
Size: Depending upon the level of abstraction, different means are used to
express the size of the memory unit. A circuit designer usually expresses memory
in terms of bits, which are equivalent to the number of individual cells need to
store the data. Going up one level in the hierarchy to the chip design level, it is
common to express memory in terms of bytes, which is a group of 8 bits. And on
a system level, it can be expressed in terms of words or pages, which are in turn
collection of bytes.
Though this approach resolves the select problem, it does not address the issues of the
memory aspect ratio. For an N-word memory, with a word length of M, the aspect ratio
will be nearly N:M, which is very difficult to implement for large values of N. Also such
sort of a design slows down the circuit very much. This is because, the vertical wires
connecting the storage cells to the inputs/outputs become excessively long. To address
this problem, memory arrays are organized so that the vertical and horizontal
dimensions are of the same order of magnitude, making the aspect ratio close to unity.
To route the correct word to the input/output terminals, an extra circuit called column
decoder is needed. The address word is partitioned into column address (A0 to AK-1)
and row address (AK-1 to AL-1). The row address enables one row of the memory for
read/write, while the column address picks one particular word from the selected row.
access times in the order of a few nanoseconds. Hence SRAMs are used as level 2 cache
memory.
Dynamic RAMs do not use flip-flops, but instead are an array of cells, each containing a
transistor and a tiny capacitor. '0's and '1's can be stored by charging or discharging the
capacitors. The electric charge tends to leak out and hence each bit in a DRAM must be
refreshed every few milliseconds to prevent loss of data. This requires external logic to
take care of refreshing which makes interfacing of DRAMs more complex than SRAMs.
This disadvantage is compensated by their larger capacities. A high packing density is
achieved since DRAMs require only one transistor and one capacitor per bit. This makes
them ideal to build main memories. But DRAMs are slower having delays in the order
tens of nanoseconds. Thus the combination of static RAM cache and a dynamic RAM
main memory attempts to combine the good properties of each.
Recap
transistors. The access transistors are turned on whenever a word line is activated for
read or write operation, connecting the cell to the complementary bit line columns.
and
When none of the word lines is selected, the pass transistors M3 and M4 are turned off
and the data is retained in all memory cells. The column capacitances are charged by
the pull-up transistors P1 and P2. The voltages across the column capacitors reach
VDD - VT.
28.4 READ Operation
Consider a data read operation, shown in Figure 28.41, assuming that logic '0' is stored
in the cell. The transistors M2 and M5 are turned off, while the transistors M1 and M6
operate in linear mode. Thus internal node voltages are V1 = 0 and V2 = VDD before the
cell access transistors are turned on. The active transistors at the beginning of data read
operation are shown in Figure 28.41.
(Eq 28.2)
(Eq 28.3)
28.5 WRITE Operation
Consider the write '0' operation assuming that logic '1' is stored in the SRAM cell
initially. Figure 28.51 shows the voltage levels in the CMOS SRAM cell at the beginning
of the data write operation. The transistors M1 and M6 are turned off, while M2 and M5
are operating in the linear mode. Thus the internal node voltage V1 = VDD and V2 = 0
before the access transistors are turned on. The column voltage Vb is forced to '0' by
the write circuitry. Once M3 and M4 are turned on, we expect the nodal voltage V2 to
remain below the threshold voltage of M1, since M2 and M4 are designed according to
Eq. 28.1.
(Eq 28.4)
(Eq 28.5)
28.6 WRITE Circuit
The principle of write circuit is to assert voltage of one of the columns to a low level.
This can be achieved by connecting either
or
to ground through transistor M3
and either of M2 or M1. The transistor M3 is driven by the column decoder selecting the
specified column. The transistor M1 is on only in the presence of the write enable signal
and when the data bit to be written is '0'. The transistor M2 is on only in the
presence of the write signal
and when the data bit to be written is '1'. The circuit
for write operation is shown in Figure 28.61
Recap
In this lecture you have learnt the following
SRAM Basics
CMOS SRAM Cell
CMOS SRAM Cell Design
READ Operation
WRITE Operation
in nanoseconds (billionths of a second). e.g. a memory chip rating of 70ns means that it
takes 70 nanoseconds to completely read and recharge each cell.
The capacitor in a dynamic RAM memory cell is like a leaky bucket. Dynamic RAM has to
be dynamically refreshed all of the time or it forgets what it is holding. This refreshing
takes time and slows down the memory.
29.2 Differential Operation In Dynamic RAMs
The sense amplifier responds to difference in signals appearing between the bit lines. It
is capable of rejecting interference signals that are common to both lines, such as those
caused by capacitive coupling from the word lines. For this common-mode to be
effective, both sides of the amplifier must be matched, taking into account the circuit
that feed each side. This is required in order to make the inherently single ended output
of the DRAM cell appear differential.
Single To Differential Conversion:
Large memories (>1Mbit) that are exceedingly prone to noise disturbances resort to
translating the single ended sensing problem into a differential one. The basic concept
behind the single to differential is demonstrated in Figure 29.21
and their voltages are equalized. At the same time, the capacitors of
) of v or v0
depending on whether a "1" or "0" is stored in the cell. Meanwhile the other half of the
line will have its voltage held equal to that of Cd (i.e.
) the result is a differential
signal that the sense amplifier detects and amplifies when it is enabled. As usual by the
end of the regenerative process, the amplifier will cause the voltage on one half of the
line to become VDD and that on the other half to become 0.
, where
If VS = 0
then
Let the capacitance per unit length of bitline be CB and the storage capacitance of the
DRAM cell be CS. If there are n such sections (as shown) then the net bit capacitance of
the bitline is nCB.
Let the bitline be precharged to VP. So when the bitline is connected to the capacitance
of the DRAM cell, the net voltage will be some intermediate voltage due to charge
sharing and is given by:
(Eq 29.1)
A term Charge Transfer Ratio is defined in this context as
(Eq 29.2)
where
is defined as
For a particular technology, CB is fixed. So only CS can be changed. When the bitline is
connected to storage capacitor, the change of voltage at the bitline is given by
(Eq 29.3)
For good design the value of
(the change in voltage at bitline) should be as high
as possible, so that it will allow the sensor to sense the bit correctly and quickly.
Increase in
requires CTR to increase. That leads to increase in the value of n. n
depends on CB and CS. Thus to increase n the storage capacitance CS can be increased
or the bitline capacitance CB can be decreased or both can be done. However increasing
the value of storage capacitance requires larger area.
(Eq 29.4)
Large area leads to large storage capacitance. Large storage capacitance leads to large
change in bit voltage
and therefore the access time will be small. DRAM cell with
small access time can be designed by improvement on cell itself and the sense amplifier.
Module 2 : MOSFET
Lecture 3 : Introduction to MOSFET
Objectives
In this course you will learn the following:
Basic MOS Structure
Types of MOSFET
MOSFET I-V Modelling
3.1 Basic MOSFET Structure
In the introduction to a system, we got an overview of various levels of design, viz.
Architectural level design, Program level design, Functional level design and Logic level
design. However we can't understand the levels of design unless we are exposed to the
basics of operation of the devices currently used to realize the logic circuits, viz.,
MOSFET (Metal Oxide Semiconductor Field Effect Transistor). So in this section, we'll
study the basic structure of MOSFET.
The cross-sectional and top/bottom view of MOSFET are as in figures 3.11 and 3.12
given below :
An n-type MOSFET consists of a source and a drain, two highly conducting n-type
semiconductor regions which are separated from the p-type substrate by reverse-biased
p-n diodes. A metal or poly crystalline gate covers the region between the source and
drain, but is isolated from the semiconductor by the gate oxide.
3.2 Types of MOSFET
MOSFETs are divided into two types viz. p-MOSFET and n-MOSFET depending upon its
type of source and drain.
The combination of a n-MOSFET and a p-MOSFET (as shown in figure 3.21) is called
cMOSFET which is the mostly used as MOSFET transistor. We will look at it in more
detail later.
3.3 MOSFET I-V Modelling
We are interested in finding the outputcharacteristics ( ) and the transfer charcteristics (
) of the MOSFET. In other words, we can find out both if we can formulate a
mathematical equation of the form:
ntutively, we can say that voltage level specifications and the material parameters
cannot be altered by designers. So the only tools in the designer's hands with which
he/she can improve the performance of the device are its dimensions, W and L (shown
in top view of MOSFET fig 2). In fact, the most important parameter in the device
simulations is ratio of W and L.
The equations governing the output and transfer characteristics of an n-MOSFET and
p-MOSFET are :
p-MOSFET:
n-MOSFET:
Linear
Saturation
Linear
Saturation
The output characteristics plotted for few fixed values of for p-MOSFET and n-MOSFET
are shown next :
The transfer characteristics of both p-MOSFET and n-MOSFET are plotted for a fixed
value of as shown next :
Note: From now onwards in the lectures, we will symbolize MOSFET by MOS.
3.4 C-V Characteristics of a MOS Capacitor
As we have seen earlier, there is an oxide layer below Gate terminal. Since oxide is a
very good insulator, it contributes to an oxide capacitance in the circuit. Normally, the
capacitance value of a capacitor doesn't change with values of voltage applied across its
terminals. However, this is not the case with MOS capacitor. We find that the
capacitance of MOS capacitor changes its value with the variation in Gate voltage. This is
because application of gate voltage results in the band bending of silicon substrate and
hence variation in charge concentration at Si-SiO2 interface. Also we can see (from
fig.3.42 ) that the curve splits into two (reason will be explained later), after a certain
voltage, depending upon the frequency (high or low) of AC voltage applied at the gate.
This voltage is called the threshold voltage(Vth) of MOS capacitor.
Recap
In this lecture you have learnt the following
Basic MOS Structure
Types of MOSFET
MOSFET I-V Modelling
Congratulations, you have finished Lecture 3.
and
Fig 30.22: Circuit for reading and writing data into cell
The circuits shown in the previous page are used to write and read the data to and from
the cell. When a read operation is to be performed,
at the same time is made LOW. As a result the data present on the
and
lines
are transferred to the input of the sense amplifier (Sense amplifier operation will be
discussed shortly). The sense amplifier then senses the data and gives the output.
During the write operation,
and
and
lines respectively.
However the read and write operation on a particular cell takes place only if the cell is
enabled by the corresponding row(Word) and column(Digit) lines. It is important to
remember that before every read operation, the
and
are precharged to a
voltage (usually VDD/2). During read operation, one of the two BIT (
or
) lines
discharges slightly whereas the other line charges to a voltage slightly greater than its
precharged value. This difference in these voltages is detected by the sense amplifier to
produce and output voltage, which corresponds to the stored value in the cell which is
read. Care should be taken in sizing the transistors to ensure that the data stored in the
cell does not change its value.
30.3 Sense Amplifier
The circuit shown in Figure 30.31 is the sense amplifier used to read data from the cell.
As soon as the SE signal goes HIGH the amplifier senses the difference between the
and
voltages and produces an output voltage appropriately. The access time
of the memory, which is defined as the time between the initiation of the read operation
and the appearance of the output, mainly depends on the performance of the sense
amplifier. So the design of the sense amplifier forms the main criteria for the design of
memories. The one that is shown here is a simple sense amplifier.
Fig 30.32: Block Diagram Of A Memory Cell With All Its Peripherals
30.4 Another Type of Sensing
and
and
lines.
As mentioned earlier, the access time of the memory mainly depends on the
performance of the sense amplifier. In contrast with the simple sense amplifier shown
earlier, Figure 30.42 shows an amplifier which is somewhat complicated to improve the
performance.
Recap
In this lecture you have learnt the following
Introduction
SRAM and its Peripherals
DRAM and its Peripherals
Congratulations, you have finished Lecture 30.
final metallization step. Figure 31.23 shows nMOS transistors in a NOR ROM array,
forming the intersection of two metal lines and two polysilicon word lines. To save silicon
area, the transistors in every two rows are arranged to share a common ground line,
also routed in n-type diffusion. To store a "0"-bit at a particular address location, the
drain diffusion of the corresponding transistor must be connected to the metal bit line
via a metal-to-diffusion contact. Omission of this contact, on the other hand, results in
stored "1"-bit.
Figure 31.25 shows a different type of NOR ROM layout implementation which is based
on deactivation of the nMOS transistor by raising their threshold voltage through
channel implants. In this case, all nMOS transistors are already connected to the column
lines: therefore, storing a "1"-bit at a particular location by omitting the corresponding
the drain contact is not possible. Instead, the nMOS transistor corresponding to the
stored "1"-bit can be deactivated, i.e. permanently turned off, by raising its threshold
voltage above the VCH level through a selective channel implant during fabrication.
Recap
In this lecture you have learnt the following
Introduction to Semiconductor Read Only Memory (ROM)
NOR based ROM Array
NAND based ROM Array
Congratulations, you have finished Lecture 31.
When a voltage of approximately 10V is applied over the thin insulator, electrons can
move to and from the floating gate through tunneling.
The main advantage of this programming approach is that it is reversible; that is,
erasing is simply achieved by reversing the voltage applied during the writing process.
Injecting electrons onto the floating gate raises the threshold, while the reverse
operation lowers it. This bidirectionality, however, introduces a threshold control
problem: removing too much charge from the floating gate results in a depletion device
that cannot be turned off by the standard wordline signals. Notice that the resulting
threshold voltage depends on initial charge on the gate, as well as the applied
programming voltages. It is a strong function of the oxide thickness, which is subject to
non-neglible variations over the die. To remedy this problem, an extra transistor
connected in series with the floating gate transistor is added to the EEPROM cell. This
transistor acts as the access device during the read operation, while the FLOTOX
transistor performs the storage function. This is in contrast to the EPROM cell, where the
FAMOS transistor acts as both the programming and access device.
The EEPROM cell with its two transistors is larger than its EPROM counterpart. This area
penalty is further aggravated by the fact that the FLOTOX device is intrinsically larger
than the FAMOS transistor due to the extra area of the tunneling oxide. Additionally,
fabrication of very thin oxide is a challenging and costly manufacturing step. Thus
EEPROM components pack less bits for more cost than EPROMs. On the positive side
EEPROM offer high versatility. They also tend to last longer, as they can support upto
100,000 erase/write cycles. Repeated programming causes a drift in the threshold
voltage due to permanently trapped charges in the SiO2.This finally leads to malfunction
or the inability to reprogram the device.
Recap
In this lecture you have learnt the following
Non-Volatile READ-WRITE Memory
The Floating Gate Transistor
Erasable Programmable Read Only Memory (EPROM)
Electrically Erasable Programmable Read Only Memory (E2PROM)
Whenever body comes in contact with plastic or other insulating material, static charge
is generated. It can be a very small charge, as low as nano Coulombs, but it can cause
potential damage to MOS devices, as voltages are pretty high.
We know that
Q = CV
V = Q/C
V = It/C
Let us consider a modest 1pF capacitor, in which, this 1nC charge is put (can be through
a 100uA current for a millisec). This results in
SiO2 breakdown voltage is 109 volts/meter. If gate oxide is about 0.1um thick, say;
Maximum allowable voltage is
.
This can easily be generated by walking across a carpet!! A human touch can produce
instanteous voltages of 20,000 volts!
A typical solution of the ESD protection problem is to use clamping diodes implemented
using MOS transistors with gates tied up to either GND for nMOS transistors, or to VDD
for pMOS transistors as shown in Figure 33.21. For normal range of input voltages these
transistors are in the OFF state. If the input voltage builds up above (or below) a certain
level, one of the transistors starts to conduct clamping the input voltage at the same
level.
These clamping transistors are very big structures consisting of a number of transistors
connected in parallel, and are able to sustain significant current. The thick field NMOS
used design is not suitable for deep submicron processes, and the thin field oxide NMOS
presents oxide breakdown problems while interfacing between blocks with high power
supply voltages.
Scaling of VLSI devices have reduced the dimensions of all structures used in ICs and
this has increased their susceptibility to ESD damage. Hence ESD protection issues are
becoming increasingly important for deep submicron technologies. The gate oxide
thicknesses are approaching the tunneling regime of around 35 Angstroms. From an
ESD perspective, the important issue is whether the oxide breakdown is reached before
the protection devices are able to turn on and protect them!
33.3 Output Buffer
The intra-chip buffer circuits are relatively well known. They are fast, and need only be
as big as needed to drive their particular load capacitances. However, in the inter-chip
buffer design case, there are some very important limitations. First, these buffers must
be able to drive large capacitive loads, as they are driving off-chip signals, which
means driving I/O pads, parasitic board capacitances, and capacitances on other chips.
Adding a few picofarads of capacitance at the output node is really inconsequential, and
shouldnt significantly degrade the propagation delay through this structure. So, the O/P
load for worst case design is considered to be 50 times normal load, approximately
50pF. The simplest driver for the output pad consists of a pair of inverters with large
transistors in addition to the standard ESD protection circuitry. The driver must be able
to supply enough current (must have enough driving capability) to achieve satisfactory
rise and fall times (tr, tf) for a given capacitive load. In addition the driver must meet
any required DC characteristics regarding the levels of output voltages for a given load
type, viz. CMOS or TTL.
The final result of the latch-up is the formation of a short-circuit (a low impedance path)
between VDD and GND which results in the destruction of the MOS transistor.
33.6 Prevention of Latch-Up
Place substrate and well contacts as close as possible to the source connections
Use minimum area p-wells (in case of twin-tub technology or n-type substrate) so
that the p-well photocurrent can be minimized during transient pulses
Source diffusion regions of pMOS transistors should be placed so that they lie
along equipotential lines when currents flow between VDD and p-wells. In some nwell I/O circuits, wells are eliminated by using only nMOS transistors.
Layout n- and p-channel transistors such that all nMOS transistors are placed close
to GND and pMOS transistors are placed close to VDD rails. Also maintain
sufficient spacings between pMOS and nMOS transistors.
Recap
In this lecture you have learnt the following
Introduction
Electrostatic Discharge
Output Buffer
Tri-state Output Circuit
Latch-Up
Prevention of Latch-Up
Module 2 : MOSFET
Lecture 4 : MOS Capacitor
Objectives
In this course you will learn the following
MOS as Capacitor
Modes of operation
Capacitance calculation of MOS capacitor
4.1 MOS as Capacitor
Refering to fig. 4.1, we can see there is an oxide layer below the Gate terminal. Since
oxide is a very good insulator, it contributes to an oxide capacitance in the circuit.
By Gauss's Law:
Also by thermal equilibrium:
where p and n are hole and electron concentrations of substrate and is hole or electron
concentration of the corresponding intrinsic seminconductor.
We see that if we keep making more and more -ve, the charges Qs and Qm keep
increasing. Thus, it is acting like a good parallel plate capacitor. Its capacitance can be
given as-
where
is the substrate acceptor density,
the surface potential at substrate.
as a function of
as
is
The depletion region grows with increased voltage across the capacitor until strong
inversion is reached. After that, further increase in the voltage results in inversion rather
than more depletion. Thus the maximum depletion width is:
Also,
Therefore at
Earlier due to low electric field, the electron-hole pairs formed below the oxide interface
recombine. However, once the electric field increases, the electron-hole pairs formed are
not able to recombine. So the free electron concentration increases.
By Kirchoff's law,
is given by:
Recap
In this lecture you have learnt the following
MOS as Capacitor
Modes of operation
Capacitance calculation of MOS capacitor
Module 2 : MOSFET
Lecture 5 : MOS Capacitor (Contd...)
Objectives
In this course you will learn the following
Threshold Voltage Calculation
C-V characteristics
Oxide Charge Correction
5.1 Threshold Voltage Calculation
Threshold voltage is that gate voltage at which the surface band bending is twice
Where
We know that the depth of depletion region for
by,
is between 0 and
is given by
and is given
where
Beyond threshold, the total charge QD in the seminconductor has to balance the charge
on gate electrode, Qs i.e.
where we define the charge in the inversion
layer as a quantity which needs to be determined.
This leads to following expression for gate voltage-
In case of depletion, there in no inversion layer charge, so Qi =0, i.e. gate voltage
becomes
The second term in second equality of last expression states our basic assumption,
namely that any change in gate voltage beyond the threshold requires a change in
inversion layer charge. Also from the same expression, we obtain threshold voltage as :
Module 2 : MOSFET
Lecture 6 : MOSFET I-V characteristics
Objectives
In this course you will learn the following
Derivation of I-V relationship
Channel length modulation and body bias effect
6.1 derivation of I-V relationship
In this section, the relation between
and
Now we turn our attention to evaluate the resistance of the infinitesimal element of
length dy along the channel (as shown in fig 6.21).
Assuming that only drift current is present and hence applying Ohm's law, we get :
Now using
as:
Now substituting Qn(y) from eqn (6.21) in eqn (6.27), we will get:
The drain current first increases linearly with the applied drain-to-source voltage, but
then reaches a maximum value. This occurs due to the formation of depletion region
between pinch-off point and drain. This behavior is known as drain saturation which is
observed for
Length modulation. This in MOSFET is caused by the increase in depletion layer width
at the drain as the drain voltage is increased. This leads to a shorter channel length
(reduced by
) and increased drain current. When the channel length of MOSFET is
decreased and MOSFET is operated beyond channel pinch-off, the relative importance of
pinchoff length
with respect to physical length is increased. This effect can be
included in saturation current as :
Here
Till now we assumed that the body of MOSFET is to be grounded. We will now take effect
of body bias into account i.e. body being applied a negative voltage in case of nMOSFET. Application of VSB > 0 increases the potential build up across the
semiconductor. Depletion region widens in order to compensate for the extra required
field, which implies higher VT. Viewing it from the point of energy band diagram, a
higher potential needs to be applied to the gate in order to bend the bands by the same
amount in order to create the same electron concentration in the channel. With the
application to the body bias, it modulates to the threshold voltage governed by the
threshold voltage governed by the following equations:
where
Recap
In this lecture you have learnt the following:
Derivation of I-V relationship
Channel length modulation and body bias effect
Module 2 : MOSFET
Lecture 7: Advanced Topics
Objectives
In this course you will learn the following
Motivation for Scaling
Types of Scaling
Short channel effect
Velocity saturation
7.1 Motivation for Scaling
The reduction of the dimensions of a MOSFET has been dramatic during the last three
decades. Starting at a minimum feature length of 10 mm in 1970 the gate length was
gradually reduced to 0.15 mm minimum feature size in 2000, resulting in a 13%
reduction per year. Proper scaling of MOSFET however requires not only a size reduction
of the gate length and width but also requires a reduction of all other dimensions
including the gate/source and gate/drain alignment, the oxide thickness and the
depletion layer widths. Scaling of the depletion layer widths also implies scaling of the
substrate doping density.
In short, we will study simplified guidelines for shrinking device dimensions to increase
transistor density & operating frequency and reduction in power dissipation & gate
delays.
7.2 Types of Scaling
Two types of scaling are common:
1) constant field scaling and
2) constant voltage scaling.
Constant field scaling yields the largest reduction in the power-delay product of a single
transistor. However, it requires a reduction in the power supply voltage as one
decreases the minimum feature size.
Constant voltage scaling does not have this problem and is therefore the preferred
scaling method since it provides voltage compatibility with older circuit technologies. The
disadvantage of constant voltage scaling is that the electric field increases as the
minimum feature length is reduced. This leads to velocity saturation, mobility
degradation, increased leakage currents and lower breakdown voltages.
After scaling, the different Mosfet parameters will be converted as given by table below:
Before Scaling After Constant Field Scaling After Constant Voltage Scaling
Recap
In this lecture you have learnt the following
Motivation for Scaling
Types of Scaling
Short channel effect
Velocity saturation
Module 2 : MOSFET
Lecture 8 : Short Channel Effects
Objectives
In this course you will learn the following
Motivation
Mobility degradation
Subthreshold current
Threshold voltage variation
Drain induced barrier lowering (DIBL)
Drain punch through
Hot carrier effect
Surface states and interface trapped charge
8.1 Motivation
As seen in the last lecture as channel length is reduced, departures from long channel
behaviour may occur. These departures, which are called Short Channel Effects, arise
as results of a two-dimensional potential distribution and high electric fields in the
channel region.
For a given channel doping concentration, as the channel length is reduced, the
depletion layer widths of source and drain junctions become comparable to channel
length. The potential distribution in the channel now depends on both the tranverse field
Ex(controlled by the gate voltage and back-surface bias) and the longitudinal field
Ey(controlled by the drain bias). In other words, the potential distribution becomes two
dimensional, and the gradual channel approximation (i.e. Ex >> Ey) is no longer valid.
This two dimensional potential results in the degradation of the threshold behaviour,
dependence of threshold voltage on the channel length & biasing voltages and failure of
the current saturation due to punch through effect.
In further sections, we will study various effects due to short channel length in MOSFET.
8.2 Mobility Degradation
Mobility is important because the current in MOSFET depends upon mobility of charge
carriers(holes and electrons).
Lateral Field Effect: In case of short channels, as the lateral field is increased,
the channel mobility becomes field-dependent and eventually velocity saturation
occurs (which was referred to in the previous lecture). This results in current
saturation.
ii.
Vertical Field Effect: As the vertical electric field also increases on shrinking the
channel lengths, it results in scattering of carriers near the surface. Hence the
surface mobility reduces (Also explained by the mobility dependence equation
given below).
Thus for short channels, we can see (in the figure 8.2) the mobility degradation which
occurs due to velocity saturation and scattering of carriers.
such carrier diffusion from source to drain can make it impossible to turn off the device
below threshold. The subthreshold current is made worse by the DIBL effect (will be
explained in later sections) which increases the injection of electrons from the source.
8.4 Threshold Voltage variation with Channel Length
Transit Time: As seen in previous lecture, the short channel results in velocity
saturation over part of the channel. So the argument used to derive the transit time for
long channel MOSFET is no longer valid for short channel MOSFETs. We note that the
transit time will be larger if electrons were moving at maximum speed all over the
channel. Thus,
Figure 8.42 shows that the transit time of a device operating in the 'flat' part of IDSVGS characteristics curve which concludes that transit time cannot be decreased by
increasing further VGS.
Quantum Mechanical Increase Effect: Another effect of quantum mechanics that also
increases with scaling, is a shift in the surface potential required for strong inversion.
This effect arises from so called "energy quantization" of confined particles which
preludes electrons and holes from existing at zero energy in the conduction or valence
bands. It is a direct consequence of the coupled Poisson-Schrodinger equation
solution. This surface potential shift manifests itself as an increase in |VT| which for the
long devices is given by
Above equation tells that |VT| increases as devices are scaled down.
8.5 Drain Induced Barrier Lowering (DIBL)
drain depletion region continues to increase with the bias, it can actually interact with
the source to channel junction and hence lowers the potential barrier. This problem is
known as Drain Induced Barrier Lowering (DIBL). When the source junction barrier
is reduced, electrons are easily injected into the channel and the gate voltage has no
longer any control over the drain current.
In DIBL case,
For figure 8.5, we can observe that under extreme conditions of encroaching source and
drain depletion regions, the two curves can meet.
8.6 Drain Punch Through
When the drain is at high enough voltage with respect to the source, the depletion
region around the drain may extend to the source, causing current to flow irrespective of
gate voltage (i.e. even if gate voltage is zero). This is known as Drain Punch Through
condition and the punch through voltage VPT given by:
So when channel length L decreases (i.e. short channel length case), punch through
voltage rapidly decreases.
8.7 Hot Carrier Effect
Electric fields tend to be increased at smaller geometries, since device voltages are
difficult to scale to arbitrarily small values. As a result, various hot carrier effects appear
in short channel devices. The field in the reversed biased drain junction can lead to
impact ionization and carrier multiplication. The resulting holes contribute to substrate
current and some may move to the source, where they lower source barrier and result in
electron injected from source into p-region. In fact n-p-n transistor can result within
source channel drain configuration and prevent gate control of the current.
Another hot electron effect is the transport of the energetic electrons over (or tunneling
through) the barrier into the oxide. Such electrons become trapped in the oxide, where
they change the threshold voltage and I-V characteristics of the device. Hot electron
effects can be reduced by reducing the doping in the source and drain regions, so that
the junction fields are smaller. However lightly doped source and drain regions are
incompatible with small geometry devices because of contact resistances and other
similar problems. A compromise design of MOSFET, called Lightly Doped Drain (LDD),
using two doping levels with heavy doping over most of the source and drain areas with
light doping in a region adjacent to the channel. The LDD structure decreases the field
between drain and channel regions, thereby reduces injection into the oxide, impact
ionization and other hot electron effects.
In order to create patterns on the wafer, the required pattern is first formed in the
reticles or photomasks. The pattern on reticle or mask is then transfered into a layer
of photoresist. Photoresist is a light sensitive material similar to the coating on a
regular photographic film. Exposure to light causes changes in its structure and
properties. If the exposure to light causes photoresist to change from a soluble to
insoluble one, it is known as negative actingand the chemical change is called
polymerization. Similarly, if exposure to light causes it change from relatively nonsoluble to much more soluble, it is known as positive acting and the term describing it
is called as photosolubilisation. The exposure radiation is generally UV and E-beam.
Removing the soluble portions with chemical solvents called developers leaves a
pattern on the photoresist depending upon the type of mask used. A mask whose
pattern exists in the opaque regions is called clear field mask. The pattern could also
be coded in reverse, and such masks are known as dark field masks.
The result obtained from the photomasking process from different combinations of mask
and resist polarities is shown in the following table:
The second transfer takes place from the photoresist layer into the wafer surface layer.
The transfer occurs when etchants remove the portion of the wafer's top layer that is not
covered by the photoresist. The chemistry of the photoresists is such that they do not
dissolve in the chemical etching solutions; they are etch resistant; hence the name
photoresists.The etchant generally used to remove silicon dioxide is hydrogen fluoride
(HF).
The choice of mask and resist polarity is a function of the level of dimensional control
and defect protection required to make the circuit work. For example, sharp lines are not
obtainable with negative photoresists while etchants are difficult to handle with positive
photoresists.
After the pattern has been taken on resist, the thin layer needs to be etched. Etching
process is used to etch into a specific layer the circuit pattern that has been defined
during the photomasking process. For example, aluminium connections are obtained
after etching of the aluminium layer.
7. As a final step, the wafer is passivated and openings to the bond pads are etched
to allow for wire bonding. Passivation protects the silicon surface against the
ingress of contaminants than can modify circuit behavior.
Recap
In this lecture you have learnt the following
Motivation
Photolithography
Fabrication Process