RAKESH ASERY(09EC73)

CE Amplifier design on Multisim

Figure: CE Amplifier with voltage divider biasing

Figure: Response of CE amplifier

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Buffer Amplifier design on Multisim

Figure: Buffer Amplifier

Figure: Response of Buffer amplifier

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OBJECT:- Introductuion to Xilinx ISE 7.1i software.
XILINX SOFTWARE
The Xilinx ISE 7.1i software will be used in this text. All menus structures and
screen shots are taken from the ISE 7.2i version. The Integrated Software
Environment (ISE) is the Xilinx design software suite that allows you to take
your design from design entry through Xilinx device programming. The ISE Project
Navigator manages and processes your design through the following steps in the
ISE design flow.
VHDL Design Entry
The Xilinx ISE tools allow the design to be entered several ways including
graphical schematics, state machine diagrams, VHDL, and Verilog.This tutorial
will focus on VHDL entry, but the other methods are similar and can be easily
explored once the reader is comfortable with theISE software.
Starting a project
Start the Xilinx ISE Project Navigator. Choose File ) New Project.A popup dialog
box will appear. Enter tutor1 for Project Name. Forthe Project Location, select the
directory where the project will be stored (i.e., Z:nXProjntutor1) for your project.

Figure 1: The New Project dialog box is used to enter the project and FPGA deviceinformation
required to create a new project.

Creating a design
Choose Project ) New Source. . . . A popup dialog box will appear.Select VHDL
Module from the list on the left and enter top levelfor the File Name. Make sure
the Add to Project option is checkedand click Next.

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The next screen of options allows you to enter the input and output signals for this
module. Leave the default values for Entity Name and Architecture Name. For this
project, only one input and one output are needed. For the input, enter pb for the
Port Name and in for the Direction. Likewise, for the output, enter led1 and out
respectively.
Since both of these signals are only one bit, the MSB and LSB eldscan be left
blank. If a multi-signal bus was being specied, then thebus width would be
specied in these elds. Click Next. A summaryof the new le to be created will be
displayed next. Verify that allof the information is correct. Use the Back button to
return to any

Figure 2: Specify the name and type of the new source file in the New Source dialog box.

Getting to know the Project Navigator

Take a few minutes to familiarize yourself with the Project Navigator layout. As
shown in Figure 2, there are four window panes in the default layout. All text files
(design files, report files, etc.) are displayed in the main window on right-hand side
of the screen. In the upper left hand pane, you may select the Module View,
Snapshot View, or Library View. Click on each of these tabs and look at the
information provided. Then click on Module View to return to the default. Module
View displays the design files in the current project and shows the relationship
between the files. Double-clicking on any design file in the

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Figure 3: Enter the input and output signals for the new VHDL module inthe VHDL Source Definition
dialog box.

Module View window will open up that le in the main window. The Process
View window is displayed in the lower left-hand side.This window provides access
to the pin assignment le, simulator, compiler settings, compilation reports,
compiler controls, and FPGA programmer. Click on the + sign beside each item in
the Process Viewwindow to view the dierent options available.Finally, the
bottom pane is the Console window. All text outputfrom the Project Navigator,
including warning and error messages, aredisplayed here.
Writing the VHDL model
Look at the top level.vhd VHDL file that you generated earlier. Thefirst four lines of code
indicate which VHDL libraries and packages are needed for this VHDL module.
IEEE.STD LOGIC 1164,

Next, you will nd the Architecture statement. This is the sectionwhere the
behavior or functionality of this VHDL module is defined.Enter led1 <= NOT pb;
on a line between begin and end Behavioral;. This line of VHDL code indicates
that an inverter is to be placed between the input pb and the output led1. Choose
file Save to save these changes.

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Figure 4: The Xilinx Project Navigator is the heart of the Xilinx ISE software.

Figure 5: The completed VHDL code for the example project

Checking the VHDL syntax

Make sure the top level.vhd item in the Module View window is highlighted. If it
is not, then single click on it to make it active. In the Process View window,

RAKESH ASERY(09EC73)
choose Synthesize ) Check Syntax (expand the Synthesize item and then doubleclick the Check Syntax option). If the VHDL code in the current le is
syntactically correct, then a green check mark will appear next to the Check Syntax
option in the Process View window. If any syntax warnings or errors are found, a
yellow exclamation point or red \X" respectively will appear. In the case of
warnings or errors, a description of the problem will be displayed in the Console
window. If multiple problems exist, you may have to scroll the text in the Console
window to see all of the comments.
Implementation
After synthesis, you run design implementation, which converts the logical design
into a physical file format that can be downloaded to the selected target device.
From Project Navigator, you can run the implementation process in one step, or
you can run each of the implementation processes separately. Implementation
processes vary depending on whether you are targeting a Field Programmable Gate
Array (FPGA) or a Complex Programmable Logic Device (CPLD).
Verification
You can verify the functionality of your design at several points in the design flow.
You can use simulator software to verify the functionality and timing of your
design or a portion of your design. The simulator interprets VHDL or Verilog code
into circuit functionality and displays logical results of the described HDL to
determine correct circuit operation. Simulation allows you to create and verify
complex functions in a relatively small amount of time. You can also run in-circuit
verification after programming your device.
Device Configuration
After generating a programming file, you configure your device. During
configuration, you generate configuration files and download the programming
files from a host computer to a Xilinx device.
Programming the board
In the Xilinx Project Navigator's Process View window, double-click on the
Configure Device (iMPACT) option under Generate Programming File. This will
open up the programming file in Xilinx's iMPACT program .Right-click on the
green representation of a Xilinx chip and select Program from the shortcut menu.
When the Program Options popup dialog box appears, click OK to program the

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device. When programming is finished, Programming Succeeded should appear in
the main window.

Figure 6: The completed VHDL code for the toggle ip-op example.

RESULT:- I have successfully study introductuion to Xilinx ISE 7.1i software.

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OBJECT:-Design Full Adder using appropriate software like VHDL (xilinx).
Full Adder CODING :entity RAFADDER is
Port ( A : in std_logic;
B : in std_logic;
C : in std_logic;
SUM : out std_logic;
CARRY : out std_logic);
end RAFADDER;
architecture Behavioral of RAFADDER is
begin
SUM <= A XOR B XOR C;
CARRY <= (A AND B) OR (B AND C) OR (C AND A);
end Behavioral;

SCHEMETIC DIAGRAM OF SUM :-

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TRUTH TABLE OF SUM :-

SCHEMETIC DIAGRAM OF CARRY :-

TRUTH TABLE OF CARRY :-

RESULT:- We have successfully design Full Adder.

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OBJECT:-Design Half adder using appropriate software like VHDL (xilinx).
Half adder CODING :entity RAHADDER is
Port ( A : in std_logic;
B : in std_logic;
SUM : out std_logic;
CARRY : out std_logic);
end RAHADDER;
architecture Behavioral of RAHADDER is
begin
SUM <= A XOR B ;
CARRY <= A AND B ;
end Behavioral;

SCHEMETIC DIAGRAM OF SUM :-

TRUTH TABLE :-

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SCHEMATIC DIAGRAMOF CARRY:-

TRUTH TABLE :-

RESULT:- We have successfully design Half adder.

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OBJECT:-Design half substractor using appropriate software like VHDL (xilinx).
Half substractor CODING :entity RAHSUB is
Port ( A : in std_logic;
B : in std_logic;
SUB : out std_logic;
BO : out std_logic);
end RAHSUB;
architecture Behavioral of RAHSUB is
begin
SUM <= A XOR B ;
CARRY <= A AND NOT(B) ;
end Behavioral;

SCHEMATIC DIAGRAM OF SUB :-

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TRUTH TABLE :-

SCHEMATIC DIAGRAM OF BORROW :-

TRUTH TABLE :-

RESULT:- We have successfully design half substractor.

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OBJECT :-Design AND Gate using appropriate software like VHDL (xilinx).

AND Gate CODING :entity AND is

Port ( a : in std_logic;
b : in std_logic;
c : out std_logic);
end AND;
architecture Behavioral of AND is
begin
c <= a AND b ;
end Behavioral;

SCHEMATIC DIAGRAM :-

TRUTH TABLE :-

RESULT:- We have successfully design AND Gate.

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OBJECT :-Design NOR Gate using appropriate software like VHDL (xilinx).
NOR Gate CODING :entity RANOR is
Port ( A : in std_logic;
B : in std_logic;
C : out std_logic);
end RANOR;
architecture Behavioral of RANOR is
begin
C <= A NOR B ;
end Behavioral;

SCHEMATIC DIAGRAM :-

TRUTH TABLE :-

RESULT:- We have successfully design NOR Gate.

RAKESH ASERY(09EC73)
OBJECT :-Design XNOR Gate using appropriate software like VHDL (xilinx).
XNOR Gate CODING :entity RAXNOR is
Port ( A : in std_logic;
B : in std_logic;
C : out std_logic);
end RAXNOR;
architecture Behavioral of RAXNOR is
begin
C <= A XNOR B ;
end Behavioral;

SCHEMATIC DIAGRAM :-

TRUTH TABLE :-

RESULT:- We have successfully design XNOR Gate.

RAKESH ASERY(09EC73)
OBJECT :-Design NAND Gate using appropriate software like VHDL (xilinx).
NAND Gate CODING :entity RANAND is
Port ( A : in std_logic;
B : in std_logic;
C : out std_logic);
end RANAND;
architecture Behavioral of RANAND is
begin
C <= A NAND B ;
end Behavioral;

SCHEMATIC DIAGRAM :-

TRUTH TABLE:-

RESULT:- We have successfully design NAND Gate.

RAKESH ASERY(09EC73)
OBJECT :-Design OR Gate using appropriate software like VHDL (xilinx).
OR Gate CODING :entity RAOR is
Port ( A : in std_logic;
B : in std_logic;
C : out std_logic);
end RAOR;
architecture Behavioral of RAOR is
begin
C <= A OR B ;
end Behavioral;

SCHEMATIC DIAGRAM :-

TRUTH TABLE :-

RESULT:- We have successfully design OR Gate.

RAKESH ASERY(09EC73)
OBJECT :-Design XOR Gate using appropriate software like VHDL (xilinx).
XOR Gate CODING :entity RAXOR is
Port ( A : in std_logic;
B : in std_logic;
C : out std_logic);
end RAXOR;
architecture Behavioral of RAXOR is
begin
C <= A XOR B ;
end Behavioral;

SCHEMATIC DIAGRAM :-

TRUTH TABLE :-

RESULT:- We have successfully design XOR Gate.

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OBJECT :-Design fullsubtractor using appropriate software like VHDL (xilinx).
Fullsubtractor CODING :entity RAFSUB is
Port ( A : in std_logic;
B : in std_logic;
Bin : in std_logic;
Sub : out std_logic;
Bout : out std_logic);
end full_sub;
architecture Behavioral of RAFSUB is
begin
Sub <= A XOR B XOR Bin;
Bout <= ((NOT A) AND B) OR ((NOT A) AND Bin) OR (Bin AND B);
end Behavioral;
SCHEMATIC DIAGRAM :-

TRUTH TABLE :-

RESULT:- We have successfully design fullsubtractor.

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NMOS Amplifier design on Multisim

Figure: NMOS Amplifier with voltage divider biasing

Figure: Response of NMOS amplifier

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OBJECT :-Design 4to1Multiplexer using appropriate software like VHDL (xilinx).
4to1Multiplexer CODING :entity RA41MUX is
Port ( I : in std_logic_vector(3 downto 0);
S : in std_logic_vector(1 downto 0);
O : out std_logic);
end RA41MUX;
architecture Behavioral of RA41MUX is
begin
with S select
O <= I(3) when "11",
I(2) when "10",
I(1) when "01",
I(0) when "00",
I(0) when others;
end Behavioral;
SCHEMATIC DIAGRAM :-

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TRUTH TABLE :-

LOGIC DIAGRAM & K MAP :-

RESULT:- We have successfully design 4to1Multiplexer.

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OBJECT :-Design 8to1Multiplexer using appropriate software like VHDL (xilinx).
8to1Multiplexer CODING :entity RA81MUX is
Port ( I : in std_logic_vector(7 downto 0);
S : in std_logic_vector(2 downto 0);
O : out std_logic);
end RA81MUX;
architecture Behavioral of RA81MUX is
begin
with S select
O <= I(7) when "111",
I(6) when "110",
I(5) when "101",
I(4) when "100",
I(3) when "011",
I(2) when "010",
I(1) when "001",
I(0) when "000",
I(0) when others;
end Behavioral;
SCHEMATIC DIAGRAM :-

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TRUTH TABLE :-

LOGIC DIAGRAM & K MAP :-

RESULT:- We have successfully design 8to1Multiplexer.

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OBJECT :-Design 16to1Multiplexer using appropriate software like VHDL
(xilinx).
16to1Multiplexer CODING :entity RA16TO1MUX is
Port ( W : in std_logic_vector(15 downto 0);
S : in std_logic_vector(3 downto 0);
F : out std_logic);
end RA16TO1MUX;
architecture Behavioral of RA16TO1MUX is
begin
with S select
F <= W(15) when "1111",
W(14) when "1110",
W(13) when "1101",
W(12) when "1100",
W(11) when "1011",
W(10) when "1010",
W(9) when "1001",
W(8) when "1000",
W(7) when "0111",
W(6) when "0110",
W(5) when "0101",
W(4) when "0100",
W(3) when "0011",
W(2) when "0010",
W(1) when "0001",
W(0) when "0000",
W(0) when others;
end Behavioral;

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SCHEMATIC DIAGRAM :-

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TRUTH TABLE :-

RESULT: - We have successfully design 1to16Multiplexer.

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OBJECT :-Design 1t4 Demultiplexer using appropriate software like VHDL
(xilinx).
1to4Demultiplexer CODING :entity RA41DMUX is
Port ( I : in std_logic;
S : in std_logic_vector(1 downto 0);
W0 : out std_logic;
W1 : out std_logic;
W2 : out std_logic;
W3 : out std_logic);
end RA41DMUX;
architecture Behavioral of RA41DMUX is
begin
W3 <= I when S="11";
W2 <= I when S="10";
W1 <= I when S="01";
W0 <= I when S="00";
end Behavioral;
SCHEMATIC DIAGRAM :-

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TRUTH TABLE :-

LOGIC DIAGRAM & K MAP :-

RESULT: - We have successfully design 1to4Demultiplexer.

RAKESH ASERY(09EC73)
OBJECT :-Design 1to8 Demultiplexer using appropriate software like VHDL
(xilinx).
1to8Demultiplexer CODING :entity RA81DMUX is
Port ( I : in std_logic;
S : in std_logic_vector(2 downto 0);
W0 : out std_logic;
W1 : out std_logic;
W2 : out std_logic;
W3 : out std_logic;
W4 : out std_logic;
W5 : out std_logic;
W6 : out std_logic;
W7 : out std_logic);
end RA81DMUX;
architecture Behavioral of RA81DMUX is
begin
W7 <= I when S="111";
W6 <= I when S="110";
W5 <= I when S="101";
W4 <= I when S="100";
W3 <= I when S="011";
W2 <= I when S="010";
W1 <= I when S="001";
W0 <= I when S="000";
end Behavioral;

RAKESH ASERY(09EC73)
SCHEMATIC DIAGRAM:-

TRUTH TABLE:-

LOGIC DIAGRAM & K MAP :-

RESULT:- We have successfully design 1to8 Demultiplexer.

RAKESH ASERY(09EC73)
OBJECT :-Design 1to16 Demultiplexer using appropriate software like VHDL
(xilinx).
1to16 Demultiplexer CODING :entity RA16TO1DMUX is
Port ( D : in std_logic;
S : in std_logic_vector(3 downto 0);
Y0 : out std_logic;
Y1 : out std_logic;
Y2 : out std_logic;
Y3 : out std_logic;
Y4 : out std_logic;
Y5 : out std_logic;
Y6 : out std_logic;
Y7 : out std_logic
Y8 : out std_logic;
Y9 : out std_logic;
Y10 : out std_logic;
Y11 : out std_logic;
Y12 : out std_logic;
Y13 : out std_logic;
Y14 : out std_logic;
Y15 : out std_logic);
end RA16TO1DMUX;
architecture Behavioral of RA16TO1DMUX is
begin
Y15 <= D when S="1111";
Y14 <= D when S="1110";
Y13 <= D when S="1101";
Y12 <= D when S="1100";
Y11 <= D when S="1011";
Y10 <= D when S="1010";
Y9 <= D when S="1001";
Y8 <= D when S="1000";
Y7 <= D when S="0111";

RAKESH ASERY(09EC73)
Y6 <= D when S="0110";
Y5 <= D when S="0101";
Y4 <= D when S="0100";
Y3 <= D when S="0011";
Y2 <= D when S="0010";
Y1 <= D when S="0001";
Y0 <= D when S="0000";
end Behavioral;
SCHEMATIC DIAGRAM:-

RAKESH ASERY(09EC73)
TRUTH TABLE:-

RESULT:- We have successfully design 1to16 Demultiplexer.

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Wein bridge generator design on Multisim

Figure: Wein bridge generator

Figure: Response of Wein bridge generator

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Square wave generator design on Multisim

Figure: Square wave generator

Figure: Response of Square wave generator

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Square wave generator design on Multisim

Figure: Square wave generator

Figure: Response of Square wave generator

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RC phase oscillator design on Multisim

Figure: RC phase oscillator

Figure: Response of RC phase oscillator

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JFET design on Multisim

Figure: JFET source follower

Figure: Response of JFET source follower

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AMV design on Multisim

Figure: AMV using 555IC

Figure: Response of AMV using 555IC

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Mono-stable Multi-vibrator (MMV)

Figure: Mono-stable Multi-vibrator (MMV) using 555 timer IC

Figure: Response of Mono-stable Multi-vibrator using 555 timer

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OBJECT :- To design2x4 Decoder on Xilinx.
2 TO 4 Decoder CODING :entity RA24DEC is
Port ( W : in std_logic_VECTOR(1 downto 0);
En : in std_logic;
Y : out std_logic_VECTOR(0 to 3));
end RA24DEC;
Architecture Behavioral of RA24DEC is
signalEnW : std_logic_vector(2 downto 0);
begin
EnW<= En & W;
with EnW select
Y <= "1000" when "100",
"0100" when "101",
"0010" when "110",
"0001" when "111",
"0000" when others;
End Behavioral;

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Figure: Top level schematic of 2x4 Decoder

Figure: 2x4 Decoder logic diagram

Figure: Truth table of 2x4 Decoder

RESULT:- Thus 2x4 Decoder have been designed successfully.

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OBJECT: - To design3x8 Decoder on Xilinx.
3 TO 8 Decoder CODING :entity RA38DEC is
Port ( W : in std_logic_VECTOR(2 downto 0);
En : in std_logic;
Y : out std_logic_VECTOR(0 to 7));
end RA38DEC;
architecture Behavioral of RA38DEC is
signalEnW : std_logic_vector(3 downto 0);
begin
EnW<= En & W;
with EnW select
Y <= "10000000" when "1000",
"01000000" when "1001",
"00100000" when "1010",
"00010000" when "1011",
"00001000" when "1100",
"00000100" when "1101",
"00000010" when "1110",

"00000001" when "1111",

"00000000" when others;

end Behavioral;

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Figure: Top level schematic of 3x8 Decoder

Figure: 3x8 Decoder logic diagram

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Figure: Truth table of 3x8 Decoder

RESULT:- Thus 3x8 Decoder have been designed successfully.

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OBJECT :- To design 4x16 Decoder on Xilinx.
4 TO16 Decoder CODING :entity RA416DEC is
Port (W : in std_logic_VECTOR(3 downto 0);
En : in std_logic;
Y : out std_logic_VECTOR(0 to 15));
end RA416DEC;
Architecture Behavioral of RA416DEC is
signalEnW : std_logic_vector(4 downto 0);
begin
EnW<= En & W;
with EnW select
Y <= "1000000000000000" when "10000",
"0100000000000000" when "10001",
"0010000000000000" when "10010",
"0001000000000000" when "10011",
"0000100000000000" when "10100",
"0000010000000000" when "10101",

"0000001000000000" when "10110",

"0000000100000000" when "10111",

"0000000010000000" when "11000",

"0000000001000000" when "11001",

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"0000000000100000" when "11010",
"0000000000010000" when "11011",
"0000000000001000" when "11100",
"0000000000000100" when "11101",
"0000000000000010" when "11110",
"0000000000000001" when "11111",
"0000000000000000" when others;
end Behavioral;

Figure: Top level schematic of 4x16 Decoder

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Figure: 4x16 Decoder logic diagram

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Figure: Truth table of 4x16 Decoder

RESULT:- Thus 4x16 Decoder have been designed successfully.

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OBJECT :- To design a 4- bit ALU on Xilinx.

4- bit ALU CODING :entity ALU is

Port ( A : in std_logic_VECTOR(3 downto 0);
B : in std_logic_VECTOR(3 downto 0);
S : in std_logic_VECTOR(3 downto 0);
Y : out std_logic_VECTOR(3 downto 0));
end ALU;
architecture Behavioral of ALU is
begin
process(A,B,S)
begin
case S is
when "0001" => Y <= (A + B);
when "0010" => Y <= (A - B);
when "0011" => Y <= (A * B);
when "0100" => Y <= (A or B);
when "0101" => Y <= (A nor B);
when "0110" => Y <= (A nand B);
when "0111" => Y <= (A and B);
when "1000" => Y <= (not A);

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when "1001" => Y <= (not B);
when "1010" => Y <= (A);
when "1011" => Y <= (B);
when "1100" => Y <= (A xnor B);
when "1101" => Y <= (A xor B);
when others => Y <= "0000";
end case;
end process;
end Behavioral;

Figure: Top level symbol of 4-bit ALU

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Figure : 4-bit ALUdiagram

RESULT:- Thus 4-bit ALU have been designed successfully.

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OBJECT :- To design D-latch/Flip-flop on Xilinx.
D-latch/Flip-flop CODING :entity DFF is
Port ( D : in std_logic;
clk : in std_logic;
Q : out std_logic);
end DFF;
architecture Behavioral of DFF is
begin
process(D,clk)
begin
IF (clk'event and clk = '1') then
Q <= D;
end If;
end process;
end Behavioral;

Figure: Top level symbol of D-latch/Flip-flop

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Figure :D-latch/Flip-flop

Figure : D-latch/Flip-flop logic diagram

Clock
clk
1
1
0

Input
D
0
1
X

Output
Q
0
1
No Change

Figure : Truth table of D Flip-flop

RESULT:- Thus D-latch/Flip-flop have been designed successfully.

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